PCM1727E/2KG4 [TI]
SERIAL INPUT LOADING, DAC WITH PROGRAMMABLE PLL, PDSO24, GREEN, SSOP-24;
| 型号： | PCM1727E/2KG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SERIAL INPUT LOADING, DAC WITH PROGRAMMABLE PLL, PDSO24, GREEN, SSOP-24 输入元件 光电二极管 转换器 |
| 文件： | 总19页 (文件大小：317K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCM1727
PC
M
1727E
49%
FPO
SBAS077A – JANUARY 1997 – REVISED MAY 2007
TM
Stereo Audio
DIGITAL-TO-ANALOG CONVERTER
With Programmable Dual PLL
FEATURES
● ACCEPTS 16-, 20-, OR 24-BIT INPUT DATA
DESCRIPTION
The PCM1727 is a complete, low-cost, stereo audio digital-
to-analog converter (DAC) with a dual phase-locked loop
(PLL) circuit included. PLL-1 derives a fixed 33.8688MHz
(768fS, fS = 44.1kHz) system clock (SCKO-1), and PLL-2
derives both the 384fS (fS = 44.1k/48k/96kHz) system
clock (SCKO-2) and the 768fS (fS = 44.1k/48kHz)/384fS
(fS = 96kHz) system clock (SCKO-3) from an external
27MHz reference frequency. The DAC contains a 3rd-
order Delta-Sigma (∆Σ) modulator, a digital interpolation
filter, and an analog output amplifier. The PCM1727 can
accept 16-, 20-, or 24-bit input data in either normal or I2S
formats.
● COMPLETE STEREO DAC: Includes Digital Filter
and Output Amp
● DYNAMIC RANGE: 92dB
● MULTIPLE SAMPLING FREQUENCIES:
fS = 44.1kHz, 48kHz, 96kHz
● PROGRAMMABLE DUAL PLL CIRCUIT:
27MHz Master Clock Input
● GENERATED SYSTEM CLOCK
SCKO1: 33.8688MHz
SCKO2: 384fS
SCKO3: 768fS (44.1k/48kHz)
384fS (96kHz)
● NORMAL OR I2S™ DATA INPUT FORMATS
The digital filter performs an 8X interpolation function and
includes selectable features such as soft mute, digital
attenuation and digital de-emphasis.
● SELECTABLE FUNCTIONS:
Soft Mute, Analog Output Mode
Digital Attenuator (256 Steps)
Digital De-Emphasis
The PCM1727 is ideal for applications that combine
compressed audio and video data such as DVD, DVD
Audio with CD-DA compatibility, and karaoke DSP.
● +5V SINGLE POWER SUPPLY
Multi-level
Delta-Sigma
Modulator
VOUT
CAP
L
BCKIN
Serial
Low-pass
Filter
DAC
DAC
LRCIN
Input
I/F
8X Oversampling
Digital Filter
with Function
Controller
DIN
Multi-level
Delta-Sigma
Modulator
VOUTR
Low-pass
Filter
ML
MC
MD
Mode
Control
I/F
ZERO
BPZ-Cont.
384fS
Open Drain
RSTB
PLL2
PLL1
Power Supply
OSC
SCKO3 SCKO2 SCKO1
MCKO XT1 XT2
VCP PGND VCA AGND VDD DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SoundPLUS is a trademark of Texas Instruments.
I2S is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1997-2004, Texas Instruments Incorporated
www.ti.com
PIN CONFIGURATION
ELECTROSTATIC
TOP VIEW
SSOP
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to ob-
serve proper handling and installation procedures can
cause damage.
XT1
PGND
VCP
1
2
3
4
5
6
7
8
9
24 XT2
23 DGND
22 VDD
MCKO
RSV
21 SCKO1
20 SCKO2
19 LRCIN
18 DIN
ESD damage can range from subtle performance deg-
radation to complete device failure. Precision integrated
circuits may be more susceptible to damage because
very small parametric changes could cause the device
not to meet its published specifications.
SCKO3
ML
MC
17 BCKIN
16 ZERO
15 CAP
MD
ABSOLUTE MAXIMUM RATINGS(1)
RSTB 10
Power Supply Voltage ...................................................................... +6.5V
+VCC to +VDD Difference ................................................................... ±0.1V
Input Logic Voltage .................................................. –0.3V to (VDD + 0.3V)
Input Current (except power supply) ............................................... ±10mA
Power Dissipation .......................................................................... 300mW
Operating Temperature Range ......................................... –25°C to +85°C
Storage Temperature ...................................................... –55°C to +125°C
Lead Temperature (soldering, 5s).................................................. +260°C
Thermal Resistance, θJA ....................................................................................... +70°C/W
V
OUTR 11
14
VOUTL
AGND 12
13 VCA
PIN ASSIGNMENTS
NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PIN NAME
I/O
DESCRIPTION
1
2
3
4
5
6
7
8
9
10
XT1
PGND
VCP
IN
—
27MHz Crystal or External Clock Input
PLL Ground
—
PLL Power Supply (+5V)
PACKAGE INFORMATION(1)
MCKO
RSV
OUT
—
Buffered Clock Output of Crystal Oscillator
Reserve; This pin should be open.
PACKAGE
SCKO3
ML
OUT
IN
System Clock Out 3; This output is 768fS or 384fS.
Latch Enable Input for Serial Interface Mode(2)
Bit Clock Input for Serial Interface Mode(2)
Serial Data Input for Serial Interface Mode(2)
PRODUCT
PACKAGE
DESIGNATOR
PCM1727E
24-Pin SSOP
DB
MC
IN
MD
IN
NOTE: (1) For the most current package and ordering information, see the
Package Option Addendum at the end of this data sheet, or see the TI website
at www.ti.com.
RSTB
IN
Reset; When this pin is low, the DF and modu-
lator are held in reset.
11
V
OUTR
OUT
Right Channel, Analog Voltage Output of Audio
Signal
12
13
14
AGND
VCA
—
—
Analog Ground
Analog Power Supply (+5V)
V
OUTL
OUT
Left Channel, Analog Voltage Output of Audio
Signal
15
16
CAP
—
Common Pin of Analog Output Amp
ZERO
OUT
Zero Data Flag; This pin is low when the input
data is continuously zero for more than 65,535
cycles of BCKIN(1)
.
17
18
19
20
BCKIN
DIN
IN
IN
Bit Clock Input for Serial Audio Data(3)
Serial Audio Data Input(3)
Left and Right Clock (sampling rate–fS)(3)
LRCIN
SCKO2
IN
OUT
System Clock Out 2; This output is 256fS or
384fS system clock.
21
SCKO1
OUT
System Clock Out 1; This output is 33.8688MHz
system clock.
22
23
24
VDD
DGND
XT2
—
—
—
Digital Power (+5V)
Digital Ground
27MHz Crystal. Connected to GND at external
clock.
NOTES: (1) Open Drain Output.
(2) Schmitt trigger input with internal pull-up resistors.
(3) Schmitt trigger input.
PCM1727
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ELECTRICAL CHARACTERISTICS
All specifications at +25°C, +VCA = +VDD = +VCP = +5V, fS = 44.1kHz, and 16-bit input data, SYSCLK = 384fS, unless otherwise noted.
PCM1727
PARAMETER
RESOLUTION
CONDITIONS
MIN
TYP
MAX
UNITS
16
Bits
DATA FORMAT
Audio Data Interface Format
Data Bit Length
Audio Data Format
Sampling Frequency (fS)
Standard/I2S Selectable
16/20/24 Selectable
MSB First, 2’s Comp
44.1
96
kHz
PLL PERFORMANCE
Master Clock Input Frequency(4)
Generated System Clock
SCKO-1
SCKO-2
SCKO-3
26.73
27
27.27
MHz
768fS (fS = 44.1k)
384fS
768fS (fS = 44.1k/48k), 384fS (fS = 96k)
IOH = 2mA
33.8688
MHz
MHz
MHz
VDC
VDC
ps
16.9344
33.8688
VDD – 0.4
36.8640
36.8640
Output Logic Level
(MCKO, SCKO 1 ~ 3)
Generated SYSCLK Jitter
VOH
VOL
IOL = 4mA
Standard Dev
0.5
±150
Generated SYSCLK Transient(1)
Power-Up Time
Generated SYSCLK Duty Cycle
fM = 27MHz
To Programmed Frequency
fM = 27MHz, CL = 15pF
20
30
60
ms
ms
%
15
50
40
DIGITAL INPUT LOGIC LEVEL
TTL
DYNAMIC PERFORMANCE(2)
THD+N at fS (0dB)
fs = 44.1kHz
fs = 96kHz
fs = 44.1kHz
fs = 96kHz
fs = 44.1kHz
fs = 96kHz
fs = 44.1kHz
fs = 96kHz
fs = 44.1kHz
–89
–87
–31
–29
92
90
94
90
93
–80
dB
dB
dB
dB
dB
dB
dB
dB
dB
THD+N at –60dB
Dynamic Range (EIAJ Method)
Signal-to-Noise Ratio(3) (EIAJ Method)
Channel Separation
90
90
88
DC ACCURACY
Gain Error
Gain Mismatch, Channel-to-Channel
Bipolar Zero Error
±1.0
±1.0
±30
±3.0
±2.0
% of FSR
% of FSR
mV
VOUT = VCC/2 at BPZ
ANALOG OUTPUT
Output Voltage
Center Voltage
Full Scale (–0dB)
0.62 x VCA
VCA/2
VPP
VDC
kΩ
Load Impedance
AC Load
5
DIGITAL FILTER PERFORMANCE
Passband
Stop Band
Passband Ripple
Stop Band Attenuation
Delay Time
0.445
fS
fS
dB
dB
sec
dB
0.555
–35
±0.17
11.125/fS
De-emphasis Error
–0.2
+0.55
INTERNAL ANALOG FILTER
–3dB Bandwidth
Passband Response
100
–0.16
kHz
dB
f = 20kHz
POWER SUPPLY REQUIREMENTS
Voltage Range
Supply Current: ICC + IDD + ICP
VCC = VDD = VCP
fS = 44.1kHz
4.5
5
25
5.5
27
VDC
mA
TEMPERATURE RANGE
Operating
Storage
–25
–55
+85
+125
°C
°C
NOTES: (1) Sysclk transient is the maximum frequency lock time when the PLL frequency is changed.
(2) Dynamic performance specs are tested with 20kHz low pass filter and THD+N specs are tested with 30kHz LPF, 400Hz HPF, Average-Mode.
(3) SNR is tested at Infinite Zero Detection off.
(4) PLL evaluations tested with 1ns maximum jitter on the 27MHz input clock.
PCM1727
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TYPICAL CHARACTERISTICS
At TA = +25°C, VCC = VDD = VCP = +5V, fS = 44.1kHz, 16-bit input data, 384fS, unless otherwise noted. Measurement bandwidth is 20kHz.
DYNAMIC PERFORMANCE
THD+N (0dB) vs TEMPERATURE and
CC = 5V, 384fS
THD+N (0dB) vs POWER SUPPLY VOLTAGE
A = 25°C, 384fS
V
T
–70
–75
–80
–85
–90
–95
–70
–75
–80
–85
–90
–95
f
S = 96k
f
S = 96k
fS = 44.1k
fS = 44.1k
–25
0
25
50
75
85
4.5
5.0
5.5
Temperature (°C)
Power Supply Voltage (V)
POWER SUPPLY CURRENT vs SAMPLING RATE (fS)
THD+N (0dB) vs SAMPLING RATE (fS)
CC = 5V, TA = 25°C
VCC = 5V, TA = 25°C
V
35
30
25
20
15
–70
–75
–80
–85
–90
–95
44.1k
48k
96k
44.1k
48k
96k
Sampling Rate, fS (Hz)
Sampling Rate, fS (Hz)
PCM1727
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TYPICAL CHARACTERISTICS (Cont.)
DIGITAL FILTER
PASSBAND RIPPLE CHARACTERISTIC
OVERALL FREQUENCY CHARACTERISTIC
0
0
–0.2
–0.4
–0.6
–0.8
–1
–20
–40
–60
–80
–100
0
0.4536fS
1.3605fS
2.2675fS
3.1745fS
4.0815fS
0
0.1134fS
0.2268fS
0.3402fS
0.4535fS
Frequency (Hz)
Frequency (Hz)
DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz)
DE-EMPHASIS ERROR (44.1kHz)
0
–2
0.6
0.4
–4
0.2
–6
0
–8
–10
–12
–0.2
–0.4
–0.6
0
5k
10k
15k
20k
25k
0
4999.8375
9999.675
14999.5125
19999.35
Frequency (Hz)
Frequency (Hz)
DE-EMPHASIS FREQUENCY RESPONSE (48kHz)
DE-EMPHASIS ERROR (48kHz)
0
–2
0.6
0.4
–4
0.2
–6
0
–8
–10
–12
–0.2
–0.4
–0.6
0
5k
10k
15k
20k
25k
0
5442
10884
16326
21768
Frequency (Hz)
Frequency (Hz)
PCM1727
SBAS077A
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TYPICAL CONNECTION DIAGRAM
DUAL PLL CIRCUIT
Figure 1 illustrates the typical connection diagram for the
PCM1727 in a DVD Audio application. The 27MHz master
video clock (fM) drives XT1 (pin 1) of the PCM1727. A
programmable system clock is generated by the PCM1727
PLL, with SCKO2 used to drive the MPEG2 decoder system
clock input, SCKO1 used to drive the CD-DA DSP system
clock input, and SCKO3 used to drive Karaoke DSP system
clock input. The standard audio signals (data, bit clock, and
word clock) are generated in the decoder from the PCM1727
system clock, providing synchronization of audio and video
signals.
The PCM1727 has a programmable internal DUAL PLL
circuit, as shown in Figure 2. The PLL is designed to accept
a 27MHz master clock or crystal oscillator and generate all
internal system clocks required to operate the digital filter
and ∆Σ modulator, at 384fS. If an external master clock is
used, XT2 must be connected to ground. In both cases, the
signal amplitude on XT1 must satisfy the specification
described in Figure 3. Therefore, careful C1 and C2 determi-
nation is required to keep this specification satisfied when
using a crystal oscillator. The PLL will directly track any
variations in the master clock frequency, and jitter on the
+5V Analog
2
23
22
VDD VCP
VOUT
CAP
3
PGND DGND
DIN
18
17
19
20
14
15
Analog
Mute
Post
LPF
L
DATA
BCK
Lch Analog Out
Rch Analog Out
MPEG
Decoder
BCKIN
+
10µF
LRCIN
LRCK
SCI
SCKO2
11
16
Analog
Mute
Post
LPF
VOUT
R
Buffer
384fS
ZERO
Buffer
CD-DA
21
SCKO1
DSP
33.8688M
Buffer
PCM1727
Karaoke
DSP
6
1
SCKO3
768/384fS
27MHz
Master
Clock
7
XT1
XT2
STRB
SCKO
SDO
PIO
ML
MC
8
27MHz CLK OUT
System
Controller
24
9
MD
10
RSTB
AGND
12
VCA
13
+5V Analog
FIGURE 1. Connection Diagram for External Master Clock in a Typical MPEG2 Application.
Frequency Control
Internal
System
Clock
PLL2
N Counter
Phase Detector
and Loop Filter
Data
ROM
VCO
VCO
M Counter
PLL1
Counter P
M Counter
N Counter
Phase Detector
and Loop Filter
Oscillator
24
XT2
1
4
21
6
20
XT1
MCKO
27MHz
SCKO1
33.8688MHz
SCKO3
768fs/384fs
SCKO2
384fs
FIGURE 2. PLL Block Diagram.
PCM1727
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1/27MHz
t
t
CH: 10ns (min)
CL: 15ns (min)
IIH (VIH = VDD) : 4mA max
tCH
I
IL (VIL = 0) : 700µA max
XT1
1.2V
0.4V
tCL
FIGURE 3. XT1 Input Timing.
MCKO
MCKO
27MHz
Out
Buffer
27MHz Internal Master Clock
27MHz Internal Master Clock
C1
X’tal
XT1
XT2
XT1
XT2
External Clock
R
R
C2
C1, C2 = 10 to 33pF
PCM1727
PCM1727
CRYSTAL RESONATOR CONNECTION
EXTERNAL CLOCK INPUT
FIGURE 4. System Clock Connection.
1/fS
L_ch
R_ch
LRCIN (pin 19)
BCKIN (pin 17)
AUDIO DATA WORD = 16-BIT
DIN (pin 18)
14 15 16
14 15 16
14 15 16
1
3
2
3
1
3
2
3
MSB
LSB
MSB
LSB
AUDIO DATA WORD = 20-BIT
DIN (pin 18)
18 19 20
1
1
2
2
18 19 20
1
1
2
2
18 19 20
MSB
3
LSB
MSB
3
LSB
AUDIO DATA WORD = 24-BIT
DIN (pin 18)
23 24
22 23 24
22 23 24
MSB
LSB
MSB
LSB
FIGURE 5. Normal Data Input Timing.
PCM1727
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1/fS
L_ch
R_ch
LRCIN (pin 19)
BCKIN (pin 17)
AUDIO DATA WORD = 16-BIT
DIN (pin 18)
14 15 16
LSB
14 15 16
LSB
1
1
1
2
2
2
1
1
1
2
2
2
3
1
1
1
2
2
2
3
MSB
3
MSB
3
AUDIO DATA WORD = 20-BIT
DIN (pin 18)
18 19 20
18 19 20
MSB
3
LSB
MSB
3
LSB
AUDIO DATA WORD = 24-BIT
DIN (pin 18)
22 23 24
22 23 24
MSB
LSB
MSB
LSB
FIGURE 6. I2S Data Input Timing.
LRCKIN
1.4V
1.4V
tBCH
tBCL
tLB
BCKIN
tBL
tBCY
1.4V
DIN
tDS
tDH
BCKIN Pulse Cycle Time
BCKIN Pulse Width High
BCKIN Pulse Width Low
: tBCY
: 100ns (min)
: tBCH
: tBCL
: 50ns (min)
: 50ns (min)
: 30ns (min)
: 30ns (min)
: 30ns (min)
: 30ns (min)
BCKIN Rising Edge to LRCIN Edge : tBL
LRCIN Edge to BCKIN Rising Edge : tLB
DIN Set-up Time
DIN Hold Time
: tDS
: tDH
FIGURE 7. Audio Data Input Timing.
system clock is specified at 150ps typical. Figure 3 illus-
trates the timing requirements for the 27MHz master clock.
Figure 4 illustrates the system clock connections for an
external clock or crystal oscillator.
Sampling Frequencies-LRCIN (kHz)
Standard Sampling Freq
44.1
48
96
Double of Standard Sampling Freq
TABLE I. Sampling Frequencies.
The PCM1727 internal PLL can be programmed for three
different sampling frequencies (LRCIN), as shown in Table
I. The internal sampling clocks generated by the various
programmed frequencies are shown in Table II. The system
clock output frequency for PCM1727 is 100% accurate.
Sampling
Frequency
(LRCIN)
SCKO2
SCKO3
System Clock
System Clock
44.1kHz
48kHz
96kHz
Standard
Standard
Double
16.9344MHz
18.4320MHz
36.8640MHz
33.8688MHz
36.8640MHz
36.8640MHz
To provide MCKO clock and SCKO1, SCKO2, SCKO3
clocks for external circuits, an external buffer may be used
to avoid degrading audio performance (as shown in the
connection diagram, in Figure 1).
TABLE II. Sampling Frequencies vs Internal System Clock
(= Output Frequencies of Dual PLL).
PCM1727
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MAPPING OF PROGRAM REGISTERS
B15
res
B14
res
B13
res
B12
res
B11
res
B10
A1
B9
A0
B8
B7
B6
B5
B4
B3
B2
B1
B0
MODE0
MODE1
MODE2
MODE3
LDL
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
res
res
res
res
res
res
res
res
res
res
res
res
res
res
res
A1
A1
A1
A0
A0
A0
LDR
PL3
IZD
AR7
PL2
SF1
AR6
PL1
SF0
AR5
PL0
AR4
IW1
AR3
IW0
res
AR2
OPE
ATC
AR1
AR0
DEM MUT
LRP
I2S
DSR1 DSR0
REGISTER
NAME
BIT
NAME
SPECIAL FUNCTIONS
DESCRIPTION
DAC Attenuation Data for Lch
Attenuation Data Load Control for Lch
Register Address
The PCM1727 includes several special functions, including
digital attenuation, digital de-emphasis, soft mute, data for-
mat selection and input word resolution. These functions are
controlled using a three-wire interface. MD (pin 9) is used
for the program data, MC (pin 8) is used to clock in the
program data, and ML (pin 7) is used to latch in the program
data. Table III lists the selectable special functions.
Register 0
Register 1
Register 2
AL (7:0)
LDL
A (1:0)
res
Reserved, should be “L”
AR (7:0)
LDL
A (1:0)
res
DAC Attenuation Data for Rch
Attenuation Data Load Control for Rch
Register Address
Reserved, should be “L”
MUT
DEM
Left and Right DACs Soft Mute Control
De-emphasis Control
OPE
Left and Right DACs Operation Control
Input Audio Data Bit Select
Output Mode Select
Register Address
Reserved, should be “L”
FUNCTION
DEFAULT MODE
IW (1:0)
PL (3:0)
A (1:0)
res
Input Audio Data Format Selection
Normal Format
I2S Format
Normal Format
Input Audio Data Bit Selection
16/20/24 Bits
Register 3
I2S
LRP
ATC
DSR (1:0)
SF (1:0)
IZD
A (1:0)
res
Audio Data Format Select
Polarity of LRCIN (pin 19) Select
Attenuator Control
Double Sampling Rate Select
Sampling Rate Select
Infinite Zero Detection Circuit Control
Register Address
Reserved, should be “L”
16 Bits
Input LRCIN Polarity Selection
Lch/Rch = High/Low
Lch/Rch = Low/High
Lch/Rch = High/Low
De-emphasis Control
Soft Mute Control
OFF
OFF
Attenuation Control
Lch, Rch Individually
Lch, Rch Common
0dB
Lch, Rch Individually Fixed
TABLE IV. Internal Register Mapping.
Infinite Zero Detection Circuit Control
Operation Enable (OPE)
OFF
REGISTER 0 (A1 = 0, A0 = 0)
Enabled
Sampling Rate Selection
Standard Sampling Rate—44.1/48kHz
Double Sampling Rate—96kHz
Sampling Frequency
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
Standard Sampling Rate
44.1kHz
44.1kHz Group
Register 0 is used to control left channel attenuation. Bits
0 - 7 (AL0 - AL7) are used to determine the attenuation
level. The level of attenuation is given by:
48kHz Group
Analog Output Mode
L, R, Mono, Mute
Stereo
TABLE III. Selectable Functions.
ATT = [20 log10 (ATT_DATA/255)] dB
PROGRAM REGISTER BIT MAPPING
ATTENUATION DATA LOAD CONTROL
Bit 8 (LDL) is used to control the loading of attenuation data
in B0:B7. When LDL is set to 0, attenuation data will be
loaded into AL0:AL7, but it will not affect the attenuation
level until LDL is set to 1. LDR in Register 1 has the same
function for right channel attenuation.
The PCM1727 special functions are controlled using four
program registers which are 16 bits long. These registers are
all loaded using MD. After the 16 data bits are clocked in,
ML is used to latch in the data to the appropriate register.
Table IV shows the complete mapping of the four registers
and Figure 8 illustrates the serial interface timing.
PCM1727
SBAS077A
9
www.ti.com
Attenuation Level (ATT) can be controlled as following
Resistor set AL (R) (7:0).
SOFTWARE
MODE
INPUT
DATA INPUT
DAC OUTPUT
AL (R) (7:0)
ATT LEVEL
Zero
Other
Zero
Controlled by OPE and IZD
Controlled by OPE and IZD
Forced to BPZ(1)
Enabled
Enabled
Disabled
Disabled
RSTB = HIGH
RSTB = LOW
00h
01h
.
–∞dB (Mute)
–48.16dB
Other
Forced to BPZ(1)
.
TABLE VII. Reset (RSTB) Function.
NOTE: (1) ∆∑ is disconnected from output amplifier. (2) ∆∑ is connected to
output amplifier.
.
.
.
.
FEh
FFh
–0.07dB
0dB
Bits 3 (IW0) and 4 (IW1) are used to determine input word
resolution. PCM1727 can be set up for input word resolu-
tions of 16, 20, or 24 bits:
REGISTER 1 (A1 = 0, A0 = 1)
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
Bit 4 (IW1)
Bit 3 (IW0)
Input Resolution
0
0
1
1
0
1
0
1
16-bit Data Word
20-bit Data Word
24-bit Data Word
Reserved
Register 1 is used to control right channel attenuation. As
in Register 1, bits 0 - 7 (AR0 - AR7) control the level of
attenuation.
Bits 5, 6, 7, and 8 (PL0:3) are used to control output format.
The output of PCM1727 can be programmed for 16 different
states, as shown in Table VIII.
REGISTER 2 (A1 = 1, A0 = 0)
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3
B2 B1
B0
res res res res res A1 A0 PL3 PL2 PL1 PL0 IW1 IW0 OPE DEM MUTE
PL0 PL1 PL2 PL3 Lch OUTPUT
Rch OUTPUT
NOTE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MUTE
MUTE
MUTE
Register 2 is used to control soft mute, de-emphasis, opera-
tion enable, input resolution, and output format. Bit 0 is used
for soft mute: a HIGH level on bit 0 will cause the output to
be muted (this is ramped down in the digital domain, so no
click is audible). Bit 1 is used to control de-emphasis. A
LOW level on bit 1 disables de-emphasis, while a HIGH
level enables de-emphasis.
MUTE
R
MUTE
L
MUTE
(L + R)/2
R
MUTE
R
R
R
L
(L + R)/2
MUTE
R
REVERSE
STEREO
R
L
L
Bit 2, (OPE) is used for operational control. Table V illus-
trates the features controlled by OPE.
L
L
L
(L + R)/2
MUTE
R
(L + R)/2
(L + R)/2
(L + R)/2
(L + R)/2
SOFTWARE MODE
DATA INPUT
DAC OUTPUT
INPUT
L
Zero
Other
Zero
Forced to BPZ(1)
Forced to BPZ(1)
Controlled by IZD
Normal
Enabled
Enabled
Enabled
Enabled
OPE = 1
OPE = 0
(L + R)/2
MONO
TABLE VIII. Programmable Output Format.
Other
TABLE V. Operation Enable (OPE) Function.
REGISTER 3 (A1 = 1, A0 = 1)
OPE controls the operation of the DAC: when OPE is LOW,
the DAC will convert all non-zero input data. If the input
data is continuously zero for 65, 536 cycles of BCKIN, the
output will be forced to zero only if IZD is HIGH. When
OPE is HIGH, the output of the DAC will be forced to
bipolar zero, irrespective of any input data.
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
res res res res res A1 A0 IZD SF1 SF0 DSR1 DSR0 res ATC LRP I2S
Register 3 is used to control input data format and polarity,
attenuation channel control, system clock frequency, sam-
pling frequency and infinite zero detection.
Bits 0 (I2S) and 1 (LRP) are used to control the input data
format. A LOW on bit 0 sets the format to Normal (MSB-
first, right-justified Japanese format) and a HIGH sets the
format to I2S (Philips serial data protocol). Bit 1 (LRP) is
used to select the polarity of LRCIN (sample rate clock).
When bit 1 is LOW, left channel data are assumed when
DATA INPUT
DAC OUTPUT
Zero
Other
Zero
Forced to BPZ(1)
Normal
IZD = 1
IZD = 0
Zero(2)
Other
Normal
TABLE VI. Infinite Zero Detection (IZD) Function.
PCM1727
10
SBAS077A
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LRCIN is in a HIGH phase and right channel data are
assumed when LRCIN is in a LOW phase. When bit 1 is
HIGH, the polarity assumption is reversed.
SF1
SF0
Sampling Frequency
0
0
1
1
0
1
0
1
44.1kHz group
44.1kHz
48/96kHz
Reserved
Reserved
48kHz group
Reserved
Bit 2 (ATC) is used for controlling the attenuator. When
bit 2 is HIGH, the attenuation data loaded in program
Register 0 are used for both left and right channels. When
bit 2 is LOW, the attenuation data for each register are
applied separately to left and right channels.
Reserved
Bit 8 is used to control the infinite zero detection function
(IZD).
When IZD is LOW, the zero detect circuit is off. Under
this condition, no automatic muting will occur if the input
is continuously zero. When IZD is HIGH, the zero detect
feature is enabled. If the input data is continuously zero for
65, 536 cycles of BCKIN, the output will be immediately
forced to a bipolar zero state (VCC/2). The zero detection
feature is used to avoid noise which may occur when the
input is DC. When the output is forced to bipolar zero,
there may be an audible click. PCM1727 allows the zero
detect feature to be disabled so the user can implement an
external muting circuit.
Bits 4 (DSR0) and 5 (DSR1) are used to control multiples
of the sampling rate:
DSR1
DSR0
Multiple
0
0
1
1
0
1
0
1
Normal
Double
Reserved
Reserved
44.1/48kHz
96kHz
Reserved
Reserved
Bits 6 (SF0) and 7 (SF1) are used to select the sampling
frequency. Frequency selection must be made with an
interval time greater than 20µs.
ML (pin 7)
MC (pin 8)
MD (pin 9)
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
FIGURE 8. Three-Wire Serial Interface.
tMLH
tMLH
tMLS
1.4V
1.4V
ML
tMCH
tMCL
tMLL
MC
tMCY
LSB
MD
1.4V
tMDS
tMDH
MC Pulse Cycle Time
MC Pulse Width LOW
MC Pulse Width HIGH
MD Setup Time
tMCY
tMCL
tMCH
tMDS
tMDH
tMLL
tMLH
tMLS
tMLH
100ns (min)
40ns (min)
40ns (min)
40ns (min)
40ns (min)
40ns + 1SYSCLK (min)
40ns + 1SYSCLK (min)
40ns (min)
MD Hold Time
ML Low Level Time
ML High Level Time
ML Setup Time
ML Hold Time
40ns (min)
SYSCLK: 1/384fS
FIGURE 9. Program Register Input Timing.
PCM1727
SBAS077A
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OUTPUT FILTERING
APPLICATION
CONSIDERATIONS
DELAY TIME
For testing purposes, all dynamic tests are done on the
PCM1727 using a 20kHz low-pass filter. This filter limits
the measured bandwidth for THD+N, etc. to 20kHz. Failure
to use such a filter will result in higher THD+N and lower
SNR and Dynamic Range readings than are found in the
specifications. The low-pass filter removes out-of-band noise.
Although not audible, it may affect dynamic specification
numbers.
There is a finite delay time in delta-sigma converters. In
analog-to-digital converters, this is commonly referred to as
latency. For a delta-sigma DAC, delay time is determined by
the order number of the FIR filter stage, and the chosen
sampling rate. The following equation expresses the delay
time of the PCM1727:
The performance of the internal low-pass filter from DC to
24kHz is shown in Figure 10. The higher frequency rolloff
of the filter is shown in Figure 11. If an application has the
PCM1727 driving a wideband amplifier, it is recommended
to use an external low-pass filter. A simple 3rd-order filter
is shown in Figure 12. For some applications, a passive RC
filter or 2nd-order filter may be adequate.
tD = 11.125 x 1/fS
For fS = 44.1kHz, tD = 11.125/44.1kHz = 251.4µs
Applications using data from a disc or tape source, such as
CD audio, DVD audio, Video CD, DAT, Minidisc, etc.,
generally are not affected by delay time.
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(10Hz~10MHz)
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(20Hz~24kHz, Expanded Scale)
10
5
0
1.0
0.5
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
0
–0.5
–1.0
10
100
1k
10k
100k
1M
10M
20
100
1k
10k
24k
Frequency (Hz)
Frequency (Hz)
FIGURE 11. Low-Pass Filter Wideband Frequency Response.
FIGURE 10. Low-Pass Filter Frequency Response.
GAIN vs FREQUENCY
90
6
Gain
–14
–34
–54
–74
–94
0
1500pF
–90
OPA604
+
10kΩ
10kΩ
10kΩ
–180
Phase
VSIN
680pF
100pF
–
–270
–360
100
1k
10k
100k
1M
Frequency (Hz)
FIGURE 12. 3rd-Order Low-Pass Filter.
PCM1727
12
SBAS077A
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Reset
common +5V power supply for all three power pins. If
separate supplies are used without a common connection,
the delta between the supplies during ramp-up time must be
less than 0.3V. An application circuit to avoid a power-on
latch-up condition is shown in Figure 15.
The PCM1727 has both an internal power-on reset circuit
and the RSTB pin (pin 10) which accepts an external forced
reset by RSTB = LOW. For internal power-on reset, initial-
ize (reset) is done automatically at power on VDD > 2.2V
(typ). During internal reset = LOW, the output of the DAC
is invalid and the analog outputs are forced to VCC/2. Figure
13 illustrates the timing of the internal power-on reset.
The PCM1727 accepts an external forced reset when
RSTB = L. When RSTB = L, the output of the DAC is invalid
and the analog outputs are forced to VCC/2 after internal
initialization (1024 system clocks count after RSTB = H.)
Figure 14 illustrates the timing of the RSTB reset pin.
Digital
Power Supply
Analog
Power Supply
For system applications, the power-up time of the internal
PLL circuit to provide a stable system clock output, is
approximately 1024 system clocks plus a 15ms transient
time.
VDD
VCP VCA
AGND
DGND
POWER SUPPLY
CONNECTIONS
FIGURE 15. Latch-up Prevention Circuit.
The PCM1727 has three power supply connections: digital
(VDD), analog (VCA), and PLL (VCP). Each connection also
has a separate ground return pin. It is acceptable to use a
2.6V
2.2V
1.8V
VCC/VDD
Reset
Reset Removal
Internal Reset
SCKO2 Clock
1024 system (SCKO2) clocks
FIGURE 13. Internal Power-On Reset Timing.
RSTB
50% of VDD
(1)
tRST
Reset
Reset Removal
Internal Reset
SCKO2 Clock
1024 system (SCKO2) clocks
NOTE: (1) tRST = 20ns min
FIGURE 14. RSTB-Pin Reset Timing.
PCM1727
SBAS077A
13
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BYPASSING POWER SUPPLIES
The combined oversampling rate of the delta-sigma modu-
lator and the internal 8X interpolation filter is 48fS for a
384fS system clock. The theoretical quantization noise per-
formance of the 5-level delta-sigma modulator is shown in
Figure 17.
The power supplies should be bypassed as close as
possible to the unit. Refer to Figure 18 for optimal values of
bypass capacitors. It is also recommended to include a
0.1µF ceramic capacitor in parallel with the 10µF tantalum
capacitor.
THEORY OF OPERATION
The delta-sigma section of the PCM1727 is based on a
5-level amplitude quantizer and a 3rd-order noise shaper.
This section converts the oversampled input data to 5-level
delta-sigma format.
AC-3 APPLICATION CIRCUIT
A typical application for the PCM1727 is AC-3 5.1 channel
audio decoding and playback. This circuit uses the PCM1727
to develop the audio system clock from the 27MHz video
clock, with the SCKO2 pin used to drive the AC-3 decoder
and two PCM1720 units, the non-PLL version of the
PCM1723 and PCM1727.
A block diagram of the 5-level delta-sigma modulator is
shown in Figure 16. This 5-level delta-sigma modulator has
the advantage of stability and clock jitter sensitivity over the
typical one-bit (2 level) delta-sigma modulator.
+
+
+
+
+
+
Z–1
Z–1
Z–1
In
8fS
18-Bit
–
–
+
+
+
5-level Quantizer
4
3
2
1
0
Out
48fS (384fS)
FIGURE 16. 5-Level ∆Σ Modulator Block Diagram.
3rd ORDER ∆Σ MODULATOR
20
0
–20
–40
–60
–80
–100
–120
–140
–160
0
5
10
15
20
25
Frequency (kHz)
FIGURE 17. Quantization Noise Spectrum.
PCM1727
14
SBAS077A
www.ti.com
(1)
+5V Analog
20
GNDD
BCKIN
19
VDD
Post
Low Pass
Filter
14
16
15
12
13
Analog
Mute
Left-Channel
Front Speaker
BCK
VOUTL
AC-3
Audio
Decoder
LRCIN
DIN
LRCK
CAP
DO_0
DO_1
DO_2
+
10µF
PCM1720
Post
Low Pass
Filter
9
Analog
Mute
Right-Channel
Front Speaker
2
6
5
4
7
VOUTR
SCKI
MD
SYSCKI
10kΩ
+5V Analog
MC
8
Mute
Control
ZERO
ML
17
TEST
11
RSTB
GNDA
10
VCA
(1)
+5V Analog
(1)
+5V Analog
20
GNDD
BCKIN
19
VDD
OUTL
Post
Low Pass
Filter
14
16
15
12
13
Analog
Mute
Left-Channel
Surround Speaker
V
LRCIN
DIN
CAP
+
10µF
PCM1720
Post
Low Pass
Filter
9
Analog
Mute
Left-Channel
Surround Speaker
2
6
5
4
7
VOUT
SCKI
MD
MPU
SDO
SCO
10kΩ
+5V Analog
MC
8
Mute
Control
ZERO
STROBE_0
RESET
ML
17
TEST
11
RSTB
GNDA
VCA
10
STROBE_1
STROBE_2
(1)
+5V Analog
(1)
+5V Analog
23
22
21
3
PGND DGND VDD VDP
Post
Low Pass
Filter
17
19
18
9
14
15
Analog
Mute
BCKIN
LRCIN
DIN
V
OUTL
Center Channel
CAP
+
10µF
MD
8
7
MC
PCM1727
Post
Low Pass
Filter
11
ML
Analog
Mute
VOUT
Sub-Woofer
10
20
RSTB
10kΩ
Buffer
Buffer
SCKO2
+5V Analog
16
24
1
Mute
Control
ZERO
Signal
Processor
21
6
SCKO1
SCKO3
XT2
XT1
Buffer
27MHz Master Clock Input
+5V Analog
VCA
Signal
Processor
GNDA
12
13
(1)
NOTE: (1) Bypass Capacitor, 1µF ~ 10µF + 0.1µ.
FIGURE 18. Connection Diagram for a 6-Channel AC-3 Application.
PCM1727
SBAS077A
15
www.ti.com
Revision History
DATE
REVISION PAGE
SECTION
DESCRIPTION
—
Entire Document
Updated format and added overbars to RSTB and ZERO.
Added “Selectable” to Audio Data Interface Format typical value column.
Deleted “Selectable” from Audio Data Format unit column.
Changed “XT2 should be connected” to “XT2 must be connected.”
Added sentence regarding XT1 signal amplitude and C1, C2 determination.
Changed 2.0V/0.8V to 1.2V/0.4V.
2
6
Electrical Characteristics
Dual PLL Circuit
5/07
A
7
Figure 3
Dual PLL Circuit
Register 3
8
Deleted paragraph regarding frequency error.
10
11
15
Changed B3 from “YES” to “res” (typo).
Register 3
Added sentence to Bit 6 regarding interval time must be greater than 20µs.
Changed Figure 18.
Figure 18
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
PCM1727
16
SBAS077A
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jun-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PCM1727E
ACTIVE
SSOP
DB
24
58 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCM1727E/2KG4
PCM1727EG4
ACTIVE
ACTIVE
SSOP
SSOP
DB
DB
24
24
TBD
Call TI
Call TI
58 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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