PCM1740E-2/2K [TI]
94dB SNR Stereo DAC with Programmable PLL&VCXO 24-SSOP;
| 型号： | PCM1740E-2/2K |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 94dB SNR Stereo DAC with Programmable PLL&VCXO 24-SSOP 光电二极管 石英晶振 压控振荡器 转换器 |
| 文件： | 总25页 (文件大小：524K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCM1740
P
C
M
1
7
4
0
SBAS128B – JANUARY 2000 – REVISED MAY 2007
TM
Stereo Audio
DIGITAL-TO-ANALOG CONVERTER
with VCXO and PLL
APPLICATIONS
● SET-TOP BOXES
FEATURES
● COMPLETE DELTA-SIGMA STEREO DAC
● DIGITAL BROADCAST RECEIVERS
● VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR:
27MHz ±150ppm Output with 0V to 3V Input
● PROGRAMMABLE PLL
DESCRIPTION
256fS or 384fS Audio System Clock Output
The PCM1740 is a complete stereo audio digital-to-
analog converter with on-chip PLL and VCXO. The
PCM1740 is designed specifically for set-top box applica-
tions requiring high-quality audio playback, a precision
tuned 27MHz master clock source, and support for mul-
tiple audio-sampling frequencies.
● DYNAMIC PERFORMANCE:
Dynamic Range: 94dB
SNR: 94dB
THD+N: –89dB
● SAMPLING FREQUENCIES:
16kHz, 22.05kHz, 24kHz
32kHz, 44.1kHz, 48kHz
64kHz, 88.2kHz, 96kHz
The stereo digital-to-analog converter (DAC) uses multi-
bit, delta-sigma architecture, which includes an 8x inter-
polation filter, 3rd-order noise shaping, 5-level amplitude
quantization, and an analog low-pass filter. The PCM1740
includes a number of user-programmable functions, which
are accessed via a standard I2C-Bus interface.
● SERIAL AUDIO INTERFACE:
Standard or I2S™ Data Formats
16-, 20-, or 24-Bit Data
● I2C-BUS™ INTERFACE FOR CONTROL
REGISTERS:
DAC
Slave Receiver Operation
7-Bit Addressing
Standard Transfer Rate (up to 100kbps)
● PROGRAMMABLE CONTROLS:
Digital Attenuation (256 steps)
Soft Mute
BCK
LRCK
DATA
8x
VOUT
L
PCM
Audio
I/F
(L)
Oversampling
Digital Filter
and
Low-Pass
Filter
VCOM
and Amp
Sub-Functions
Process
DAC
(R)
VOUT
R
SCL
SDA
AD1
AD0
I2C
I/F
and
ZERO
REGs
SCKO
(256fS/384fS)
Counter N
Counter M
XTUN
Phase
Detector
Infinite Zero Detect Mute
De-Emphasis (32kHz, 44.1kHz, 48kHz)
DAC Output Mode
LPF
VCO
XT1
27MHz
Crystal
MCKO
(27MHz)
VCXO
XT2
RST
● SINGLE +5V SUPPLY
Reset
Power Supply
● SMALL SSOP-24 PACKAGE
VPP PGND VCC AGND VDD DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SoundPLUS is a trademark of Texas Instruments.
I2C-Bus, I2C, and I2S are trademarks of NXP B.V.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2000-2007, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause
damage.
Power Supply Voltage(2) ................................................................... +6.5V
Supply Voltage Differences(3) ........................................................... ±0.1V
GND Voltage Differences(4) .............................................................. ±0.1V
Digital Input Voltage ................................................. –0.3V to (VDD + 0.3V)
Analog Input Voltage................................................ –0.3V to (VCC + 0.3V)
Input Current (any pins except supplies) ........................................ ±10mA
Operating Temperature Range ......................................... –25°C to +85°C
Storage Temperature ...................................................... –55°C to +125°C
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 5s).................................................. +260°C
Package Temperature (IR reflow, peak, 10s) ................................ +235°C
ESDdamagecanrangefromsubtleperformancedegrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTES: (1) Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability. (2) VCC, VDD, VPP
.
(3) Among VCC, VDD, VPP. (4) Among AGND, DGND, and PGND.
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA
PRODUCT
PACKAGE-LEAD
PCM1740E
"
SSOP-24
"
DB
"
–25°C to +85°C
PCM1740E
PCM1740E
PCM1740E
Rails, 58
"
PCM1740E/2K
Tape and Reel, 2000
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website at www.ti.com.
PIN CONFIGURATION
PIN ASSIGNMENTS
Top View
SSOP
PIN
NAME
I/O
FUNCTION
1
2
XT1
PGND
XTUN
VPP
—
—
IN
—
27MHz Crystal connection.
PLL and VCXO ground.
XT1
PGND
XTUN
VPP
1
2
3
4
5
6
7
8
9
24 XT2
3
VCXO tune, tuning voltage range from 0V to 3V.
PLL and VCXO power supply, +5V.
4
23 DGND
22 VDD
5
MCKO
AD0
OUT Buffered clock output of VCXO.
6
IN
IN
IN
Device address pin for I2C-BUS.(1)
Device address pin for I2C-BUS.(1)
Bit clock input for I2C-BUS interface.
7
AD1
21 SCKO
20 RSV
19 LRCK
18 DATA
17 BCK
16 ZERO
15 VCOM
8
SCL
MCKO
AD0
9
SDA
RST
IN/OUT Serial data for I2C-BUS interface.
IN
Reset, active LOW.(2)
OUT Right-channel analog voltage output.
10
11
12
13
14
15
16
17
18
19
PCM1740
VOUT
R
AD1
AGND
VCC
—
—
Analog ground.
Analog power supply, +5V.
SCL
V
OUTL
OUT Left-channel analog voltage output.
DC common-mode voltage output.
OUT Zero flag output, active LOW.(3)
SDA
VCOM
ZERO
BCK
—
RST 10
OUTR 11
IN
IN
IN
Bit clock input for serial audio data.(1)
Serial audio data input.(1)
V
14 VOUT
13 VCC
L
DATA
LRCK
AGND 12
Left and right word clock, equal to the sampling
rate (fS).(1)
20
21
22
23
24
RSV
SCKO
VDD
—
Reserved must be open.
OUT System clock output, 256/384 fS.
—
—
—
Digital power supply, +5V.
Digital ground.
DGND
XT2
27MHz Crystal connection.
NOTES: (1) Schmitt trigger input.
(2) Schmitt trigger input with internal pull-up resistor.
(3) Open drain output.
PCM1740
2
SBAS128B
www.ti.com
ELECTRICAL CHARACTERISTICS
All specifications at TA = +25°C, VCC = VDD = VPP = 5.0V, fS = 44.1kHz, system clock = 384fS, 16-bit data, unless otherwise noted.
PCM1740E
PARAMETER
RESOLUTION
CONDITIONS
MIN
TYP
MAX
UNITS
16
Bits
DATA FORMAT
Audio Interface Format
Audio Data Bit Length
Audio Data Format
Standard/I2S Selectable
16/20/24 Selectable
Bits
MSB First, Two’s Binary Complement
Sampling Frequency (fS)
Standard (fS)
Half (fS)
32
16
64
44.1
22.05
48
24
96
kHz
kHz
kHz
Double (fS)
88.2
Internal System Clock Frequency
256fS/384fS
DIGITAL INPUT/OUTPUT
Logic Family
Input Logic
VIH = VDD
TTL Compatible
(1), (2)
High Level Input Voltage: VIH
2.0
VDC
VDC
µA
(1), (2)
Low Level Input Voltage: VIL
0.8
(1), (2)
High Level Input Current: IIH
±10
Low Level Input Current:
(1)
IIL
VIL = 0V
VIL = 0V
±10
µA
µA
(2)
IIL
–120
(3)
High Level Output Voltage: VOH
IOH = –2mA
VDD – 0.5V
VDC
Low Level Output Voltage:
(3)
VOL
IOL = 4mA
IOL = 2mA
0.5
0.5
VDC
VDC
(4)
VOL
DIGITAL INPUT/OUTPUT of I2C-BUS INTERFACE
(5)
High Level Input Voltage: VIH
3.0
–0.3
0
V
V
(5)
Low Level Input Voltage: VIL
1.5
(6)
Low Level Output Voltage: VOL
0.4
250
10
V
(7)
Output Fall Time: tOF
ns
µA
pF
Input Logic Current: II(8)
10% to 90% of VDD
–10
Capacitance for each I/O pin: CI(5)
10
VCXO CHARACTERISTICS (MCKO)
Crystal Clock Frequency (9)
Crystal Clock Accuracy(9)
XTUN Tuning Voltage Range(10)
XTUN Input Impedance(10)
Output Clock Frequency
Output Clock Accuracy
VCXO Tuning Range
27MHz, Fundamental Crystal
27.0000
MHz
ppm
V
±30
0
3.0
55
60
27.0000
±50
300
45
kΩ
XTUN = 1.3V
XTUN = 1.3V
MHz
ppm
ppm
%
XTUN = 0V – 3V
Output Clock Duty Cycle
Output Clock Jitter
10pF Load
35
Standard Deviation
20% to 80% VDD, 10pF Load
80% to 20% VDD, 10pF Load
100
4
ps
Output Rise Time
ns
Output Fall Time
4
ns
Response Time(11)
Power Up Time(12)
10
5
µs
ms
PLL AC CHARACTERISTICS (SCKO)
Output Clock Frequency
Output Clock Duty Cycle
Output Clock Jitter
MCKO = 27.0MHz
10pF Load
4.096
40
36.864
60
MHz
%
50
150
4
Standard Deviation
ps
Output Rise Time
20% to 80% VDD, 10pF Load
80% to 20% VDD, 10pF Load
ns
Output Fall Time
4
ns
Frequency Transition Time(13)
Power Up Time(14)
20
30
ms
ms
15
DYNAMIC PERFORMANCE(15)
THD+N:
VOUT = 0dB
fS = 44.1kHz
fS = 96kHz
fS = 44.1kHz
0.0035
0.007
0.0035
0.007
94
90
94
90
0.01
0.01
%
%
%
VOUT = –60dB
fS = 96kHz
%
Dynamic Range
fS = 44.1kHz, EIAJ, A-Weighted
fS = 96kHz, A-Weighted
fS = 44.1kHz, EIAJ, A-weighted
fS = 96kHz, A-weighted
fS = 44.1kHz
90
90
88
dB
dB
dB
dB
dB
Signal-to-Noise Ratio(16)
Channel Separation
92
fS = 96kHz
88
dB
dB
Level Linearity Error
VOUT = –90dB
±1.0
PCM1740
SBAS128B
3
www.ti.com
ELECTRICAL CHARACTERISTICS (Cont.)
All specifications at TA = +25°C, VCC = VDD = VPP = 5.0V, fS = 44.1kHz, system clock = 384fS, 16-bit data, unless otherwise noted.
PCM1740E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Gain Error
±1.0
±1.0
±1.0
±3.0
±3.0
% of FSR
% of FSR
% of FSR
Gain Mismatch, Channel-to-Channel
Bipolar Zero Error
ANALOG OUTPUT
Voltage Range
Full Scale (0dB)
AC Coupled
0.62 VCC
0.5 VCC
VPP
VDC
kΩ
Center Voltage
Load Impedance
5
DIGITAL FILTER PERFORMANCE
Passband
0.445 fS
±0.17
Hz
Hz
Stop Band
0.555 fS
Passband Ripple
Stop Band Attenuation
De-Emphasis Error
Delay Time
dB
dB
–35
–0.2
+0.55
dB
sec
11.125/fS
ANALOG FILTER PERFORMANCE
Frequency Response
20Hz to 20kHz
20Hz to 40kHz
–0.16
–0.6
dB
dB
POWER SUPPLY REQUIREMENTS
Voltage Range
VDD, VCC, VPP
+4.5
+5
25
125
+5.5
30
150
VDC
mA
mW
Supply Current, IDD + ICC + IPP
Power Dissipation
VDD = VCC = VPP = +5V
VDD = VCC = VPP = +5V
TEMPERATURE RANGE
Operation
–25
–55
+85
°C
°C
Storage
+125
Thermal Resistance, θJA
100
°C/W
NOTES: (1) Pins 6, 7, 18, 19: AD0, AD1, BCK, DATA, LRCK (Schmitt trigger input).
(2) Pin 10: RST (Schmitt trigger input with internal pull-up resistor).
(3) Pins 5, 21: MCKO, SCKO. (4) Pin 16: ZERO (open drain output).
(5) Pins 8, 9: SCL, SDA.
(6) Pin 9: SDA (open drain output, IOL = 3mA).
(7) Pin 9: SDA (from VIHMIN to VILMAX with a bus capacitance from 10pF to 400pF).
(8) Pins 8, 9: SCL, SDA (input current each I/O pin with an input voltage between 0.1VDD and 0.9VDD).
(9) This characteristic is the requirement for crystal oscillator.
(10) Pin 3: XTUN.
(11) The maximum response time when the XTUN is changed.
(12) The maximum delay time from power on to oscillation.
(13) The maximum lock up time when the PLL frequency is changed.
(14) The maximum delay time from power on to lock up.
(15) Dynamic performance specifications are tested with a 20kHz low-pass filter using a Shibasoku distortion analyzer 725°C with 30kHz LPF, 400Hz
HPF, Average-Mode.
(16) SNR is tested with infinite zero detection circuit disabled.
PCM1740
4
SBAS128B
www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, VCC = VDD = +5V, fS = 44.1kHz, fSCKO = 384fS = 16.9344MHz, and 16-bit data, unless otherwise noted.
FREQUENCY RESPONSE
(De-emphasis OFF, fS = 44.1kHz)
PASSBAND RIPPLE
(De-emphasis OFF, fS = 44.1kHz)
0
–20
0
–0.2
–0.4
–0.6
–0.8
–1
–40
–60
–80
–100
0
1
2
3
4
0
0.1
0.2
0.3
0.4
0.5
fS
fS
DE-EMPHASIS ERROR (3kHz)
DE-EMPHASIS FREQUENCY RESPONSE (3kHz)
0.6
0.4
0
–2
0.2
–4
0
–6
–0.2
–0.4
–0.6
–8
–10
–12
0
3628
7256
10884
14512
19999.35
21768
0
0
0
5k
10k
15k
20k
25k
25k
25k
Frequency (Hz)
Frequency (Hz)
DE-EMPHASIS ERROR (44.1kHz)
DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz)
0.6
0.4
0.2
0
–2
–4
–6
–8
0
–0.2
–0.4
–0.6
–10
–12
0
4999.8375
9999.675
14999.5125
5k
10k
15k
20k
Frequency (Hz)
Frequency (Hz)
DE-EMPHASIS ERROR (48kHz)
DE-EMPHASIS FREQUENCY RESPONSE (48kHz)
0.6
0.4
0.2
0
–2
–4
–6
–8
0
–0.2
–0.4
–0.6
–10
–12
0
5442
10884
16326
5k
10k
15k
20k
Frequency (Hz)
Frequency (Hz)
PCM1740
SBAS128B
5
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VCC = VDD = +5V, fS = 44.1kHz, FSCKO = 384fS = 16.9344MHz, and 16-bit data, unless otherwise noted.
ANALOG FILTER
(1Hz to 10MHz)
ANALOG FILTER
(1Hz to 20kHz)
20
0
0.05
0
–20
–40
–60
–80
–100
–0.05
–0.1
–0.15
0
0.1
0.1
0.2
0.3
0.4
0.4
0.5
1
10
100
1k
10k
100k
Log Frequency (Hz)
Log Frequency (Hz)
THD+N (FS), DYNAMIC RANGE, and SNR
vs SUPPLY VOLTAGE
THD+N (FS), DYNAMIC RANGE, and SNR
vs TEMPERATURE
(Temperature = 25°C, 384fS, fS = 44.1kHz)
(VCC = VDD = VPP = 5V, 384fS, fS = 44.1kHz)
0.005
0.004
0.003
0.002
0.001
0.000
95
94
93
92
91
90
0.005
0.004
0.003
0.002
0.001
0.000
95
SNR
SNR
94
93
92
91
90
Dynamic Range
Dynamic Range
THD+N
THD+N
4.25
4.5
4.75
5
5.25
5.5
5.75
–50
–25
0
25
50
75
100
Supply Voltage (V)
Temperature (°C)
THD+N (FS), DYNAMIC RANGE, and SNR
vs SAMPLING FREQUENCY
SUPPLY CURRENT vs SAMPLING FREQUENCY
0.010
96
35
0.008
0.006
0.004
0.002
0.000
94
92
90
88
86
THD+N
30
25
20
SNR
Dynamic Range
32
44.1
48
64
88.2
96.0
32
44.1
48
64
88.2
96.0
Sampling Frequency (kHz)
Sampling Frequency (kHz)
PCM1740
6
SBAS128B
www.ti.com
STEREO DIGITAL-TO-ANALOG
CONVERTER
3rd ORDER ∆Σ MODULATOR
20
0
The stereo DACs of the PCM1740 use a multi-level delta-
sigma architecture. Based upon a 3rd-order noise shaper and
a 5-level amplitude quantizer, this section converts the 8x
oversampled, 18-bit input data from the interpolation filter
to a 5-level delta-sigma format. A block diagram of the
multi-level delta-sigma modulator is shown in Figure 1.
This architecture has the advantage of improved stability
and increased tolerance to clock jitter when compared to the
one-bit (2-level) delta-sigma DACs.
–20
–40
–60
–80
–100
–120
–140
–160
The combined oversampling rate of the delta-sigma modu-
lator and the 8x interpolation filter is 48fS for a 384fS system
clock, and 64fS for a 256fS system clock. The theoretical
quantization noise performance for the 5-level delta-sigma
modulator is shown in Figure 2.
0
5
10
15
20
25
Frequency (kHz)
The output of the delta-sigma modulator is low-pass filtered
and buffered by an on-chip output amplifier. For best
performance, an external low-pass filter is recommended.
Refer to the Applications Information section of this data
sheet for details regarding DAC output filter recommenda-
tions.
FIGURE 2. Quantization Noise Spectrum.
rily used for decoupling purposes. See the Applications
Information section of this data sheet for more information
regarding the use of the VCOM output for biasing external
circuitry.
The PCM1740 includes two analog outputs, VOUTL (pin 14)
and VOUTR (pin 11), corresponding to the left and right audio
outputs. The full-scale output amplitude is 0.62 × VCC, or
3.1VPP with a +5V supply and an AC-coupled load of 5kΩ or
greater. The analog outputs are centered about the DC com-
mon-mode voltage, which is typically VCC/2.
VOLTAGE CONTROLLED CRYSTAL OSCILLATOR
(VCXO)
The PCM1740 includes an on-chip voltage-controlled crys-
tal oscillator, or VCXO, which is used to generate the
27MHz master clock required by most digital broadcast and
MPEG-2 decoding applications.
The DC common-mode voltage is made available at the
VCOM output (pin 15). This is an unbuffered output, prima-
+
+
+
+
+
+
Z–1
Z–1
Z–1
In
8fS
18-Bit
–
–
+
+
+
5-level Quantizer
4
3
2
1
0
Out
48fS (384fS)
64fS (256fS)
FIGURE 1. 5-Level ∆Σ Modulator Block Diagram.
PCM1740
SBAS128B
7
www.ti.com
The 27MHz clock is available at the MCKO output (pin 5).
The VCXO output frequency can be precisely tuned using a
control voltage at the XTUN input (pin 3). The tuning range
is 27MHz ±150ppm typical for a 0V to +3V control voltage
range. Figure 3 shows the VCXO equivalent circuit, while
Figure 4 shows the typical tuning curve.
27MHz
Tuned Clock
XT1
1
27MHz
Crystal
XT2
24
3
At power up, the VCXO requires 5ms start up time. The
VCXO also exhibits a 10µs settling time in response to
changes in the XTUN control voltage. VCXO operation and
the MCKO output are not affected by the power on or
external reset functions, continuing to operate during the
initialization sequence.
Voltage
Range
0 to 3V
XTUN
CLV
CL
Crystal Selection
The VCXO connects to an external 27MHz crystal via XT1
(pin 1) and XT2 (pin 24). The crystal should be AT-cut,
fundamental mode with ±30ppm accuracy and less than 50Ω
motional resistance. Crystal shunt capacitance should be 3pF
maximum, while load capacitance should be less than 7pF.
Miniature lead type or surface-mount devices are recom-
mended. External load capacitors are not needed, since they
are provided on-chip. The crystal should be placed as close as
possible to the XT1 and XT2 pins to reduce effects of parasitic
capacitance and land resistance.
FIGURE 3. VCXO Equivalent Circuit.
27.005
27.004
27.003
27.002
27.001
27.000
26.999
26.998
26.997
26.996
26.995
PROGRAMMABLE PHASE LOCKED LOOP (PLL)
The PCM1740 includes an on-chip PLL for generating a 256fS
or 384fS audio system clock from the 27MHz VCXO output.
A block diagram of the PLL section is shown in Figure 5. The
PLL output clock is used by the digital filter and delta-sigma
modulator circuitry, and is made available at the SCKO output
(pin 21) for use with additional audio converters and signal
processors.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Tuning Voltage (V)
FIGURE 4. VCXO Output Frequency (MCKO) versus
Tuning Voltage (XTUN).
PLL
Frequency Selection
Control Register 3
N Counter
Phase
Frequency
Selection
ROM
Detector
and
Loop Filter
VCO
M Counter
SCKO
256/384fS
MCKO
27MHz ±150ppm
27MHz
VCXO
Crystal
XTUN
0V to +3V
FIGURE 5. PLL Block Diagram.
PCM1740
8
SBAS128B
www.ti.com
The PLL can generate one of nine pre-programmed system
clock rates for either 256fS or 384fS output. The PLL output
and sampling frequencies are programmed using Control
Register 3. Table I shows the available sampling frequencies
and the corresponding PLL output clock rates. The reset
default condition for the PLL is fS = 44.1kHz with SCKO =
384fS, or 16.9344MHz.
RESET OPERATION
POWER-ON RESET
The PCM1740 includes power-on reset circuitry for start up
initialization. The initialization sequence starts when VDD
exceeds 2.2V (typical). The initialization sequence requires
1024 PLL output (or SCKO) clock cycles for completion.
During initialization, both VOUTL and VOUTR are forced to
VCC/2. Figure 6 shows the power-on reset timing, while
Table II shows the reset default settings for user-program-
mable functions. The user should not attempt to write
control registers via the I2C-Bus interface during the initial-
ization sequence.
SAMPLING
FREQUENCY (LRCK)
INTERNAL SYSTEM
Clock - 256fS
INTERNAL SYSTEM
Clock - 384fS
16kHz
32kHz
Half
4.096MHz
8.192MHz
6.144MHz
12.288MHz
24.576MHz
8.4672MHz
16.9344MHz
33.8688MHz
9.216MHz
Normal
Double
Half
64kHz
16.384MHz
5.6448MHz
11.2896MHz
22.5792MHz
6.144MHz
22.05kHz
44.1kHz
88.2kHz
24kHz
Normal
Double
Half
EXTERNAL RESET
The PCM1740 includes an external reset input, RST (pin
10). This input may be used to force an initialization se-
quence. As shown in Figure 7, the RST pin must be held low
for a minimum of 20ns. The initialization sequence will then
start on the rising edge of RST. Initialization requires 1024
PLL output (or SCKO) clock cycles for completion. During
initialization, both VOUTL and VOUTR are forced to VCC/2.
Table II shows the reset default settings for user-program-
mable functions. The user should not attempt to write
control registers via the I2C-Bus interface during the initial-
ization sequence.
48kHz
Normal
Double
12.288MHz
24.576MHz
18.432MHz
36.864MHz
96kHz
TABLE I. PLL Sampling and System Clock Frequencies.
At power-up, the PLL requires 30ms start up time for
stabilization. The PLL also exhibits a settling time of 20ms
in response to changes in sampling frequency selection.
The PLL output continues to operate during power-on or
external reset sequences, with the sampling frequency set to
fS = 44.1kHz and SCKO = 384fS.
2.4V
2.2V
2.0V
VCC /VDD
Reset
Reset Removal
Internal Reset
1024 System Clock Periods
System Clock
(SCKO)
FIGURE 6. Power-On Reset Operation.
t
RST ≥ 20ns
tRST
RST
tRST
Reset
Reset Removal
Internal Reset
1024 System Clock Periods
System Clock
(SCKO)
FIGURE 7. External Reset Operation.
PCM1740
SBAS128B
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ZERO FLAG OUTPUT
Audio DSP/Decoder
PCM1740
The PCM1740 includes a zero flag output, ZERO (pin 16).
This is an open-drain output, and a 10kΩ pull-up resistor
connected to VDD is recommended when using the ZERO
flag as a logic output.
Frame Sync
Serial Bit Clock
Serial Data Output
Audio Clock
LRCK
BCK
DATA
SCKO
The PCM1740 includes an infinite zero detection function
that monitors the audio data at the DATA input (pin 18). If
the audio data for both the left and right channels is all zeros
for 65,536 continuous BCK clock cycles, the zero flag will
be activated, turning on a MOSFET switch and connecting
the ZERO pin to ground. This provides an active low output
that may be used to control an external mute circuit, or as a
logic indicator for an audio DSP/decoder or microprocessor.
FIGURE 8. Interfacing the PCM1740 to an Audio DSP.
LRCK and BCK Rates
The LRCK input is operated at the sampling frequency, fS.
The BCK input is operated at 32, 48, or 64 times the
sampling frequency. Both LRCK and BCK must be syn-
chronous with the SCKO output for proper operation.
AUDIO SERIAL INTERFACE
Data Formats
The PCM1740 includes a three-wire serial audio interface.
This includes LRCK (pin 19), BCK (pin 17), and DATA
(pin 18). The LRCK input is the audio left/right clock, which
is used as a latch signal for the interface. The BCK input is
used to clock audio data into the serial port. The DATA
input carries multiplexed data for the left and right audio
channels. Audio data must be Two’s Complement, MSB
first formatted. Figure 8 shows the typical connection be-
tween the PCM1740 audio serial interface and an audio DSP
or decoder.
The PCM1740 supports two audio interface formats: Standard
and I2S. These formats are shown in Figure 9. The audio data
word length for the Left and Right channels may be 16-, 20-,
or 24-bits. The audio data word length and format are pro-
grammed using Control Registers 2 and 3. The reset default
condition is Standard format with 16-bit audio data.
Timing Requirements
Figure 10 shows the audio interface timing requirements.
(a) Standard Right - Justified Format
1/fs
L_ch
R_ch
LRCIN (pin 4)
BCKIN (pin 6)
AUDIO DATA WORD = 16-BIT
DIN (pin 5) 14 15 16
1
3
2
3
14 15 16
1
3
2
3
14 15 16
MSB
LSB
MSB
LSB
AUDIO DATA WORD = 20-BIT
DIN (pin 5) 18 19 20
1
1
2
2
18 19 20
1
1
2
2
18 19 20
MSB
3
LSB
MSB
3
LSB
AUDIO DATA WORD = 24-BIT
DIN (pin 5)
23 24
22 23 24
22 23 24
MSB
LSB
MSB
LSB
(b) I2S Format
1/fs
L_ch
R_ch
LRCIN (pin 4)
BCKIN (pin 6)
AUDIO DATA WORD = 16-BIT
DIN (pin 5)
1
1
1
2
2
2
3
14 15 16
LSB
1
1
1
2
2
2
3
14 15 16
LSB
1
1
1
2
2
2
MSB
3
MSB
3
AUDIO DATA WORD = 20-BIT
DIN (pin 5)
18 19 20
18 19 20
MSB
3
LSB
MSB
3
LSB
AUDIO DATA WORD = 24-BIT
DIN (pin 5)
22 23 24
22 23 24
MSB
LSB
MSB
LSB
FIGURE 9. Audio Interface Formats.
PCM1740
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LRCKIN
BCKIN
1.4V
1.4V
BCKIN Pulse Cycle Time
BCKIN Pulse Width High
BCKIN Pulse Width Low
: tBCY
: 100ns (min)
: tBCH : 50ns (min)
tBCH
tBCL
tLB
: tBCL
: 50ns (min)
: 30ns (min)
: 30ns (min)
: 30ns (min)
: 30ns (min)
BCKIN Rising Edge to LRCIN Edge : tBL
LRCIN Edge to BCKIN Rising Edge : tLB
tBL
tBCY
DIN Set-up Time
DIN Hold Time
: tDS
: tDH
DIN
1.4V
tDS
tDH
FIGURE 10. Audio Interface Timing.
This section describes the control registers, while the
I2C-Bus interface is described in a later section. Table II lists
the available functions and their corresponding reset default
condition.
Loss of Synchronization
Ideally, LRCK and BCK will be derived from the SCKO
output, ensuring synchronous operation. For other cases, the
PCM1740 includes circuitry to detect loss of synchroniza-
tion between the LRCK and the system clock, SCKO. A loss
of synchronization condition is detected when the phase
relationship between SCKO and LRCK exceeds ±6 BCK
cycles during one sample period, or 1/fS. If a loss of
synchronization condition is detected, the DAC operation
will halt within one sample period and the analog outputs
will be forced to VCC/2 until re-synchronization between
LRCK and SCKO is completed. Figure 11 shows the state of
the analog outputs given a loss of synchronization event.
During the undefined states, as well as transitions between
normal and undefined states, the analog outputs may gener-
ate audible noise.
Register Map
The control register map is shown in Table III. Sub-address
bits B8 through B10 are used to specify the register that is
being written. All reserved bits, shown as “res”, must be set
to ‘0’.
Register Descriptions
The following pages provide detailed descriptions of the five
control registers and their associated functions. All reserved
bits, shown as “res”, must be set to ‘0’.
FUNCTION
MODE BY DEFAULT
Audio Data Format Select:
Standard Format/I2S Format
Standard Format
USER PROGRAMMABLE FUNCTIONS
Audio Data Word Select:
16-Bit /20-Bit /24-Bit
16-Bit
The PCM1740 includes a number of programmable func-
tions, which are configured using five control registers.
These registers are accessed using the I2C-Bus interface.
Polarity of LR-clock Selection
Left/Right = HIGH/LOW
De-emphasis Control:
OFF, 32kHz, 44.1kHz, 48kHz
OFF
Soft Mute Control
OFF
Attenuation Data for Left-channel
Attenuation Data for Right-channel
Attenuation Data Mode Control
Analog Output Mode Select
0dB
0dB
State of
Synchronous
Asynchronous
Synchronous
Left-channel, Right-channel Individually
Synchronization
Stereo Mode
OFF
within
1/fS
Infinity Zero Detect Mute Control
DACs Operation Control
22.2/fS
ON
Undefined Data
Normal
VCOM
(= 0.5 VCC
System Clock Select: 256fS /384fS
384fS
)
Undefined
Data
VOUT
Normal
Sampling Frequency Select:
32kHz Group, 44.1kHz Group, 48kHz Group
44.1kHz Group
Normal, x1
Sampling Frequency Multiplier:
Normal/Double/Half
FIGURE 11. Loss of Synchronization and Analog Output State.
TABLE II. User-Programmable Functions.
DATA BYTE
SUB ADDRESS BYTE
REGISTER
Register 0
Register 1
Register 2
Register 3
Register 4
B15
res
res
res
res
res
B14
res
res
res
res
res
B13
res
res
res
res
res
B12
res
res
res
res
res
B11
res
res
res
res
res
B10
A2
A2
A2
A2
A2
B9
A1
A1
A1
A1
A1
B8
A0
A0
A0
A0
A0
B7
AL7
AR7
PL3
SF1
res
B6
AL6
AR6
PL2
SF0
res
B5
B4
B3
AL3
AR3
IW1
SYS
res
B2
B1
AL1
AR1
DEM
LRP
IZD
B0
AL0
AR0
MUT
IIS
AL5
AR5
PL1
AL4
AR4
PL0
AL2
AR2
IW0
ATC
OPE
DSR1 DSR0
res res
LD
TABLE III. Control Register Map.
PCM1740
SBAS128B
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REGISTER DEFINITIONS
B15
res
B14
res
B13
res
B12
res
B11
res
B10
0
B9
0
B8
0
B7
B6
B5
B4
B3
B2
B1
B0
Register 0
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
Left Channel Attenuation Data
Default: AL[7:0] = FFHEX
Register 0 is used to set the digital attenuation level for the Left Channel. If the ATC bit in Register 3 is set to ‘1’, then these
data are also used to control the Right Channel attenuation. The attenuation level is defined by the following relationships:
Attenuation (dB) = 20 x log (AL[7:0]DEC ÷ 256), when AL[7:0] = 01HEX (1DEC) through FEHEX (254DEC
)
Attenuation (dB) = –∞ (or Mute), when AL[7:0] = 00HEX
Attenuation (dB) = 0dB, when AL[7:0] = FFHEX
The Attenuation Load bit, LD, in Register 4 must be set to ‘1’ in order to update attenuation settings.
If LD is set to ‘0’, the attenuation remains at the previously programmed level, ignoring the new data until LD is set to ‘1’.
B15
res
B14
res
B13
res
B12
res
B11
res
B10
0
B9
0
B8
1
B7
B6
B5
B4
B3
B2
B1
B0
Register 1
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
Right Channel Attenuation Data
Default: AR[7:0] = FFHEX
Register 1 is used to set the digital attenuation level for the Right Channel. If the ATC bit in Register 3 is set to ‘1’, then the
Left Channel attenuation data in Register 1 are used to control the Right Channel attenuation. The attenuation level is defined
by the following relationships:
Attenuation (dB) = 20 x log (AR[7:0]DEC ÷ 256), when AR[7:0] = 01HEX (1DEC) through FEHEX (254DEC
)
Attenuation (dB) = –∞ (or Mute), when AR[7:0] = 00HEX
Attenuation (dB) = 0dB, when AR[7:0] = FFHEX
The Attenuation Load bit, LD, in Register 4 must be set to ‘1’ in order to update attenuation settings.
If LD is set to ‘0’, the attenuation remains at the previously programmed level, ignoring the new data until LD is set to ‘1’.
B15
res
B14
res
B13
res
B12
res
B11
res
B10
0
B9
1
B8
0
B7
B6
B5
B4
B3
B2
B1
B0
Register 2
PL3
PL2
PL1
PL0
IW1
IW0
DEM
MUT
MUT
Soft Mute Control
The MUT bit controls the soft mute function. Soft mute changes the digital attenuation level for both the Left
and Right channels, stepping from the currently programmed value to infinite attenuation one step per sample
period, or 1/fS. This provides a quiet muting of the outputs without audible noise.
MUT = 0
MUT = 1
Soft Mute Disabled (default)
Soft Mute Enabled
DEM
Digital De-Emphasis
The DEM bit controls the digital de-emphasis function, which is valid only for 32kHz, 44.1kHz,
and 48kHz sampling frequencies. The de-emphasis plots are shown in the Typical Characteristics section of this
data sheet.
DEM = 0
DEM = 1
De-Emphasis OFF (default)
De-Emphasis ON
PCM1740
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IW0
IW1
Audio Data Word Length
The IW0 and IW1 bits are used to select the data word length for the audio serial interface.
The audio data format is selected using the IIS bit in Register 3.
IW1
IW0
Word Length
16-bits (default)
20-bits
0
0
1
1
0
1
0
1
24-bits
Reserved
PL[3:0]
Analog Output Mode Select
Bits PL[3:0] are used to set the output mode for the analog outputs. Refer to the table below.
PL3
PL2
PL1
PL0
VOUTL
VOUTR
Notes
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Mute
Mute
Mute
Mute
Mute
Left
Mute
Left
Right
(L+R)/2
Mute
Left
Left
Right
(L+R)/2
Mute
Left
Reverse
Left
Right
Right
Right
Right
Left
Stereo (default)
Right
(L+R)/2
Mute
(L+R)/2
(L+R)/2
(L+R)/2
(L+R)/2
Left
Right
(L+R)/2
Mono
B15
res
B14
res
B13
res
B12
res
B11
res
B10
B9
1
B8
B7
B6
B5
B4
B3
B2
B1
B0
IIS
Register 3
0
1
SF1
SF0
DSR1 DSR0
SYS
ATC
LRP
IIS
Audio Data Format
The IIS bit is used to select the audio data format, either Standard Right-Justified or I2S.
IIS = 0
IIS = 1
Standard Right Justified (default)
I2S
LRP
ATC
LRCK Polarity
The LRP bit selects the polarity of left/right clock input (LRCK) when using the Standard Right-Justified audio
data format. This bit has no effect when using the I2S audio data format.
LRP = 0
LRP = 1
Left Channel when LRCK = High; Right Channel when LRCK = Low (default)
Left Channel when LRCK = Low; Right Channel when LRCK = High
Attenuation Mode Control
The ATC bit is used to select independent or common attenuation data for the Left and Right channels.
ATC = 0
ATC = 1
Independent: Left Channel uses Register 0 and Right Channel uses Register 1 (default)
Common: Left and Right Channels both use Register 0
PCM1740
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SYS
Audio System Clock (or SCKO)
The SYS bit is used to select the system clock (or SCKO) frequency, either 256fS or 384fS.
SYS = 0
SYS = 1
384fS (default)
256fS
DSR0
DSR1
Sampling Frequency Multiplier
The DSR0 and DSR1 bits are used to select the multiplier used in conjunction with the SF0 and SF1 bits.
DSR1
DSR0
Multiplier
0
0
1
1
0
1
0
1
Normal, x1 (default)
Double, x2
Half, x 1/2
Reserved
SF0
SF1
Sampling Frequency Select
The SF0 and SF1 bits are used to select the sampling frequency group (32kHz, 44.1kHz, or 48kHz). Frequency
selection must be made with an interval time greater than 20µs. The DSR0 and DSR1 bits, described previously,
are used to select the multiplier.
SF1
0
SF0
0
Sampling Frequency Group
44.1kHz Group ( 22.05kHz, 44.1kHz, or 88.2kHz) (default)
48 kHz Group (24kHz, 48kHz, or 96kHz)
32 kHz Group (16kHz, 32kHz, or 64kHz)
Reserved
0
1
1
0
1
1
B15
res
B14
res
B13
res
B12
res
B11
res
B10
1
B9
0
B8
0
B7
B6
B5
B4
B3
B2
B1
B0
LD
Register 4
res
res
res
res
res
OPE
IZD
LD
Attenuation Data Load Control
The LD bit is used to simultaneously set the Left and Right digital attenuation data. When LD is set to ‘1’, the
digital attenuation data given by Registers 0 and 1 are loaded for the Left and Right channels. When LD is set
to ‘0’, updates to Registers 0 and 1 are ignored, and the attenuation settings remain as previously programmed
until LD is set to ‘1’.
LD = 0
LD = 1
Disabled
Enabled: Left and Right Attenuation Data Updated Simultaneously
IZD
Infinite Zero Detect Mute
The IZD bit is used to enable/disable the infinite zero detect mute function. The PCM1740 includes infinite zero
detection logic that monitors the audio data at the DATA input (pin 18). If the audio data for both the Left and
Right channels are all zeros for 65,536 continuous BCK clock cycles, the zero flag will be activated and output
amplifier will be disconnected from the output of the delta-sigma modulator. The output amplifier input is
switched to the DC common-mode voltage. This forces VOUTL and VOUTR to VCC/2. The ZERO output flag (pin
16) is not affected by the setting of this bit.
IZD = 0
IZD = 1
Disabled (default)
Enabled
OPE
DAC Operation Control
The OPE bit is used to enable/disable the operation of the DACs. When enabled, the DAC outputs are connected
to the output amplifier for normal operation. When disabled, the output amplifier is disconnected from the DAC
output and switched to the DC common-mode voltage. This forces VOUTL and VOUTR to VCC/2.
OPE = 0
OPE = 1
Enabled: Normal Operation(default)
Disabled: Outputs forced to VCC/2
PCM1740
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I2C-BUS INTERFACE DESCRIPTION
Bus Operation
Figure 13 shows the typical configuration of the PCM1740 on
the I2C-Bus. The Master transmitter or transmitter/receiver is
typically a microcontroller, or an audio DSP/decoder. The
Master device controls the data transfers on the bus. The
PCM1740 operates as a Slave receiver, and accepts data from
the Master when it is properly addressed. The data transfer
may be comprised of an unlimited number of bytes, or 8-bit
data words. Figure 14 shows the message transfer protocol.
The PCM1740 includes an I2C-Bus interface for writing the
internal control registers. This provides an industry standard
method for interfacing a host CPU control port to the
PCM1740. The PCM1740 operates as a Slave receiver on
the bus, and supports data transfer rates up to 100 kilobits-
per-second (kbps).
The I2C-Bus interface is comprised of four signals: SDA
(pin 9), SCL (pin 8), AD0 (pin 6), and AD1 (pin 7). The SCL
input is the serial data clock, while SDA is the serial data
input. SDA carries start/stop, slave address, sub-address (or
register address), register, and acknowledgment data. The
AD0 and AD1 inputs form the lower two bits of the slave
address.
For normal bit transfer on the bus, data on SDA must
be static while SCL is High. Data on SDA may change
High/Low states when SCL is Low. The exception to this
rule is the Start and Stop conditions.
The Start condition is defined by a High-to-Low transition on
SDA while SCL is High, and is denoted with an ‘S’ in Figure
12. The Stop condition is defined by a Low-to-High transition
on SDA while SCL is High, and is denoted with a ‘P’ in Figure
12. The Start and Stop conditions are always generated by the
Master. All data transfers from Master to Slave begin with a
Start condition and end with a Stop condition. The bus is
considered to be busy after the Start condition, and becomes
free some time after the Stop condition.
Slave Address
The PCM1740 Slave address consists of seven bits, as shown
in Figure 12. The five most significant bits are fixed, while the
two least significant bits, named A0 and A1, are defined by the
logic levels present at the AD0 and AD1 input pins. This
allows four PCM1740s to reside on the same I2C-Bus.
Start
from
Master
Acknowledge
from
Acknowledge
from
Acknowledge Stop
from
Slave
from
Slave
Slave
Master
MSB
R/W
S
1
0
0
1
1
A1 A0
0
A
B15 B14 B13 B12 B11 B10 B09 B08
A
B07 B06 B05 B04 B03 B02 B01B00
A
P
Slave Address
Sub Address Byte
Data Byte
Internal Strobe for
Data Latching
FIGURE 12. Control Data Format.
SDA
SCL
Master
Transmitter/
Receiver
Slave
Receiver
(PCM1740)
Slave
Transmitter/
Receiver
Master
Transmitter/
Receiver
FIGURE 13. Typical I2C-Bus Configuration.
SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9
Start
Condition
Slave
Address
R/W
ACK
Data
ACK
Start
Condition
Slave
Address
R/W
ACK
Stop
NOTES: (1) Clock LOW (min) = 4.7µs; clock HIGH (min) = 4µs.
(2) The dashed line is the acknowledgement of the receiver.
(3) Mark-to space ratio = 1:1 (LOW-to-HIGH).
(4) Maximum number of bytes is unrestriced.
(5) Premature termination of transfer is allowed by generation of STOP condition.
(6) Acknowledge clock bit must be provided by master.
FIGURE 14. I2C Bus Data Transfer.
PCM1740
SBAS128B
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Data transfer begins with a Start condition, and is immedi-
ately followed by the Slave address and Read/Write bit. The
Read/Write bit is set to ‘0’ for the PCM1740, in order to
write data to the control register specified by the sub-
address. This is followed by an acknowledgment from the
PCM1740, the sub-address (that is, the control register
address), another acknowledgment from the PCM1740, the
control register data, and another acknowledgment from the
PCM1740. What happens after this depends on if the user
wants to continue writing additional control registers, or if
they want to terminate the data transfer. If the user wants to
continue, the acknowledgment is followed by a Start condi-
tion for the next write sequence. If the user decides to
terminate the data transfer, then a Stop condition is gener-
ated by the Master.
The I2C-Bus specification defines timing requirements for
devices connected to the bus. Timing requirements for the
PCM1740 are shown in Figure 15.
Reference
For additional information regarding the I2C-Bus, please
refer to the I2C-Bus Specification available online from
NXP Semiconductors.
SDA
tBUF
tLOW
tSU, DAT
tHD; STA
tR
tF
tR
tF
SCL
tHD; DAT
tHIGH
tHD; STA
tSU; STA
tSU; STO
S: START condition
Sr: repeated START condition
P: STOP condition
S
Sr
P
S
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
fSCL
SCL Clock Frequency
100
kHz
tHD; STA
Hold time (repeated) START condition,
after this period, the first clock pulse is
generated
4.0
µs
tLOW
tHIGH
tSU:STA
tHD;DAT
tSU;DAT
tR
LOW period of the SCL clock
HIGH period of the SCL clock
4.7
4.0
4.7
0
µs
µs
µs
µs
ns
ns
ns
µs
µs
Set-up time for a repeated START condition
Data hold time for I2C-BUS devices
Data set-up time
3.45(2)
250
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
1000
300
tF
tSU;STO
tBUF
4.0
4.7
Bus free time between a STOP and START
condition
CB
Capacitive load for each bus line
400
pF
V
VNL
Noise margin at the LOW level for each
connected device (including hysteresis)
0.1 VDD
0.2 VDD
VNH
Noise margin at the HIGH level for each
connected device (including hysteresis)
V
FIGURE 15. I2C Bus Timing.
PCM1740
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www.ti.com
inductor or ferrite bead should be placed in series with the
+5V supply connection to reduce or eliminate high-fre-
quency noise on the supply line.
APPLICATIONS INFORMATION
BASIC CONNECTION DIAGRAM
A basic connection diagram is shown in Figure 16. Power
supply and reference decoupling capacitors should be located
as close as possible to the PCM1740 package. The 27MHz
crystal should also be located as close as possible to the
package, to reduce the effects of parasitic capacitance on
VCXO operation.
In cases where overshoot or ringing is present on the LRCK
or BCK signals, a series resistance of 25Ω to 100Ω should
be added. The resistor forms a simple RC filter with the
device input and printed circuit board (PCB) parasitic ca-
pacitance, dampening the overshoot and ringing effects,
while reducing high-frequency noise emissions.
A single +5V supply is recommended, to avoid issues with
power-supply sequencing and SCR latch-up. It is recom-
mended that this supply be separate from the system digital
power supply. In cases where this is not practical, an
TYPICAL APPLICATION DIAGRAM
Figure 17 shows the PCM1740 being used as part of the
audio sub-system in a set-top box application.
C1 to C6 = 1µF to 10µF Capacitors
( Aluminum Electrolytic or tantalum)
+5V
27MHz Crystal
PCM1740
1
XT2
DGND
VDD
XT1
2
3
PGND
XTUN
VPP
C2
VCXO
Control
Voltage
(0V to +3V)
27MHz
Master Clock
+
Buffer(1)
256/384fS
to AudioDecoder
and Data Converters
C1
4
+
SCKO
RSV
Buffer(1)
5
MCKO
AD0
X
6
LRCK
DATA
BCK
From Audio
7
Decoder
Serial
Interface
AD1
I2C BUS
and Reset
Control
9
SCL
8
from µP
ZERO
VCOM
SDA
RST
Zero Flag
C3
C4
10
+
10kΩ
+
VOUT
L
V
OUTR
+
C5
VCC
AGND
C6
+
Low Pass
Filter(2)
Low Pass
Filter(2)
Analog
Ground
NOTES: (1) Use buffer when driving multiple nodes.
(2) See applications information section for filter
recommendations.
Right Channel
Output
Left Channel
Output
FIGURE 16. Basic Connection Diagram.
VOUT
VCOM
VOUT
L
BCIN
LRCIN
DAC
8x
Interpolation
Filter
Audio
Serial
I/F
Line-Out_L
Line-Out_R
Audio
(L)
Low-Pass
Decoder
DIN
Low-Pass
Filter
Filter
and Output
Amp
and
R
Programmable
Functions
DAC
(R)
and
Analog
Mute
SCL
SDA
ZERO
I2C
I/F
and
AD1
AD0
XTUN
REGs
Counter N
Counter M
SCKO
MCKO
PD
LPF
VCO
To Audio Decoder
and Data Converters
MPEG
System Controller
27MHz
Crystal
XTI
XTO
RST
To Other Devices
VCXO
27MHz Reference
Generated by
Receive Counter
Reset
Power Supply
Phase
Detec.
LPF
VCP PGND VCC AGND VDD DGND
VCXO Control Voltage
FIGURE 17. Typical Application Diagram.
PCM1740
SBAS128B
17
www.ti.com
The VTUN control voltage is generated by the MPEG-2
controller, which compares the MCKO output clock from
the PCM1740 with the clock count received from the trans-
mitter. VTUN is adjusted to retain clock synchronization
between the transmitted and received signals. The SCKO
output is used as the audio master clock for the audio
decoder and additional data converters.
The PCM1740 includes an on-chip low-pass filter as part of
the output amplifier stage. The frequency response for the
filter is shown in the Typical Characteristics section
of this data sheet. The –3dB cutoff frequency is fixed at
100kHz.
Figure 19 shows the recommended external low-pass active
filter circuits for dual and single-supply applications. These
circuits are second-order Butterworth filters using the Mul-
tiple Feedback (MFB) circuit arrangement. Both filters have
a cutoff frequency of 30kHz. Figure 19(a) is a dual-supply
filter with a gain of 1.85 (for a standard 2 VRMS line output
level). Figure 19(b) is a single-supply filter with a gain of 1.
Values for the filter components may be calculated using the
FilterPro program, available from the TI web site
(www.ti.com) and local sales offices. For more information
regarding MFB active filter design and the FilterPro pro-
gram, refer to TI Application Report SBFA001.
V
COM Output
The unbuffered DC common-mode voltage output, VCOM
(pin 15), is brought out mainly for de-coupling purposes.
VCOM is nominally biased to VCC/2. The VCOM output may
be used to bias external circuits, but it must be connected to
a high-impedance node or buffered using a voltage follower.
Figure 18 shows examples of the proper use of the VCOM
output for external biasing applications.
DAC OUTPUT FILTERING
Since the overall system performance is defined primarily
by the quality of the DACs and their associated analog
output circuitry, op amps designed specifically for audio
applications are recommended for the active filters. TI’s
OPA2134, OPA2353, and OPA2343 dual op amps are ideal
for use with the PCM1740.
Delta-Sigma DACs utilize noise shaping techniques to im-
prove in-band signal-to-noise (SNR) performance at the
expense of generating increased out of band noise above the
Nyquist frequency, or fS/2. The out-of-band noise must be
low-pass filtered in order to provide optimal converter
performance. This is accomplished by a combination of on-
chip and external low-pass filtering.
(b) Using a Buffer to Provide Bias for Multiple or
Low Input Impedance Nodes
(a) Biasing an External Active Filter Stage
Use voltage follower
to buffer VCOM
VCC
Non-Polarized
1µF
PCM1740
PCM1740
VOUT
OPA343
VCOM
To Bias
Nodes
+
OPA337
1-10µF
VCOM
+
1-10µF
FIGURE 18. Using VCOM To Bias External Circuitry.
PCM1740
18
SBAS128B
www.ti.com
R2
5.76kΩ
C1
220pF
PCM1740
1µF
to
10µF
+VA
R1
3.16kΩ
R3
10kΩ
VOUTR/L
+
Filtered
Output
C2
2200pF
OPA134 Series
–VA
(a) Dual-Supply Filter Circuit
R2
C1
3.83kΩ
220pF
PCM1740
1µF
to
10µF
R1
3.83kΩ
VCC
R3
15kΩ
1µF
to
10µF
VOUTR/L
+
Filtered
Output
C2
2200pF
+
OPA343/353 Series
VCOM
4.7µF
to 10µF
VCC
2
(b) Single-Supply Filter Circuit
FIGURE 19. Recommended Output Filter Circuits.
PCM1740
SBAS128B
19
www.ti.com
Revision History
DATE
REVISION PAGE
SECTION
DESCRIPTION
—
Entire Document
Updated format.
2
Electrical Characteristics Changed Low Level Output Voltage VOH to VOL (typo)
5/07
B
14
SF0, SF1
Figure 12
Figure 14
Added sentence regarding interval time must be greater than 20µs.
Changed Figure 12.
15
Changed Figure 14.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
PCM1740
20
SBAS128B
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jun-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PCM1740E
ACTIVE
SSOP
DB
24
58 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCM1740E-2/2K
PCM1740E-2/2KG4
PCM1740E/2K
OBSOLETE
OBSOLETE
ACTIVE
SSOP
SSOP
SSOP
DB
DB
DB
24
24
24
TBD
TBD
Call TI
Call TI
Call TI
Call TI
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCM1740E/2KG4
PCM1740EG4
ACTIVE
ACTIVE
SSOP
SSOP
DB
DB
24
24
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
58 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jun-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
PCM1740E/2K
SSOP
DB
24
2000
330.0
17.4
8.5
8.6
2.4
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jun-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP DB 24
SPQ
Length (mm) Width (mm) Height (mm)
336.6 336.6 28.6
PCM1740E/2K
2000
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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