PCM3060_技术文档

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PCM3060

SLAS533B–MARCH 2007–REVISED MARCH 2008

24-BIT, 96/192-kHz ASYNCHRONOUS STEREO AUDIO CODEC

1

FEATURES

and DAC

•

24-Bit Delta-Sigma ADC and DAC

ADC, DAC Asynchronous Operation

Stereo ADC:

–

Digital De-Emphasis: 32, 44.1, 48 kHz for

DAC

–

Power Down: ADC/DAC Independently

Asynchronous/Synchronous Control for

ADC/DAC Operation

–

High Performance: (Typical, 48 kHz)

–

THD+N: –93 dB

SNR: 99 dB

•

External Reset and Power-Down Pin:

ADC/DAC Simultaneously

Audio Interface Mode:

ADC/DAC Independent Master/Slave

Audio Data Format:

–

Dynamic Range: 99 dB

–

Sampling Rate: 16–96 kHz

System Clock: 256, 384, 512, 768 f_S

Full Scale Input: 3 Vp-p

–

ADC/DAC Independent

I²S, Left-Justified, Right-Justified

Antialiasing Filter Included

1/64 Decimation Filter:

•

Dual Power Supplies:

5-V for Analog and 3.3-V for Digital

Package: TSSOP-28

–

Pass-Band Ripple: ±0.05 dB

–

Stop-Band Attenuation: –65 dB

–

On-Chip High-Pass Filter: 0.91 Hz at

f_S= 48 kHz

APPLICATIONS

•

Stereo DAC:

•

DVD-RW

Digital TV

Digital Set-Top Box

Audio-Visual Applications

–

High Performance: (Typical, Differential,

48 kHz)

–

THD+N: –94 dB

SNR: 105 dB

DESCRIPTION

Dynamic Range: 104 dB

–

Sampling Rate: 16–192 kHz

The PCM3060 is

a low-cost, high-performance,

single-chip, 24-bit stereo audio codec with

single-ended analog inputs and differential analog

outputs.

System Clock: 128, 192, 256, 384,

512, 768 f_S

–

Differential Voltage Output: 8 Vp-p

Single-Ended Voltage Output: 4 Vp-p

Analog Low-Pass Filter Included

4×/8× Oversampling Digital Filter:

The stereo 24-bit ADC employs

a

64-times

delta-sigma modulator. It supports 16–96 kHz

sampling rates and a 16/24-bit digital audio output

word on the audio interface.

–

Pass-Band Ripple: ±0.04 dB

The stereo 24-bit DAC employs a 64- or 128-times

delta-sigma modulator. It supports 16–192 kHz

sampling rates and a 16/24-bit digital audio input

word on the audio interface.

Stop-Band Attenuation: –50 dB

–

Zero Flags

•

Flexible Mode Control

The PCM3060 supports fully independent operation

of the sampling rate and audio interface for the ADC

and DAC.

Each audio interface supports I²S, left-justified, and

right-justified formats with 16/24-bit words.

–

3-Wire SPI, 2-Wire I²C Compatible Serial

Control Interface

–

Hardware Control Mode

•

Multiple Functions via SPI or I²C Interface:

–

Digital Attenuation and Soft Mute for ADC

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

PCM3060

www.ti.com

SLAS533B–MARCH 2007–REVISED MARCH 2008

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION (CONTINUED)

The PCM3060 can be software-controlled through a 3-wire SPI-compatible or 2-wire I²C-compatible serial

interface, which provides access to all functions including digital attenuation, soft mute, de-emphasis etc.

The PCM3060 can be also used in hardware mode, which provides three basic functions.

The PCM3060 is fabricated using a highly advanced CMOS process and is available in a small 28-pin TSSOP

package.

The PCM3060 is suitable for various sound processing applications for DVD-RW, digital TV, STB, and other AV

equipment.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE

UNIT

V_CC

V_DD

–0.3 to 6.5

Supply voltage

V

–0.3 to 4

Ground voltage differences AGND1, AGND2, DGND, SGND

RST, MS, MC, MD, SCKI1, SCKI2, DIN

±0.1

–0.3 to 6.5

V

Digital input voltage

BCK1, BCK2, LRCK1, LRCK2, DOUT

ZEROL, ZEROR, MODE

–0.3 to (V_DD+ 0.3 V) < 4

–0.3 to (V_CC+ 0.3 V) < 6.5

±10

V

Analog input voltage

V_INL, V_INR, V_COM, V_OUTL+, V_OUTL–, V_OUTR+, V_OUTR–

V

Input current (any pins except supplies)

Ambient temperature under bias

Storage temperature

mA

°C

T_A

–40 to 125

T_stg

T_J

–55 to 150

Junction temperature

150

Lead temperature (soldering)

Package temperature (IR reflow, peak)

260, 5 s

260

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

NOM

5

MAX UNIT

V_CCAnalog supply voltage

V_DDDigital supply voltage

Digital input interface level

5.5

3.6

V

2.7

3.3

TTL compatible

Sampling frequency, LRCK1, LRCK2

System clock frequency, SCKI1, SCKI2

16

96/192

36.864

kHz

MHz

Vpp

kΩ

Digital input clock frequency

Analog input level

2.048

3

AC-coupled

DC-coupled

5

Analog output load resistance

10

kΩ

Analog output load capacitance

Digital output load capacitance

Operating free-air temperature

50

20

85

pF

–25

25

°C

2

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SLAS533B–MARCH 2007–REVISED MARCH 2008

ELECTRICAL CHARACTERISTICS

All specifications at T_A= 25°C, V_CC= 5 V, V_DD= 3.3 V, f_S= 48 kHz, SCKI1 = SCKI2 = 512 f_S, 24-bit data (unless otherwise

noted).

PCM3060PW

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

DIGITAL INPUT/OUTPUT

DATA FORMAT

Audio data interface format

I²S, LJ, RJ

16, 24

Audio data word length

Audio data format

Bits

MSB-first, 2s-complement

Sampling frequency, ADC

Sampling frequency, DAC

System clock frequency

16

48

96

192

f_S

kHz

128, 192, 256, 384, 512, 768 f_S

2.048

36.864

MHz

INPUT LOGIC

(1)

V_IH

2

V_DD

0.8

(1)

V_IL

Input logic level

VDC

µA

(2) (3)

V_IH

5.5

(2) (3)

V_IL

0.8

(2)

I_IH

V_IN= V_DD

V_IN= 0 V

V_IN= V_DD

V_IN= 0 V

±10

100

±10

(2)

I_IL

Input logic current

(1) (3)

I_IH

65

(1) (3)

I_IL

OUTPUT LOGIC

(4)

V_OH

I_OUT= –4 mA

I_OUT= 4 mA

2.8

Output logic level

VDC

(4) (5)

V_OL

REFERENCE OUTPUT

V_COMoutput voltage

0.5

0.5 V_CC

12.5

V

V_COMoutput impedance

7

18

±1

kΩ

Allowable V_COMoutput

source/sink current

µA

ADC CHARACTERISTICS

Resolution

ANALOG INPUT

16

24

Bits

Full scale input voltage

Center voltage

V_INL, V_INR = 0 dB

0.6 V_CC

0.5 V_CC

10

Vp-p

V

Input impedance

kΩ

Antialiasing filter response

–3 dB

300

kHz

DC ACCURACY

Gain mismatch,

channel-to-channel

Full-scale input, V_INL, V_IN

R

±2

±8 % of FSR

Gain error

Full-scale input, V_INL, V_IN

±2

±8 % of FSR

±2 % of FSR

Bipolar zero error

HPF bypass, V_INL, V_IN

R

±0.5

(1) BCK1, BCK2, LRCK1, LRCK2 (in slave mode, Schmitt-trigger input with 50-kΩ typical internal pulldown resistor)

(2) SCKI1, SCKI2, DIN, MS/ADR/IFMD, MC/SCL/FMT, MD/SDA/IFMD (Schmitt-trigger input, 5-V tolerant).

(3) RST (Schmitt-trigger input with 50-kΩ typical internal pulldown resistor, 5-V tolerant).

(4) BCK1, BCK2, LRCK1, LRCK2 (in master mode), DOUT, ZEROL, ZEROR

(5) MD/SDA/IFMD (in I²C mode, open drain LOW output)

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SLAS533B–MARCH 2007–REVISED MARCH 2008

ELECTRICAL CHARACTERISTICS (continued)

All specifications at T_A= 25°C, V_CC= 5 V, V_DD= 3.3 V, f_S= 48 kHz, SCKI1 = SCKI2 = 512 f_S, 24-bit data (unless otherwise

noted).

PCM3060PW

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

(6) (7)

DYNAMIC PERFORMANCE

V_IN= –1 dB, f_S= 48 kHz

–93

99

–85

THD+N

Total harmonic distortion + noise

dB

V_IN= –1 dB, f_S= 96 kHz

f_S= 48 kHz, A-weighted

f_S= 96 kHz, A-weighted

f_S= 48 kHz, A-weighted

f_S= 96 kHz, A-weighted

f_S= 48 kHz

95

92

Dynamic range

101

99

SNR

Signal-to-noise ratio

101

96

Channel separation

(between L-ch and R-ch)

f_S= 96 kHz

98

f_S1 = 48 kHz, f_S2 = 44.1 kHz

f_S1 = 96 kHz, f_S2 = 44.1 kHz

96

Crosstalk from DAC

98

DIGITAL FILTER PERFORMANCE

0.454

f_S

Pass band

Hz

0.583

f_S

Stop band

Pass-band ripple

< 0.454 f_S

> 0.583 f_S

±0.05

dB

s

Stop-band attenuation

Group delay time

–65

17.4/f_S

0.019 f_S

/1000

HPF frequency response

–3 dB

Hz

DAC CHARACTERISTICS

Resolution

16

24

Bits

ANALOG OUTPUT

Single-ended

Differential

Single-ended

Differential

AC-coupled

DC-coupled

f = 20 kHz

f = 44 kHz

–3 dB

0.8 V_CC

1.6 V_CC

0.5 V_CC

0.48 V_CC

Output voltage

Center voltage

Load impedance

Vp-p

V

5

kΩ

10

–0.02

–0.07

300

dB

LPF frequency response

kHz

DC ACCURACY

Gain mismatch,

channel-to-channel

±1

±4 % of FSR

±6 % of FSR

Gain error

±2

±1

Single-ended

±2

Bipolar zero error

% of FSR

Differential (V_OUTX+ – V_OUTX–)

(6) f_IN= 1 kHz, using System Two audio measurement system by Audio Precision, RMS mode with 20-kHz LPF and 400-Hz HPF.

(7) f_S= 96 kHz: SCKI1 = SCKI2 = 256 f_S, f_S= 192 kHz: SCKI1 = 512 f_Sat f_S= 48 kHz and SCKI2 = 128 f_Sat f_S= 192 kHz.

4

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SLAS533B–MARCH 2007–REVISED MARCH 2008

ELECTRICAL CHARACTERISTICS (continued)

All specifications at T_A= 25°C, V_CC= 5 V, V_DD= 3.3 V, f_S= 48 kHz, SCKI1 = SCKI2 = 512 f_S, 24-bit data (unless otherwise

noted).

PCM3060PW

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

(8) (9) (10)

DYNAMIC PERFORMANCE (SINGLE-ENDED)

V_OUT= 0 dB, f_S= 48 kHz

–93

–94

103

104

101

–85

THD+N

Total harmonic distortion + noise V_OUT= 0 dB, f_S= 96 kHz

V_OUT= 0 dB, f_S= 192 kHz

dB

f_S= 48 kHz, EIAJ, A-weighted

99

100

97

Dynamic range

f_S= 96 kHz, EIAJ, A-weighted

f_S= 192 kHz, EIAJ, A-weighted

f_S= 48 kHz, EIAJ, A-weighted

f_S= 96 kHz, EIAJ, A-weighted

f_S= 192 kHz, EIAJ, A-weighted

f_S= 48 kHz

SNR

Signal-to-noise ratio

Channel separation

Crosstalk from ADC

f_S= 96 kHz

f_S= 192 kHz

f_S1 = 48 kHz, f_S2 = 44.1 kHz

f_S1 = 48 kHz, f_S2 = 88.2 kHz

97

f_S1 = 48 kHz, f_S2 = 176.4 kHz

(8) (9) (11)

DYNAMIC PERFORMANCE (DIFFERENTIAL)

V_OUT= 0 dB, f_S= 48 kHz

–94

–95

104

105

103

THD+N

Total harmonic distortion + noise V_OUT= 0 dB, f_S= 96 kHz

V_OUT= 0 dB, f_S= 192 kHz

dB

f_S= 48 kHz, EIAJ, A-weighted

Dynamic range

f_S= 96 kHz, EIAJ, A-weighted

f_S= 192 kHz, EIAJ, A-weighted

f_S= 48 kHz, EIAJ, A-weighted

f_S= 96 kHz, EIAJ, A-weighted

f_S= 192 kHz, EIAJ, A-weighted

f_S= 48 kHz

SNR

Signal-to-noise ratio

Channel separation

Crosstalk from ADC

f_S= 96 kHz

f_S= 192 kHz

f_S1 = 48 kHz, f_S2 = 44.1 kHz

f_S1 = 48 kHz, f_S2 = 88.2 kHz

f_S1 = 48 kHz, f_S2 = 176.4 kHz

SHARP ROLLOFF

DIGITAL FILTER PERFORMANCE

0.454

f_S

Pass band

Hz

0.546

f_S

Stop band

Pass-band ripple

< 0.454 f_S

> 0.546 f_S

±0.04

dB

Stop-band attenuation

–50

(8) f_S= 96 kHz: SCKI1 = SCKI2 = 256 f_S, f_S= 192 kHz: SCKI1 = 512 f_Sat f_S= 48 kHz and SCKI2 = 128 f_Sat f_S= 192 kHz.

(9) f_OUT= 1 kHz, using System Two audio measurement system by Audio Precision, RMS mode with 20-kHz LPF and 400-Hz HPF.

(10) Assumed 5-kΩ AC-coupled second-order LPF and 115-dB or higher- performance buffer.

(11) Assumed 10-kΩ DC-coupled second-order LPF and 115- dB or higher-performance differential to single-ended converter.

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SLAS533B–MARCH 2007–REVISED MARCH 2008

ELECTRICAL CHARACTERISTICS (continued)

All specifications at T_A= 25°C, V_CC= 5 V, V_DD= 3.3 V, f_S= 48 kHz, SCKI1 = SCKI2 = 512 f_S, 24-bit data (unless otherwise

noted).

PCM3060PW

PARAMETER

TEST CONDITIONS

SLOW ROLLOFF

UNIT

MIN

TYP

MAX

DIGITAL FILTER PERFORMANCE

0.308

f_S

Pass band

Hz

Stop band

Pass-band ripple

0.73 f_S

–35

Hz

dB

< 0.308 f_S

> 0.73 f_S

±0.5

Stop-band attenuation

DIGITAL FILTER PERFORMANCE

Group delay time

20/f_S

±0.1

s

De-emphasis error

dB

POWER SUPPLY REQUIREMENTS

V_CC

4.5

2.7

5

3.3

25

5.5

3.6

36

Voltage range

V_DD

VDC

f_S= 48 kHz/ADC, f_S= 48 kHz/DAC

f_S= 96 kHz/ADC, f_S= 96 kHz/DAC

f_S1 = 48 kHz/ADC, f_S2 = 192 kHz/DAC

f_S= 48 kHz/ADC, power down/DAC

Power down/ADC, f_S= 48 kHz/DAC

mA

µA

25

I_CC

12

13

(12) (13)

Full power down

780

9

Supply current

f_S= 48 kHz/ADC, f_S= 48 kHz/DAC

f_S= 96 kHz/ADC, f_S= 96 kHz/DAC

f_S1 = 48 kHz/ADC, f_S2 = 192 kHz/DAC

f_S= 48 kHz/ADC, power down/DAC

Power down/ADC, f_S= 48 kHz/DAC

Full power down ⁽¹²⁾

12

mA

µA

16

13

I_DD

5

150

160

180

170

77

f_S= 48 kHz/ADC, f_S= 48 kHz/DAC

f_S= 96 kHz/ADC, f_S= 96 kHz/DAC

f_S1 = 48 kHz/ADC, f_S2 = 192 kHz/DAC

f_S= 48 kHz/ADC, power down/DAC

Power down/ADC, f_S= 48 kHz/DAC

Full power down ^{(12) (13)}

220

Power dissipation

mW

82

4.4

TEMPERATURE RANGE

Operation temperature

–25

85

°C

θ_JA

Thermal resistance

105

°C/W

(12) Halt SCKI1, SCKI2, BCK1, BCK2, LRCK1, LRCK2

(13) AC-coupled configuration. If DC-coupled configuration is used, DC current flow to external load is added and it depends on external load

resistance.

6

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SLAS533B–MARCH 2007–REVISED MARCH 2008

PIN ASSIGNMENTS

PCM3060

PW (TSSOP) PACKAGE

(TOP VIEW)

1

MC/SCL/FMT

MD/SDA/DEMP

DOUT

28

27

26

25

24

23

22

21

20

19

18

17

16

15

MODE

2

MS/ADR/IFMD

V_INR

3

4

LRCK1

BCK1

V_INL

5

V_CC

SCKI1

AGND1

6

7

V_DD

AGND2

V_COM

DGND

8

SCKI2

9

V_OUTL+

V_OUTL–

BCK2

10

11

12

13

14

LRCK2

DIN

V_OUTR+

V_OUTR–

SGND

RST

ZEROR

ZEROL

P0043-03

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SLAS533B–MARCH 2007–REVISED MARCH 2008

Table 1. TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

23

22

5

AGND1

AGND2

BCK1

–

ADC analog ground

DAC analog ground

I/O⁽¹⁾Audio data bit clock input/output for ADC

I/O⁽¹⁾Audio data bit clock input/output for DAC

BCK2

10

8

DGND

–

I⁽²⁾

O

Digital ground

DIN

12

3

Audio data digital input for DAC

Audio data digital output for ADC

DOUT

LRCK1

LRCK2

MC/SCL/FMT

MD/SDA/DEMP

4

I/O⁽¹⁾Audio data left/right clock input/output for ADC

I/O⁽¹⁾Audio data left/right clock input/output for DAC

11

1

I ⁽²⁾

Mode control, clock for SPI, clock for I²C, format for H/W mode⁽⁵⁾

2

I/O⁽³⁾Mode control, data for SPI, data for I²C, de-emphasis for H/W mode

This pin provides four operation modes according to its input connection. Connected directly to

V_DD: SPI mode. Connected to VDD through 220-kΩ pullup resistor: H/W mode, single-ended

V_OUTX. Connected to DGND through 220-kΩ pulldown resistor: H/W mode, differential V_OUTX.

Connected directly to DGND : I²C mode.

(4)

MODE

28

I

MS/ADR/IFMD

RST

27

15

6

I ⁽²⁾

Mode control, select for SPI with low active, address for I²C, I/F mode for H/W mode

Reset and power-down control input, active-low

System clock input for ADC

(5)

I

SCKI1

SCKI2

SGND

V_CC

I⁽²⁾

–

9

System clock input for DAC

16

24

21

7

Shield analog ground

–

ADC, DAC analog power supply, 5-V

V_COM

–

ADC, DAC voltage common decoupling

V_DD

–

Digital power supply, 3.3-V

V_IN

L

25

26

19

20

14

13

17

18

I

Analog input to ADC, L-channel

V_INR

I

Analog input to ADC, R-channel

V_OUTL–

V_OUTL+

ZEROL

ZEROR

V_OUTR–

V_OUTR+

O

Analog output from DAC, L-channel – in differential mode, must be open in single-ended mode

Analog output from DAC, L-channel + in differential mode, L-channel in single-ended mode

Zero flag, L-channel

Zero flag, R-channel

Analog output from DAC, R-channel – in differential mode, must be open in single-ended mode

Analog output from DAC, R-channel + in differential mode, R-channel in single-ended mode

(1) Schmitt-trigger input/output with 50-kΩ typical internal pulldown resistor

(2) Schmitt-trigger input, 5-V tolerant

(3) Schmitt-trigger input, 5 V tolerant for SPI, H/W mode and Schmitt-trigger input/open drain LOW output, 5-V tolerant for I²C

(4) V_DD/2 biased, quad-state input

(5) Schmitt-trigger input with 50-kΩ typical internal pulldown resistor, 5-V tolerant

8

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SLAS533B–MARCH 2007–REVISED MARCH 2008

BLOCK DIAGRAM

SE to Diff.

Converter

Delta-Sigma

Modulator

V_INL

V_DD

Decimation Filter

with HPF

DGND

SE to Diff.

Converter

Delta-Sigma

Modulator

V_INR

DOUT

LRCK1

V_CC

BCK1

Audio

AGND1

SGND

Common

and

Reference

Interface

and

Clock

SCK1

SCK2

BCK2

LRCK2

DIN

Voltage Common and Reference

AGND2

V_COM

Control

ZEROR

V_OUTR–

Multi-Level

Delta-Sigma

Modulator

LPF and

Buffer

V_OUTR+

RST

Interpolation Filter

with Digital Function

MODE

Mode

Control

MS/ADR/IFMD

MC/SCL/FMT

MD/SDA/DEMP

V

_OUTL+

Multi-Level

Delta-Sigma

Modulator

LPF and

Buffer

V_OUTL–

ZEROL

B0229-01

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SLAS533B–MARCH 2007–REVISED MARCH 2008

TYPICAL PERFORMANCE CURVES OF ADC INTERNAL FILTER

All specifications at T_A= 25°C, V_CC= 5 V, V_DD= 3.3 V, f_S= 48 kHz, SCKI1 = SCKI2 = 512 f_S, 24-bit data,

unless otherwise noted.

DIGITAL FILTER

DECIMATION FILTER, STOP-BAND CHARACTERISTICS

DECIMATION FILTER, PASS-BAND CHARACTERISTICS

0.1

0

−20

0.0

−0.1

−0.2

−0.3

−0.4

−0.5

−40

−60

−80

−100

−120

−140

−160

0

8

16

24

32

0.0

0.1

0.2

0.3

0.4

0.5

Normalized Frequency [×f ]

S

G001

G002

Figure 1.

Figure 2.

ANALOG FILTER

HIGH-PASS FILTER CHARACTERISTICS

ANTIALIASING FILTER CHARACTERISTICS

0

−5

0

−5

−10

−15

−20

−25

−30

−35

−40

−45

−50

−10

−15

−20

−25

−30

−35

−40

−45

−50

0.0

0.1

0.2

0.3

0.4

1

10

100

1k

10k

f − Frequency − kHz

Normalized Frequency [×f /1000]

S

G004

G003

Figure 3.

Figure 4.

10

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SLAS533B–MARCH 2007–REVISED MARCH 2008

TYPICAL PERFORMANCE CURVES OF DAC INTERNAL FILTER

All specifications at T_A= 25°C, V_CC= 5 V, V_DD= 3.3 V, f_S= 48 kHz, SCKI1 = SCKI2 = 512 f_S, 24-bit data,

unless otherwise noted.

DIGITAL FILTER

INTERPOLATION FILTER, STOP BAND

INTERPOLATION FILTER, PASS BAND

(SHARP-ROLL OFF)

0.1

0.0

0

−20

−40

−0.1

−0.2

−0.3

−0.4

−0.5

−60

−80

−100

−120

−140

−160

0

1

2

3

4

0.0

0.1

0.2

0.3

0.4

0.5

Normalized Frequency [×f ]

S

G005

G006

Figure 5.

Figure 6.

ANALOG FILTER

DE-EMPHASIS FILTER CHARACTERISTICS

(f_S= 44.1 kHz)

LOW-PASS FILTER CHARACTERISTICS

0

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

0

−10

−20

−30

−40

−50

0

2

4

6

8

10 12 14 16 18 20

1

10

100

1k

10k

f − Frequency − kHz

G007

G008

Figure 7.

Figure 8.

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TYPICAL ADC PERFORMANCE CURVES

All specifications at T_A= 25°C, V_CC= 5 V, V_DD= 3.3 V, f_S= 48 kHz, SCKI1 = SCKI2 = 512 f_S, 24-bit data,

unless otherwise noted.

THD+N at –1 dB vs TEMPERATURE

DYNAMIC RANGE and SNR vs TEMPERATURE

−88

−90

−92

−94

−96

−98

−100

104

102

100

98

V

IN

= –0.5 dB

Dynamic Range

SNR

96

94

92

−25

0

25

50

75

100

0

25

50

75

100

T

A

− Free-Air Temperature − °C

T

A

− Free-Air Temperature − °C

G009

G010

Figure 9.

Figure 10.

THD+N at –1 dB vs SUPPLY VOLTAGE

DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE

−88

−90

−92

−94

−96

−98

−100

104

102

100

98

V

IN

= –1 dB

Dynamic Range

SNR

96

94

92

4.50

4.75

V

5.00

5.25

5.50

4.75

V

5.00

5.25

5.50

− Supply Voltage − V

CC

G011

G012

Figure 11.

Figure 12.

12

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TYPICAL DAC PERFORMANCE CURVES

All specifications at T_A= 25°C, V_CC= 5 V, V_DD= 3.3 V, f_S= 48 kHz, SCKI1 = SCKI2 = 512 f_S, 24-bit data,

unless otherwise noted.

THD+N vs TEMPERATURE

DYNAMIC RANGE and SNR vs TEMPERATURE

−90

−92

110

108

106

104

102

100

98

SNR

−94

−96

Dynamic Range

−98

−100

−102

−25

0

25

50

75

100

−25

0

25

50

75

100

T

A

− Free-Air Temperature − °C

T

A

− Free-Air Temperature − °C

G013

G014

Figure 13.

Figure 14.

THD+N vs SUPPLY VOLTAGE

DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE

−90

−92

110

108

106

104

102

100

98

−94

SNR

−96

Dynamic Range

−98

−100

−102

4.50

4.75

V

5.00

5.25

5.50

4.50

4.75

V

5.00

5.25

5.50

− Supply Voltage − V

CC

G015

G016

Figure 15.

Figure 16.

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TYPICAL PERFORMANCE CURVES

All specifications at T_A= 25°C, V_CC= 5 V, V_DD= 3.3 V, f_S= 48 kHz, SCKI1 = SCKI2 = 512 f_S, 24-bit data,

unless otherwise noted.

ADCs OUTPUT SPECTRUM

OUTPUT SPECTRUM (–1 dB, N=32768)

OUTPUT SPECTRUM (–60 dB, N=32768)

0

−20

0

−20

−40

−60

−80

−100

−120

−140

−100

−120

−140

0

5

10

15

20

0

5

10

15

20

f − Frequency − kHz

G017

G018

Figure 17.

Figure 18.

DAC OUTPUT SPECTRUM

OUTPUT SPECTRUM (0 dB, N=32768)

OUTPUT SPECTRUM (–60 dB, N=32768)

0

−20

0

−20

−40

−60

−80

−100

−120

−140

−100

−120

−140

0

5

10

15

20

0

5

10

15

20

f − Frequency − kHz

G019

G020

Figure 19.

Figure 20.

14

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SLAS533B–MARCH 2007–REVISED MARCH 2008

DEVICE DESCRIPTION

ASYNCHRONOUS OPERATION

The PCM3060 supports complete asynchronous operation between the ADC and DAC by receiving two

independent system clocks on SCKI1 and SCKI2.

Also, the PCM3060 supports synchronous operation between ADC and DAC by receiving one common system

clock on either SCKI1 or SCKI2 and controlling the system clock configuration through register 67 or 72 in serial

mode control.

SYSTEM CLOCK

The PCM3060 requires two system clocks for operating the ADC and DAC blocks independently, or it requires

one common clock for synchronous ADC and DAC operation.

The system clock for the ADC of the PCM3060 must be 256, 384, 512, or 768 f_S, where f_Sis the audio sampling

rate for the ADC, 16 to 96 kHz.

The system clock for the DAC of the PCM3060 must be 128, 192, 256, 384, 512, or 768 f_S, where f_Sis the audio

sampling rate for the DAC, 16 to 192 kHz.

Table 2 lists the typical system clock frequencies, f_SCKI1and f_SCKI2for common audio sampling rates, and

Figure 21 shows the timing requirements for the system clock inputs.

Table 2. System Clock Frequencies for Common Audio Sampling Clock Frequencies

SAMPLING

FREQUENCY

(kHz)

SYSTEM CLOCK FREQUENCY, f_SCKI1, f_SCKI2[MHz]

(1)

128 f_S

192 f_S

256 f_S

384 f_S

512 f_S

768 f_S

16

32

2.048

4.096

3.072

6.144

4.096

8.192

6.144

12.288

16.9344

18.432

33.8688

36.864

See ⁽²⁾

8.192

16.384

22.5792

24.576

See ⁽²⁾

12.288

24.576

33.8688

36.864

See ⁽²⁾

44.1

48

5.6488

6.144

8.4672

9.216

11.2896

12.288

22.5792

24.576

88.2

11.2896

12.288

22.5792

24.576

16.9344

18.432

33.8688

36.864

96

176.4 ⁽¹⁾

192 ⁽¹⁾

See

(2)

See ⁽²⁾

(1) This combination of sampling clock frequency and system clock frequency is supported only for the DAC.

(2) This system clock frequency is not supported for the given sampling clock frequency.

t_w(SCH)

H

2 V

System Clock

(SCK1, SCK2)

0.8 V

L

t_w(SCL)

t_(SCY)

T0005-14

SYMBOL

t_(SCY)

PARAMETERS

MIN

25

MAX

UNIT

System clock cycle time

System clock high time

System clock low time

System clock duty cycle

ns

t_w(SCH)

t_w(SCL)

0.4 t_(SCY)

40%

60%

Figure 21. System Clock Input Timing

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SLAS533B–MARCH 2007–REVISED MARCH 2008

POWER-ON RESET AND EXTERNAL RESET SEQUENCE

The PCM3060 has both an internal power-on reset circuit and an external reset circuit. The sequences for both

resets are shown in the following.

Figure 22 illustrates the timing of the internal power-on reset. Initialization (reset) is done automatically at the

time when V_DDexceeds 2.2 V typical.

Internal reset is released 1024 SCKIx (x = 1, 2) after power on if the H/W control mode is selected and RST is

kept HIGH; then the PCM3060 begins normal operation. If the S/W control mode is selected and RST is kept

HIGH, internal reset is released 1024 SCKIx after the reset of ADPSV and DAPSV through serial control port;

then the PCM3060 begins normal operation. If RST is kept LOW, internal reset is held and the reset sequence is

frozen until RST is changed from LOW to HIGH. V_OUTL and V_OUTR from the DAC are forced to the V_COM(= 0.5

V_CC) level as V_CCrises. If synchronization is maintained among SCKIx, BCKx, and LRCKx, V_OUTL and V_OUTR go

into the fade-in sequence after t_DACDLY1= 2048/f_Sfrom internal reset release. Then V_OUTL and V_OUTR provide

outputs corresponding to DIN after t_DACDLY2= 1616/f_Sfrom the start of fade-in. Similarly, DOUT from the ADC is

enabled and goes into the fade-in sequence after t_ADCDLY1= 2048/f_Sfrom internal reset release, and then DOUT

provides an output corresponding to V_INL and V_INR after t_ADCDLY2= 1936/f_Sfrom the start of fade-in. If

synchronization is not held, the internal reset is not released and operation mode is kept on reset and

power-down state. After resynchronization, the DAC begins its fade-in sequence, and the ADC also begins

fade-in operation after internal initialization and an initial delay.

Figure 23 is the timing chart of the external reset. The RST pin initiates external forced reset when RST is held

LOW for at least t_RST= 2048/f_S; it resets the device places it in the power-down state, which is the lowest-power

dissipation state in the PCM3060.

When RST transitions from HIGH to LOW while SCKIx, BCKx, and LRCKx are synchronized, V_OUTL and V_OUT

R

are forced to the V_COM(= 0.5 V_CC) level after the fade-out sequence lasting t_DACDLY2= 1616/f_S, and DOUT is

forced to ZERO after t_ADCDLY2= 1936/f_Sfade-out sequence. After that, the internal reset becomes LOW, the

PCM3060 resets and enters into the power-down state, finally all registers and memory except mode control

registers are reset. To resume into normal operation, changing RST to HIGH again is required, and the sequence

shown in Figure 22 is performed. It is possible to halt SCKIx, BCKx and LRCKx during the power-down state, but

all clocks must be resumed prior to starting the power-up sequence. The same fade-in/-out sequence of V_OUTL/R

and DOUT can be obtained by setting the ADPSV and DAPSV bits through serial mode control port.

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POWER-ON RESET AND EXTERNAL RESET SEQUENCE (Continued)

(V_DD= 3.3 V typ.)

(V_DD= 2.7 V min.)

V_DD

(V_DD= 2.2 V typ.)

0 V

SCKIx,

BCKx,

LRCKx

Synchronous Clocks

MODE

RST

ADPSV

DAPSV

(1)

1024 SCKIx

Power Down

Internal

Reset

Normal Operation

t_(DACDLY1)

2048/f_S

t_(DACDLY2)

1616/f_S

V_OUTL+/–

V_OUTR+/–

0.5 V_CC

V_COM(0.5 V_CC

)

t_(ADCDLY1)

2048/f_S

t_(ADCDLY2)

1936/f_S

DOUT

ZERO

Fade-in

T0097-02

NOTE: Release from the power-save mode is required if the software control mode is selected.

Figure 22. DAC Output and ADC Output for Power-On Reset

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(V_DD= 3.3 V typ.)

V_DD

0 V

SCKIx,

BCKx,

LRCKx

Synchronous Clocks

MODE

RST

t_RST

2048/f_Smin.

ADPSV

DAPSV

(1)

1024 SCKIx

Internal

Reset

Normal Operation

Power Down

t_(DACDLY1)

2048/f_S

t_(DACDLY2)

1616/f_S

t_(DACDLY2)

1616/f_S

V_OUTL+/–

V_OUTR+/–

0.5 V_CC

V_COM(0.5 V_CC

)

t_(ADCDLY2)

1936/f_S

t_(ADCDLY1)

2048/f_S

t_(ADCDLY2)

1936/f_S

DOUT

Fade-out

ZERO

Fade-in

T0098-02

(1) ADPSV and DAPSV control V_OUTL/R and DOUT, respectively, with fade-in/out the same as for RST.

Figure 23. DAC Output and ADC Output for External Reset

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SLAS533B–MARCH 2007–REVISED MARCH 2008

PCM AUDIO INTERFACE

Audio Interface Mode and Timing

The digital audio data can be interfaced in either slave or master mode, and this interface mode is selectable

using the serial mode control described in the Mode Control section.

The interface mode is also selectable independently for the ADC and the DAC. DIN is always input to the

PCM3060 and DOUT is always an output from the PCM3060. Slave mode is the default mode for both the ADC

and the DAC.

In slave mode, BCK1/2 and LRCK1/2 are inputs to the PCM3060, and BCK1/2 must be either 64 f_Sor 48 f_S. DIN

is sampled on the rising edge of BCK2, and DOUT is changed on the falling edge of BCK1. The default timing

specification is shown in Figure 24.

In master mode, BCK1/2 and LRCK1/2 are outputs from the PCM3060. BCK1/2 and LRCK1/2 are generated by

the PCM3060 from SCKI1/2, and BCK1/2 is fixed at 64 f_S. DIN is sampled on the rising edge of BCK2, and

DOUT is changed on the falling edge of BCK1. The detailed timing specification is shown in Figure 25.

t_(BCH)

t_(BCL)

BCK1/2

(Input)

1.4 V

t_(BCY)

t_(LRH)

t_(LRS)

LRCK1/2

(Input)

1.4 V

t_(DOD)

0.5 V_DD

DOUT

t_(DIS)

t_(DIH)

DIN

1.4 V

T0247-01

SYMBOL

t_(BCY)

DESCRIPTION

MIN

75

35

10

15

TYP

MAX

UNIT

ns

BCK1/2 cycle time

t_{w (BCH)}

t_{w (BCL)}

t_(LRS)

BCK1/2 high time

BCK1/2 low time

ns

LRCK1/2 set-up time to BCK1/2 rising edge

LRCK1/2 hold time to BCK1/2 rising edge

DIN setup time to BCK1/2 rising edge

DIN hold time to BCK1/2 rising edge

ns

t_(LRH)

t_(DIS)

ns

t_(DIH)

ns

t_(DOD)

DOUT delay time from BCK1/2 falling edge

70

ns

NOTE: Load capacitance of output is 20 pF.

Figure 24. Audio Data Interface Timing (Slave Mode: BCK1/2 and LRCK1/2 Work as Inputs)

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SCKI1/2

(Input)

1.4 V

t_(BCH)

t_(BCD)

t_(BCL)

t_(BCD)

BCK1/2

(Output)

0.5 V_DD

t_(BCY)

t_(LRD)

LRCK1/2

(Output)

t_(DOD)

DOUT

t_(DIS)

t_(DIH)

DIN

1.4 V

T0248-01

SYMBOL

t_(BCY)

PARAMETERS

MIN

TYP

MAX

UNIT

BCK1/2 cycle time

1/64 f_S

t_w(BCH)

t_w(BCL)

t_(LRD)

t_(DIS)

BCK1/2 high time

BCK1/2 low time

0.4 t_(BCY)

0.5 t_(BCY)0.6 t_(BCY)

30

0.4 t_(BCY)

LRCK1/2 delay time from BCK1/2 falling edge

DIN setup time to BCK1/2 rising edge

0

ns

10

0

t_(DIH)

DIN hold time to BCK1/2 rising edge

t_(DOD)

t_(BCD)

DOUT delay time from BCK1/2 falling edge

BCK1/2 delay time from SCKI1/2 rising edge⁽¹⁾

30

40

10

NOTE: Load capacitance of output is 20 pF.

(1) This specification applies for SCKI1/2 when the frequency is less than 25 MHz.

Figure 25. Audio Data Interface Timing (Master Mode: BCK1/2 and LRCK1/2 work as Outputs)

Audio Interface Format

The PCM3060 supports the following four interface formats in both slave and master modes, and they are

selectable independently for the ADC and DAC using serial mode control.

24-bit I²S format

24-bit left-justified format

24-bit right-justified format

16-bit right-justified format

All formats are provided in MSB-first, 2s complement data format.

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FMT1/2[1:0] = 00

24-Bit, MSB-First, I²S

LRCK1/2

Right-Channel

Left-Channel

BCK1/2

DIN

1

2

3

22 23 24

LSB

1

2

3

22 23 24

LSB

MSB

DOUT

1

2

22 23 24

LSB

1

2

22 23 24

LSB

MSB

FMT1/2[1:0] = 01

24-Bit, MSB-First, Left-Justified

LRCK1/2

Right-Channel

BCK1/2

DIN

1

2

3

22 23 24

1

2

3

22 23 24

LSB

1

MSB

LSB

MSB

DOUT

1

2

22 23 24

LSB

1

2

3

22 23 24

LSB

MSB

FMT1/2[1:0] = 10

24-Bit, MSB-First, Right-Justified

LRCK1/2

Right-Channel

BCK1/2

DIN 24

DOUT 24

1

2

3

22 23 24

LSB

1

2

3

22 23 24

LSB

MSB

1

2

22 23 24

LSB

1

2

22 23 24

LSB

MSB

FMT1/2[1:0] = 11

16-Bit, MSB-First, Right-Justified

LRCK1/2

Right-Channel

BCK1/2

DIN 16

DOUT 16

1

2

3

14 15 16

LSB

1

2

3

14 15 16

LSB

MSB

1

2

14 15 16

LSB

1

2

14 15 16

LSB

MSB

T0016-18

Figure 26. Audio Data Input/Output Format

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SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM

As the PCM3060 operates under the system clock (SCKI1/2) and the audio sampling clock (LRCK1/2), SCKI1/2

and LRCK1/2 must have a specific relationship in slave mode. The PCM3060 does not need a specific phase

relationship between audio the interface clocks (LRCK1/2, BCK1/2) and system clock (SCKI1/2), but does

require a frequency synchronization of LRCK1/2, BCK1/2, and SCKI1/2.

If the relationship between SCKI2 and LRCK2 changes more than ±6 BCK2s (BCK2 = 64 f_S) or ±5 BCK2s (BCK2

= 48 f_S) due to jitter or frequency change, etc., internal operation of DAC halts within 2/f_S, and analog output is

forced to V_COM(0.5V_CC) until resynchronization of SCKI2 to LRCK2 and BCK2 is completed and then t_DACDLY3

passes by.

If the relationship between SCKI1 and LRCK1 changes more than ±6 BCK1s (BCK1 = 64 f_S) or ±5 BCK1s (BCK1

= 48 f_S) due to jitter, frequency change, etc., internal operation of ADC halts within 2/f_S, and digital output is

forced into ZERO code until resynchronization of SCKI1 to LRCK1 and BCK1 is completed and then t_ADCDLY3

passes by.

In case of changes less than ±5 BCK1/2s (BCK1/2 = 64) or ±4 BCK1/2s (BCK1/2 = 48), resynchronization does

not occur, and previously described analog/digital output control and discontinuity do not occur.

Figure 27 illustrates the DAC analog output and ADC digital output for loss of synchronization.

During undefined data, it may generate some noise in audio signal. Also, the transition of normal to undefined

data and undefined or zero data to normal creates a discontinuity in the data on the analog and digital outputs,

which may generate some noise in the audio signal.

The ADC output, DOUT and DAC outputs, and V_OUTX hold the previous state if the system clock halts.

State of Synchronization

Synchronous

Asynchronous

Synchronous

t_(DACDLY3)

(22/f_S)

Within 2/f_S

Normal

V_COM

(0.5 V_CC

)

Undefined

Data

DAC V_OUTX+/–

Normal

t_(ADCDLY3)

(32/f_S)

Undefined

Data

ADC DOUT

Normal

Zero

Normal

T0020-08

Figure 27. DAC Output and ADC Output for Loss of Synchronization

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ANALOG INPUTS TO ADC

The PCM3060 has two independent input channels, V_INL and V_INR. These are single-ended (unbalanced) inputs,

each capable of 0.6-V_CCVpp input with 10-kΩ input resistance, typically.

ANALOG OUTPUTS FROM DAC

The PCM3060 has two independent output channels, V_OUTL and V_OUTR. These are differential, (balanced)

outputs, each capable of driving 0.8-V_CCVpp (1.6-Vpp in differential) typical with a 10-kΩ dc-coupled load. The

internal output amplifiers for V_OUTL+, V_OUTL– and V_OUTR+, V_OUTR– are biased to V_COM, described as follows.

The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy

present at the DAC outputs due to the noise shaping characteristics of the PCM3060 delta-sigma modulators.

The frequency response of this filter is shown in the typical performance curves. This filter is not enough to

attenuate the out-of-band noise to an acceptable level for many applications in general. An external low-pass

filter is used if further out-of-band noise rejection in required.

V_OUTX+, V_OUTX– configuration can be changed to single-ended (unbalanced) output via a MODE pin setting or

serial mode control, and V_OUTX+ is assigned as an output pin in single-ended mode.

V_COMOUTPUT

One unbuffered common voltage output pin, VCOM (pin 20) is brought out for decoupling purposes. This pin is

internally biased to a dc voltage level of 0.5 V_CCnominal, and is used as an internal common voltage and

reference voltage for the ADC and DAC. This pin can be used to bias an external circuit, but the load impedance

must be high enough for operation with the output resistance of this pin, which is 12.5 kΩ, typically.

OVERSAMPLING RATE CONTROL

The oversampling rate of ADC of PCM3060 is fixed at 64 f_S, but the oversampling rate of DAC of PCM3060 is

one of 64 f_S, 32 f_Sor 16 f_S, and this is automatically selected by the ratio of system clock frequency and sampling

frequency. And it can be also set to double rate, i.e., one of 128 f_S, 64 f_Sor 32 f_S, through serial control.

ZERO FLAGS

Zero-Detect Condition

For each DAC channel, the PCM3060 has a zero-detect circuit that recognizes zero detection when 1024

consecutive zeros have been sampled on DIN.

Zero-Flag Outputs

There are two zero-flag outputs, ZEROL and ZEROR. These pins can be used to operate external mute circuits,

or used as status indicators for a microcontroller, audio signal processor, etc. These pins can be programmed in

following two modes using the serial control port as described in the MODE CONTROL section.

DESCRIPTION

AZRO

ZEROL

ZEROR

0 (default)

1

L-ch zero detection

R-ch zero detection

L-ch and R-ch zero detection

For zero detection, these pins are set to HIGH (1) by default, but the polarity of the zero-flag outputs can be

inverted through the serial control port.

ZREV

0 (default)

1

DESCRIPTION

HIGH for zero detection

LOW for zero detection

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MODE CONTROL

The PCM3060 supports the following three types of mode control interface and four types of operation

configuration, according to the input state of MODE (pin 28) as follows. The pullup or pulldown resistor must be

220 kΩ ±5%.

MODE

Tie to DGND

MODE CONTROL INTERFACE

2-wire (I²C) serial control, selectable V_OUTX configuration

Pulldown resistor to DGND

Pullup resistor to V_DD

Tie to V_DD

3-wire parallel control, differential V_OUT

3-wire parallel control, single-ended V_OUT

3-wire (SPI) serial control, selectable V_OUTX configuration

X

The input state of the MODE pin is sampled during power-on reset or external reset; therefore, an input change

after reset is ignored until the next reset is performed.

The definitions (assignments) of the following three pins are changed by this control mode setting.

DEFINITION

SPI

MD

MC

MS

I²C

H/W

DEMP

FMT

2

1

SDA

SCL

ADR

27

IFMD

In serial mode control, the actual mode control is performed by register write (and read) through an SPI- or

I²C-compatible serial control port.

In parallel mode control, three specific functions are controlled directly through high/low settings of three specific

pins.

PARALLEL HARDWARE CONTROL

IFMD (Interface Mode)

DESCRIPTION

LOW

HIGH

Slave mode for ADC, slave mode for DAC

Master (256 f_S) mode for ADC, slave mode for DAC

The audio interface of the ADC and DAC can be independent from each other, but mode selection is applied on

both.

FMT (Interface Format)

DESCRIPTION

LOW

HIGH

24-bit I²S for ADC and DAC

24-bit left-justified for ADC and DAC

The audio interface of the ADC and DAC can be independent from each other, but format selection is applied on

both.

DEMP (De-emphasis)

DESCRIPTION

LOW

HIGH

De-emphasis off

(1)

De-emphasis on

(1) The 44.1-kHz de-emphasis filter is always selected.

3-WIRE (SPI) SERIAL CONTROL

The PCM3060 supports SPI-compatible serial ports, which operate asynchronously to the audio serial interface.

The control interface consists of MD, MC, and MS. MD is the serial data input, used to program the mode control

registers. MC is the serial bit clock, used to shift the data into the control port. MS is the select input, used to

enable the mode control port.

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Register Write Operation

All single-write operations via the serial control port use 16-bit data words. Figure 28 shows the control data word

format. The most significant bit must be a 0. There are seven bits, labeled IDX[6:0], that set the register index

(address) for the write operation. The least significant eight bits, D[7:0], contain the data to be written to the

register specified by IDX[6:0].

Figure 29 shows the functional timing diagram for single-write operations on the serial control port. MS is held in

the High state until a register is to be written. To start the register write cycle, MS is set to the Low state. Sixteen

clocks are then provided on MC, corresponding to the 16 bits of the control data word on MD. After the sixteenth

clock cycle has completed, MS is set to High to latch the data into the indexed mode control register.

The PCM3060 supports the multiple-write operation in addition to the single-write operation. Multiple write is

performed by sending N-sets of 8-bit register data after the first 16 bits of register address and register data,

while keeping the MC clock and MS in the Low state. Closing the multiple-write operation is done by setting MS

to the High state.

LSB

D0

MSB

0

IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0

Register Index (or Address)

D7

D6

D5

D4

D3

D2

D1

Register Data

R0001-01

Figure 28. Control Data Word Format for MD

MS

MC

MD

X

0

D7 D6 D5 D4 D3 D2

D1 D0

X

0

IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0

IDX6

T0048-01

Figure 29. Register Write Operation

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Timing Requirements

Figure 30 shows a detailed timing diagram for the 3-wire serial control interface. These timing parameters are

critical for proper control port operation.

t_(MHH)

1.4 V

MS

MC

MD

t_(MSS)

t_(MCH)

t_(MCL)

t_(MSH)

1.4 V

t_(MCY)

LSB

1.4 V

t_(MDS)

t_(MDH)

T0013-10

SYMBOL

t_(MCY)

PARAMETER

MIN

MAX

UNIT

ns

MC cycle time

100

40

t_w(MCL)

t_{w (MCH)}

t_(MHH)

t_(MSS)

t_(MSH)

t_(MDH)

t_(MDS)

MC low-level time

MC high-level time

MS high-level time

ns

40

ns

t_(MCY)

15

ns

MS falling edge to MC rising edge

ns

MS rising edge from MC rising edge for LSB⁽¹⁾

15

ns

MD hold time

15

ns

MD setup time

15

ns

(1) MC rise edge for LSB to MS rise edge.

Figure 30. Control Interface Timing for SPI

TWO-WIRE (I²C) SERIAL CONTROL

The PCM3060 supports the I²C-compatible serial bus and the data transmission protocol for standard-mode and

fast-mode (C_Bmax = 100 pF) as a slave device. This protocol is explained in the well-known I²C 2.0

specification.

Slave Address

MSB

LSB

R/W

1

0

1

ADR

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The PCM3060 has 7 bits for its own slave address. The first six bits (MSBs) of the slave address are factory

preset to 10 0011. The next bit of the address byte is the device select bit, which can be user-defined by the

ADR pin (pin 27). Two PCM3060s at maximum can be connected on the same bus at one time. Each PCM3060

responds when it receives its own slave address.

Packet Protocol

A master device must control packet protocol, which consists of a start condition, slave address with read/write

bit, data if write or acknowledgment if read, and stop condition. The PCM3060 supports the slave receiver

function.

SDA

Sp

SCL

St

1-7

8

9

1-8

9

1-8

9

Slave Address

ACK

DATA

ACK

DATA

ACK

R/W

Start

Condition

Stop

Condition

R/W: Read Operation if 1; Otherwise, Write Operation

ACK: Acknowledgement of a Byte if 0, not Acknowledgement of a Byte if 1

DATA: 8 Bits (Byte)

T0049-06

Write Operation

The PCM3060 supports the receiver function. A master can write to any PCM3060 registers using single or

multiple accesses. The master sends a PCM3060 slave address with a write bit, a register address, and the

data. If multiple access is required, the address is that of the starting register, followed by the data to be

transferred. When the data are received properly, the index register is incremented by 1 automatically. When the

index register reaches 4Ah, the next value is 40h. When undefined registers are accessed, the PCM3060 does

not send an acknowledgment. Figure 31 is a diagram of the write operation. The register address and the write

data are 8-bit in MSB-first format.

Transmitter

Data Type

M

S

M

S

M

S

M

S

M

Reg Address

Sp

St Slave Address

ACK

Write Data 1 ACK

Write Data 2 ACK

ACK

W

M: Master Device S: Slave Device St: Start Condition W: Write ACK: Acknowledgement Sp: Stop Condition

R0002-04

Figure 31. Framework for Write Operation

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Timing Diagram

The detailed timing diagram for SCL and SDA is shown as follows.

Start

Repeated Start

Stop

t_(D-HD)

t_(SDA-F)

t_(P-SU)

t_(BUF)

t_(D-SU)

t_(SDA-R)

SDA

t_(SCL-R)

t_(S-HD)

t_(GW)

t_(LOW)

SCL

t_(S-HD)

t_(HI)

t_(S-SU)

t_(SCL-F)

T0050-04

Timing Characteristics

STANDARD MODE

FAST MODE

SYMBOL

PARAMETER

UNIT

MIN

MAX

MIN

MAX

f_(SCL)

SCL clock frequency

100

400

kHz

µs

ns

µs

ns

pF

V

t_(BUF)

t_(LOW)

t_(HI)

Bus free time between STOP and START conditions

Low period of the SCL clock

High period of the SCL clock

Setup time for START/repeated START condition

Hold time for START/repeated START condition

Data setup time

4.7

4

1.3

0.6

t_(S-SU)

t_(S-HD)

t_(D-SU)

t_(D-HD)

t_(SCL-R)

t_(SCL-F)

t_(SDA-R)

t_(SDA-F)

t_(P-SU)

t_(GW)

4.7

4

0.6

250

0

100

Data hold time

3450

1000

0

900

300

Rise time of SCL signal

20 + 0.1 C_B

0.6

Fall time of SCL signal

Rise time of SDA signal

Fall time of SDA signal

Setup time for STOP condition

Allowable glitch width

4

N/A

400

50

C_B

Capacitive load for SDA and SCL lines

100

Noise margin at high level for each connected device (including hysteresis)

Noise margin at low level for each connected device (including hysteresis)

Hysteresis of Schmitt-trigger input

0.2 V_DD

0.1 V_DD

N/A

0.2 V_DD

0.1 V_DD

0.05 V_DD

V

Figure 32. Control Interface Timing for I²C

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MODE CONTROL REGISTERS

The PCM3060 has many user-programmable functions which are accessed via control registers, and they are

programmed through the SPI or I²C serial control port. Table 3 lists the available mode control functions along

with reset default conditions and associated register addresses. The register map is shown in Table 3.

Table 3. User-Programmable Mode Control Functions

FUNCTION RESET

Mode control register reset (ADC and DAC)

System reset (ADC and DAC)

DEFAULT

Normal operation

Power save

REGISTER

LABEL

MRST

SRST

ADPSV

DAPSV

S/E

64

ADC power-save control (ADC)

DAC power-save control (DAC)

Power save

VOUT configuration control (DAC)

Differential

Digital attenuation control, 0 dB to –100 dB in 0.5-dB steps

(DAC)

0 dB, no attenuation

65 and 66

AT21[7:0], AT22[7:0]

Clock select for DAC operation (DAC)

Master/slave mode for DAC audio interface (DAC)

Interface format for DAC audio interface (DAC)

Oversampling rate control (DAC)

Output phase select (DAC)

CLK2 enable

Slave

67

68

69

CSEL2

M/S 2[2:0]

FMT2[1:0]

OVER

I²S

Low (x64/x32/x16)

Normal

DREV2

Soft-mute control (DAC)

Mute disabled

Sharp rolloff

MUT22, MUT21

FLT

Digital filter rolloff control (DAC)

De-emphasis sampling rate selection (DAC)

De-emphasis function control (DAC)

Zero-flag polarity control (DAC)

44.1 kHz

DMF[1:0]

DMC

De-emphasis disabled

High for detection

L-ch, R-ch independent

ZREV

Zero-flag form select (DAC)

AZRO

Digital attenuation control, 20 dB to –100 dB in 0.5-dB steps

(ADC)

0 dB, no attenuation

70 and 71

AT11[7:0], AT12[7:0]

Clock select for ADC operation (ADC)

Master/slave mode for ADC audio interface (ADC)

Interface format for ADC audio interface (ADC)

Zero-cross detection disable for digital attenuation control (ADC)

HPF bypass control (ADC)

CLK1 enable

Slave

72

73

CSEL1

M/S1[2:0]

FMT1[1:0]

ZCDD

I²S

Zero-cross detection enabled

Bypass disabled

Normal

BYP

Input phase select (ADC)

DREV1

Soft-mute control (ADC)

Mute disabled

MUT12, MUT11

Table 4. Register Map

REGISTER ADDRESS

DATA

HEX

DEC

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

RSV⁽¹⁾

AT212

AT222

RSV⁽¹⁾

AT211

AT221

40h

Register 64

0

1

0

MRST

SRST

ADPSV DAPSV

RSV⁽¹⁾

S/E

41h

42h

Register 65

Register 66

0

1

0

1

0

AT217

AT227

AT216

AT226

AT215

AT225

AT214

AT224

AT213

AT223

AT210

AT220

RSV⁽¹⁾

43h

44h

45h

Register 67

Register 68

Register 69

0

1

0

1

0

1

0

1

CSEL2

M/S 22

OVER

DMF1

M/S 21

M/S 20

FMT21

FMT20

RSV⁽¹⁾

FLT

RSV⁽¹⁾

DMF0

RSV⁽¹⁾

DMC

DREV2 MUT22 MUT21

RSV⁽¹⁾

AT113

AT123

RSV⁽¹⁾

AT112

AT122

ZREV

AZRO

46h

47h

Register 70

Register 71

0

1

0

1

0

1

AT117

AT127

AT116

AT126

AT115

AT125

AT114

AT124

AT111

AT121

AT110

AT120

RSV⁽¹⁾

BYP

RSV⁽¹⁾

48h

49h

Register 72

Register 73

0

1

0

1

0

1

CSEL1

RSV⁽¹⁾

M/S 12

RSV⁽¹⁾

M/S 11

RSV⁽¹⁾

M/S 10

ZCDD

FMT11

FMT10

DREV1 MUT12 MUT11

(1) RSV means reserved for factory use or future extension, and these bits should be set to 0 during regular operation. Do not write any

values in addresses other than those listed.

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REGISTER DEFINITIONS

B15 B14 B13 B12 B11 B10

B9

0

B8

0

B7

B6

B5

B4

B3

B2

B1

B0

Register 64

0

1

0

MRST

SRST

ADPSV DAPSV

RSV

S/E

MRST: Mode Control Register Reset (ADC and DAC)

Default value: 1

MRST = 0

MRST = 1

Set default value

Normal operation (default)

The MRST bit controls reset of the mode control registers to their default values. Pop noise may be generated.

Returning the MRST bit to 1 is not required, as the MRST bit is automatically set to 1 after a mode control

register reset.

SRST: System Reset (ADC and DAC)

Default value: 1

SRST = 0

SRST = 1

Resynchronization

Normal operation (default)

The SRST bit controls system reset, the relation between system clock and sampling clock is re-synchronized,

and ADC operation and DAC operation is restarted. The mode control register is not reset and the PCM3060

does not go into power down state, but pop-noise may be generated. Returning the SRST bit to 1 is not required,

as the SRST bit is automatically set to 1 after triggering a system reset.

ADPSV: ADC Power-Save Control (ADC)

Default value: 1

ADPSV = 0

ADPSV = 1

Normal operation

Power-save mode (default)

The ADPSV bit controls the ADC power-save mode. In power-save mode, DOUT is forced to ZERO with a

fade-out sequence, the internal ADC data are reset, and the ADC goes into the power-down state. For

power-save mode release, a fade-in sequence is applied on DOUT during the resume process. The serial mode

control is enabled during this mode. A waiting time of more than 2048/f_Sis required for the proper status change

by this power save control on/off. As the default state after power on is the power-save mode and DOUT is

disabled (ZERO), release from the power-save mode is required for normal operation. The detailed sequence

and timing for ADPSV control is shown Figure 22 and Figure 23.

NOTE:

It is recommended that changing/stopping clocks or changing the audio interface

mode be performed in power-down mode in order to avoid unexpected pop/click noise

and performance degradation.

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DAPSV: DAC Power-Save Control (DAC)

Default value: 1

DAPSV = 0

DAPSV = 1

Normal operation

Power-save mode (default)

The DAPSV bit controls DAC power-save mode. In power-save mode, DAC outputs are forced to Vcom with a

fade-out sequence, the internal DAC data are reset and the DAC goes into the power-down state. For

power-save mode release, a fade-in sequence is applied on the DAC outputs in resume process. The serial

mode control is enabled during this mode. A waiting time of more than 2048/f_Sis required for the proper status

change by this power-save control on/off. As the default state after power on is the power-save mode and the

DAC outputs are disabled (V_COM), release from the power-save mode is required for normal operation. The

detailed sequence and timing for DAPSV control is shown Figure 22 and Figure 23.

NOTE:

It is recommended that changing/stopping clocks or changing the audio interface

mode be performed in power-down mode in order to avoid unexpected pop/click noise

and performance degradation.

S/E: DAC Output Configuration Control (DAC)

Default value: 0

S/E = 0

S/E = 1

Differential (default)

Single-ended

The S/E bit allows the user to select the configuration of the DAC output on the V_OUTX pins according to

application circuit.

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B15 B14 B13 B12 B11 B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Register 65

Register 66

0

1

0

1

AT217

B7

AT216

B6

AT215

B5

AT214

B4

AT213 AT212 AT211

AT210

B0

B15 B14 B13 B12 B11 B10

B9

B8

B3

B2

B1

0

1

0

1

0

AT227

AT226

AT225

AT224

AT223 AT222 AT221

AT220

AT2x[7:0]: Digital Attenuation Level Setting (DAC)

Where x = 1 or 2, corresponding to the DAC output V_OUTL (x = 1) and V_OUTR (x = 2).

Default value: 1111 1111b

AT2x[7:0]

1111 1111b

1111 1110b

1111 1101b

:

DECIMAL VALUE

ATTENUATION LEVEL SETTING

255

254

253

:

0 dB, no attenuation (default)

–0.5 dB

–1 dB

:

1000 0001b

1000 0000b

0111 1111b

:

129

128

127

:

–63 dB

–63.5 dB

–64 dB

:

0011 1000b

0011 0111b

0011 0110b

:

56

55

54

:

–99.5 dB

–100 dB

Mute

:

0000 0000b

0

Mute

Each DAC channel (V_OUTL and V_OUTR) has a digital attenuator function. The attenuation level may be set from 0

dB to –100 dB in 0.5-dB steps, and also may be set to infinite attenuation (mute). The attenuation level change

from current value to target value is performed by incrementing or decrementing one 0.5-dB step for every 8/f_S

time interval. While the attenuation level change sequence is in progress, new commands for attenuation level

change are not processed, but the new command overwrites the previous command in the command buffer. The

last command for attenuation level change is performed after the present attenuation level change sequence is

finished.

The attenuation level for each channel can be set individually using the following formula, and the foregoing table

shows attenuation levels for various settings:

Attenuation level (dB) = 0.5 × (AT2x[7:0]_DEC– 255), where AT2x[7:0]_DEC= 0 through 255 for AT2x[7:0]_DEC= 0

through 54, the level is set to infinite attenuation (mute).

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B15 B14 B13 B12 B11 B10

B9

1

B8

1

B7

B6

B5

B4

B3

B2

B1

B0

Register 67

0

1

0

CSEL2 M/S 22

M/S 21

M/S 20

RSV

FMT21 FMT20

CSEL2: Clock Select for DAC Operation

Default value: 0 (SCKI2, BCK2, LRCK2 enabled for DAC operation)

CSEL2 = 0

CSEL2 = 1

SCKI2, BCK2, LRCK2 enabled for DAC operation (default)

SCKI1, BCK1, LRCK1 enabled for DAC operation

The CSEL2 bit controls system clock and audio interface clocks for the DAC operation.

SCKI2, BCK2, LRCK2 are used for the DAC portion if CSEL2 = 0 (default), and SCKI1, BCK1, LRCK1 are used

for DAC operation if CSEL2 = 1.

M/S 2[2:0]: Audio Interface Mode for DAC

Default value: 000 (slave mode)

M/S 2[2:0]

0 0 0

Audio Interface Mode for DAC

Slave mode (default)

Master mode, 768 f_S

Master mode, 512 f_S

Master mode, 384 f_S

Master mode, 256 f_S

Master mode, 192 f_S

Master mode, 128 f_S

Reserved

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

The M/S 2[2:0] bits control the audio interface mode for the DAC.

FMT2[1:0]: Audio Interface Format for DAC

Default value: 00 (I²S Mode)

FMT2[1:0]

0 0

Audio Interface Format for DAC

24-bit I²S format (default)

24-bit left-justified format

0 1

1 0

24-bit right-justified format

16-bit right-justified format

1 1

The FMT2[1:0] bits control the audio interface format for the DAC.

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B15 B14 B13 B12 B11 B10

B9

0

B8

0

B7

B6

B5

B4

B3

B2

B1

B0

Register 68

0

1

0

1

RSV

OVER

RSV

DREV2

MUT22

MUT21

OVER: Oversampling Rate Control (DAC)

Default value: 0

OVER

System clock = 512 f_Sor 768 f_S

×64 Oversampling (default)

×128 Oversampling

System clock = 256 f_Sor 384 f_S

×32 Oversampling (default)

×64 Oversampling

System clock = 128 f_Sor 192 f_S

×16 Oversampling (default)

×32 Oversampling

OVER = 0

OVER = 1

The OVER bit is used to control the oversampling rate of the delta-sigma D/A converters.

Setting OVER = 1 might improve out-of-band noise characteristics in some application environments, but it might

also slightly affect baseband performance.

Writing over this bit during normal operation may generate pop noise.

DREV2: Output Phase Select (DAC)

Default value: 0

DREV2 = 0

DREV2 = 1

Normal output (default)

Inverted output

The DREV2 bit is used to control the phase of the analog signal outputs (V_OUTL and V_OUTR).

MUT2x: Soft Mute Control (DAC)

where x = 1 or 2, corresponding to the DAC output V_OUTL (x = 1) and V_OUTR (x = 2).

Default value: 0

MUT2x = 0

MUT2x = 1

Mute disabled (default)

Mute enabled

The mute bits, MUT21 and MUT22, are used to enable or disable the soft mute function for the corresponding

DAC outputs, V_OUTL and V_OUTR. The soft mute function is incorporated into the digital attenuators. When mute is

disabled (MUT2x = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUT2x = 1,

the digital attenuator for the corresponding output is decreased from the current setting to infinite attenuation at

the rate of one 0.5-dB step for every 8/f_Stime interval. By setting MUT2x = 0, the attenuator is increased to the

previously programmed attenuation level at the rate of one 0.5-dB step for every 8/f_Stime interval. This provides

pop-free muting of the DAC output.

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B15 B14 B13 B12 B11 B10

B9

0

B8

1

B7

B6

B5

B4

B3

B2

B1

B0

Register 69

0

1

0

1

FLT

DMF1

DMF0

DMC

RSV

ZREV

AZRO

FLT: Digital Filter Rolloff Control (DAC)

Default value: 0

FLT = 0

FLT = 1

Sharp rolloff (Default)

Slow rolloff

The FLT bit allows the user to select the digital filter roll-off that is best suited to their application. Sharp and Slow

filter roll-off selections are available. The filter responses for these selections are shown in the Typical

Performance Curves section of this data sheet.

DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function (DAC)

Default value: 00

DMF[1:0]

0 0

De-Emphasis Sampling Rate Selection

44.1 kHz (default)

48 kHz

0 1

1 0

32 kHz

1 1

Reserved

The DMF[1:0] bits are used to select the sampling frequency of the digital de-emphasis function when it is

enabled.

DMC: Digital De-Emphasis Function Control (DAC)

Default value: 0

DMC = 0

DMC = 1

De-emphasis disabled (default)

De-emphasis enabled

The DMC bit is used to enable or disable the digital de-emphasis function. See the plots shown in the Typical

Performance Curves section of this data sheet for frequency characteristics.

ZREV: Zero-Flag Polarity Select (DAC)

Default value: 0

ZREV = 0

ZREV = 1

High for zero detect (default)

Low for zero detect

The ZREV bit is used to control the polarity of zero flag pins.

AZRO: Zero-Flag Function Select (DAC)

Default value: 0

AZRO = 0

AZRO = 1

ZEROL: L-ch ZERO detection (default)

ZEROL: L and R ZERO detection

ZEROR: R-ch ZERO detection (default)

ZEROR: L and R ZERO detection

The AZRO bit is used to select the function of zero flag pins.

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B15 B14 B13 B12 B11 B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Register 70

Register 71

0

1

0

1

0

AT117

B7

AT116

B6

AT115

B5

AT114

B4

AT113 AT112 AT111

AT110

B0

B15 B14 B13 B12 B11 B10

B9

B8

B3

B2

B1

0

1

0

1

AT127

AT126

AT125

AT124

AT123 AT122 AT121

AT120

AT1x[7:0]: Digital Attenuation Level Setting (ADC)

where x = 1 or 2, corresponding to the ADC output L-ch part of DOUT (x = 1) or R-ch part of DOUT (x = 2).

Default value: 1101 0111b

AT1x[7:0]

1111 1111b

1111 1110b

1111 1101b

:

DECIMAL VALUE

ATTENUATION LEVEL SETTING

255

254

253

:

20 dB

19.5 dB

19 dB

:

1101 1000b

1101 0111b

1101 0110b

:

216

215

214

:

0.5 dB

0 dB, no attenuation (default)

–0.5 dB

:

0001 0000b

0000 1111b

0000 1110b

:

16

15

14

:

–99.5 dB

–100 dB

Mute

:

0000 0000b

0

Mute

Each ADC channel has a digital attenuator function with 20-dB gain. The attenuation level may be set from 20 dB

to –100 dB in 0.5-dB steps, and also may be set to infinite attenuation (mute). The attenuation level change from

the current value to the target value is performed by incrementing or decrementing one by 0.5-dB step at the

timing of zero-cross detection on the input signal which is sampled for every 1/f_Stime interval, or for every 8/f_S

time interval if the zero-cross detection mode is disabled by ZCDD setting. If a zero-crossing is not detected for

512/f_S, actual level change is done for every 1/f_Stime interval until a zero-crossing is detected again. While the

attenuation level change sequence is in progress, new commands for attenuation level change are not

processed, but the new command overwrites the previous command in the command buffer. The last command

for attenuation level change is performed after the present attenuation level change sequence is finished.

The attenuation level for each channel can be set individually using the following formula, and the above table

shows attenuation levels for various settings:

Attenuation level (dB) = 0.5 × (AT1x[7:0]_DEC– 215), where AT1x[7:0]_DEC= 0 through 255 for AT1x[7:0]_DEC= 0

through 14, the level is set to infinite attenuation (mute).

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B15 B14 B13 B12 B11 B10

B9

0

B8

0

B7

B6

B5

B4

B3

B2

B1

B0

Register 72

0

1

0

1

0

CSEL1 M/S 12

M/S 11

M/S 10

RSV

FMT11 FMT10

CSEL1: Clock Select for ADC Operation

Default value: 0 (SCKI1, BCK1, LRCK1 enabled for ADC operation)

CSEL1 = 0

CSEL1 = 1

SCKI1, BCK1, LRCK1 enabled for ADC operation (default)

SCKI2, BCK2, LRCK2 enabled for ADC operation

The CSEL1 bit controls the system clock and audio interface clocks for the ADC operation.

SCKI1, BCK1, LRCK1 are used for ADC portion if CSEL1 = 0 (default), and SCKI2, BCK2, LRCK2 are used for

ADC portion if CSEL1 = 1.

M/S 1[2:0]: Audio Interface Mode for ADC

Default value: 000 (slave mode)

M/S 1[2:0]

0 0 0

Audio Interface Mode for ADC

Slave mode (default)

Master mode, 768 f_S

Master mode, 512 f_S

Master mode, 384 f_S

Master mode, 256 f_S

Reserved

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

Reserved

1 1 1

Reserved

The M/S 1[2:0] bits control the audio interface mode for the ADC.

FMT1[1:0]: Audio Interface Format for ADC

Default value: 00 (I²S mode)

FMT1[1:0]

0 0

Audio Interface Format for ADC

24-bit I²S format (default)

24-bit left-justified format

0 1

1 0

24-bit right-justified format

16-bit right-justified format

1 1

The FMT1[1:0] bits control the audio interface mode for ADC.

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B15 B14 B13 B12 B11 B10

B9

0

B8

1

B7

B6

B5

B4

B3

B2

B1

B0

Register 73

0

1

0

1

0

RSV

ZCDD

BYP

DREV1 MUT12 MUT11

ZCDD: Zero-Cross Detection Disable for Digital Attenuation (ADC)

Default value: 0

ZCDD = 0

ZCDD = 1

Zero-cross detection enabled (default)

Zero-cross detection disabled

The ZCDD bit controls the zero-cross detect function for digital attenuation and mute. When zero-cross detection

is enabled, the actual level change for digital attenuation and mute is done at the timing of zero-cross detection

on the input signal which is sampled for every 1/f_Stime interval. If zero-crossing is not detected for 512/f_S, the

actual level change is done for every 1/f_Stime interval until a zero-crossing is detected again as timeout control

for no zero-crossing input signal. When zero-cross detection is disabled, the actual level change is done at the

timing of 8/f_Stime interval.

BYP: HPF Bypass Control (ADC)

Default value: 0

BYP = 0

BYP = 1

Normal output, HPF enabled (default)

Bypassed output, HPF disabled

The BYP bit controls the HPF function; the dc component of the input signal and the internal dc offset are

converted in bypass mode.

DREV1: Input Phase Select (ADC)

Default value: 0

DREV1 = 0

DREV1 = 1

Normal input (default)

Inverted input

The DREV1 bit is used to control the phase of analog signal inputs (V_INL and V_INR).

MUT1x: Soft Mute Control (ADC)

where x = 1 or 2, corresponding to the ADC output L-ch part of DOUT (x = 1) and R-ch part of DOUT (x = 2).

Default value: 0

MUT1x = 0

MUT1x = 1

Mute disabled (default)

Mute enabled

The mute bits, MUT11 and MUT12, are used to enable or disable the soft mute function for the corresponding

ADC outputs, DOUT. The soft mute function is incorporated into the digital attenuators. When mute is disabled

(MUT1x = 0), the attenuator and ADC operate normally. When mute is enabled by setting MUT1x = 1, the digital

attenuator for the corresponding output is decreased from the current setting to infinite attenuation in 0.5 dB step

at the timing of zero-cross detection on the input signal which is sampled for every 1/f_Stime interval, or for every

8/f_Stime interval if zero-cross detection mode is disabled by ZCDD setting. If a zero-crossing is not detected for

512/f_S, actual level change is done for every 1/f_Stime interval until zero-crossing is detected again. By setting

MUT1x = 0, the attenuator is increased to the previously programmed attenuation level in 0.5 dB step in the

same manner as for decreasing. This provides pop-free muting for the ADC input.

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TYPICAL CIRCUIT CONNECTION

Figure 33 illustrates typical circuit connection.

Control MCU

1

2

3

4

5

6

7

8

9

MC/FMT/SCL

MODE

28

27

Termination

MD/DEMP/SDA

MS/IFMD/ADR

C5

V_IN

V_CC

R

DOUT

LRCK1

BCK1

SCKI1

V_DD

26

25

24

Analog Input

L

Audio

Receiver

/Encoder

C4

5 V

C1

AGND1 23

AGND2 22

0 V

C2

3.3 V

0 V

V_COM

V_OUTL+

V_OUTL–

V_OUTR+

V_OUTR–

DGND

SCKI2

21

20

19

18

17

C3

Analog Output

Post LPF

and

10 BCK2

11 LRCK2

12 DIN

Audio

Transmitter

/Decoder

Buffer

13 ZEROR

14 ZEROL

SGND 16

RST 15

Note: C1, C2: 0.1-mF ceramic capacitor and 10-mF electrolytic capacitor, depend on power supply.

C3: 0.1-mF ceramic capacitor and 10-mF electrolytic capacitor is recommended.

C4, C5: 4.7-mF electrolytic capacitor is recommended for 3-Hz cutoff frequency.

The termination for mode/configuration control.

Either one of following circuits has to be applied according to necessary mode/configuration.

Resistor value must be 220 kW, ±5 % tolerance.

28

3.3 V

28

0 V

(1)

(2)

(3)

(4)

S0257-01

Figure 33. Typical Application Diagram

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Application Examples for Analog Input and Output

a) Example of V_COM-biased buffering for 2-Vrms input with overvoltage protection.

R2

C2

Example of C, R values with

gain (G) and corner frequency (f_C)

+V

C1

R1

R1: 20 kW

R2: 10 kW

R3: 1 kW

C1: 10 mF

C2: 330 pF

C3: 0.1 mF

G: 0.5

R3

Input

V_IN

X

–V

V_COM

f_C: 48 kHz

C3

b) Example of capless differential to single-ended converter with LPF and gain for 2-Vrms standard output.

R3

Example of C, R values with

gain (G) and corner frequency (f_C)

C2

R1, R2: 10 kW

R3, R4: 7.5 kW

R5, R6: 820 W

R7: 100 W

+V

R1

C1

R2

R5

R6

R7

V_OUTX+

V_OUTX–

Output

–V

C1: 1500 pF

C2, C3: 470 pF

G: 0.75 (Differential to S/E)

f_C: 54 kHz

R4

C3

c) Example of V_COM-biased single-supply single-ended application with LPF and MUTE control for 1-Vrms output.

R2

C2

Example of C, R values with

gain (G) and corner frequency (f_C)

+V

R1

R3

R1: 10 kW

R2: 7.5 kW

R3: 750 W

C1: 3300 pF

C2: 470 pF

C3: 0.1 mF

C4: 10 mF

G: 0.75

C4

V_OUTX+

V_COM

Output

Mute

C1

C3

f_C: 54 kHz

ZEROx

Mute

OR

S0258-01

Figure 34. Application Examples for Analog Input and Output

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DESIGN AND LAYOUT CONSIDERATIONS IN APPLICATION

Power Supply Pins (V_CC, V_DD

)

The digital and analog power supply lines to the PCM3060 should be bypassed to the corresponding ground pins

with 0.1-µF ceramic and 10-µF electrolytic capacitors as close to the pins as possible to maximize the dynamic

performance of the ADC and DAC.

Although the PCM3060 has two power lines to maximize the potential of dynamic performance, using one

common source, 5-V power supply for V_CCand a 3.3-V power supply for V_DDwhich is generated from the 5-V

power supply for V_CC, is recommended to avoid unexpected problems, such as latch-up, from incorrect power

supply sequencing.

Grounding (AGND1, AGND2, SGND, DGND)

To maximize the dynamic performance of the PCM3060, the analog and digital grounds are not connected

internally. These points should have very low impedance to avoid digital noise and signal components feeding

back into the analog ground. So, they should be connected directly to each other under the parts to reduce the

potential of noise problems.

V_INL, V_INR Pins

A 4.7-µF electrolytic capacitor is recommended as the ac coupling capacitor, which gives a 3-Hz cutoff

frequency. If higher full-scale input voltage is required, it can be adjusted by adding only one series resistor to

the V_INX pins, although a small gain error is added due to variations of absolute input resistance of the

PCM3060. For example, adding 9.1 kΩ gives 2 Vrms full-scale with about 10% gain error.

V_COMPin

Ceramic 0.1-µF and electrolytic 10-µF capacitors are recommended between V_COMand AGND to ensure low

source impedance of the ADC and DAC references. These capacitors should be located as close as possible to

the V_COMpins to reduce dynamic errors on ADC and DAC references.

V_OUTL+, V_OUTL–, V_OUTR+, V_OUTR– Pins

The differential to single-ended buffer with post LPF can be directly (without capacitor) connected to these output

pins, thereby minimizing the use of coupling capacitors for the 2-Vrms outputs. The output pins in single-ended

mode are assigned to V_OUTL+ and V_OUTR+ ; in single-ended mode, the V_OUTL– and V_OUTR– pins must be open.

MODE Pin

This pin is a logic input with quad-state input capability.

The pin is connected to V_DDfor High, to DGND for Low, and pulled up or pulled down through an external

resistor and for the two mid-states in order to distinguish the four input states. The pullup or pulldown resistor

must be 220 kΩ, ±5% tolerance.

System Clocks

The quality of SCKI1/2 may influence dynamic performance, as the PCM3060 (both ADC and DAC) operates

based on SCKI1/2. Therefore, it may be required to consider the jitter, duty, rise and fall time, etc. of the system

clocks.

The PCM3060 supports asynchronous operation between the ADC and DAC. Therefore, there is no restriction

on the relationship between SCKI1 and SCKI2 for digital operation, but it is strongly recommended to use a

common clock if the application does not require different base clock frequencies, like 44.1 kHz and 48 kHz.

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Audio Interface Clocks

In slave mode, PCM3060 does not require specific timing relationship between BCK1/LRCK1 and SCKI1,

BCK2/LRCK2 and SCKI2, but there is a possibility of performance degradation with a certain timing relationship

between them. In that case, specific timing-relationship control might solve this performance degradation.

In master mode, there is a possibility of performance degradation due to heavy loads on BCK1/LRCK1,

BCK2/LRCK2 and DOUT. It is recommended to load these pins as lightly as possible.

External Mute Control

For power-down ON/OFF control without the pop noise which is generated by a dc level change on the DAC

output, the external mute control is generally required. Use of the following control sequence is recommended:

external mute ON, codec power down ON, SCKI1/SCKI2 stop and resume if necessary, codec power down OFF,

and external mute OFF.

xxxxxx

REVISION HISTORY

Changes from Original (March 2007) to Revision A ....................................................................................................... Page

•

Changed Figure 34(a), (b), and (c). Updated the Example of C, R values. ........................................................................ 40

Changes from Revision A (February 2008) to Revision B ............................................................................................. Page

•

Changed Supply Current - f_S= 48 kHz/ADC, f_S= 48 kHz/DAC max value From: 30 mA To: 36 mA ................................... 6

Changed Power dissipation - f_S= 48 kHz/ADC, f_S= 48 kHz/DAC max valueFrom: 190 mW To: 220 mW.......................... 6

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IMPORTANT NOTICE AND DISCLAIMER

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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	PCM3060
厂家：	TEXAS INSTRUMENTS
描述：	具有 96/192kHz 采样速率的 24 位异步立体声音频编解码器编解码器
文件：	总50页 (文件大小：721K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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