PCM5242 [TI]
4.2VRMS DirectPath™、32 位、384kHz、114dB 音频立体声 DAC;
| 型号： | PCM5242 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4.2VRMS DirectPath™、32 位、384kHz、114dB 音频立体声 DAC |
| 文件： | 总129页 (文件大小：2695K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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PCM5242
SLASE12A –JULY 2014–REVISED OCTOBER 2014
PCM5242 4.2-V DirectPath™, 114-dB Audio Stereo Differential-Output DAC with 32-bit,
RMS
384-kHz PCM Interface
1 Features
3 Description
The PCM5242 is a monolithic CMOS integrated
circuit that includes
converter and additional support circuitry in a small
QFN package. The PCM5242 uses the latest
1
•
•
•
•
•
•
Differential DirectPath™ Ground Biased Outputs
Market-Leading Low Out-of-Band Noise
Selectable Digital-Filter Latency and Performance
No DC Blocking Capacitors Required
a
stereo digital-to-analog
generation
architecture
of
to
TI’s
advanced
achieve
segment-DAC
dynamic
excellent
Integrated Negative Charge Pump
performance and improved tolerance to clock jitter.
Intelligent Muting System; Soft Up or Down Ramp
and Analog Mute for 120dB Mute SNR
The PCM5242 integrates fully programmable
a
miniDSP core, allowing developers to integrate filters,
dynamic range controls, custom interpolators and
other differentiating features to their products.
•
Integrated High-Performance Audio PLL With
BCK Reference to Generate SCK Internally
•
•
Accepts 16-, 24-, and 32-Bit Audio Data
The PCM5242 provides 4.2VRMS ground-centered
differential outputs, allowing designers to eliminate
DC blocking capacitors on the output, as well as
external muting circuits traditionally associated with
single supply line drivers.
PCM Data Formats: I2S, Left-Justified, Right-
Justified, TDM
•
•
•
SPI or I2C Control
Software or Hardware Configuration
The integrated PLL on the device removes the
requirement for a system clock (commonly known as
master clock), allowing a 3-wire I2S connection and
reducing system EMI.
Automatic Power-Save Mode When LRCK And
BCK Are Deactivated
•
•
1.8V or 3.3V Failsafe LVCMOS Digital Inputs
Single Supply Operation:
Device Information(1)
–
3.3V Analog, 1.8V or 3.3V Digital
PART NAME
PCM5242
PACKAGE
BODY SIZE (NOM)
•
•
Integrated Power-On Reset
VQFN (32)
5.00mm × 5.00mm
Small 32-terminal QFN Package
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
•
•
•
HiFi Smartphone
A/V Receivers
DVD, BD Players
HDTV Receivers
4 Simplified System Diagram
2
DOUT
I
S
2ch Single Ended
BCK
Current Segment DAC
TPA3130
PCM1863/5
miniDSPs,
Filters
LRCK
IN
AUX
2ch Single Ended
PCM5242
TPA6120A2
Analog
Sensor
BT Module
WiLAN chip
MSP430
- Light Intensity
- Ultrasonic
- Battery Level
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCM5242
SLASE12A –JULY 2014–REVISED OCTOBER 2014
www.ti.com
Simplified Block Diagram
Current
Segment
DAC
DIN (I2S)
Digital
Volume
Control
Differential
Line Outputs
DOUT (I2S)
(through
any GPIO)
Current
Segment
DAC
Zero Data
Detector
MOSI/SDA/ATT2
MS/MODE2
MODE1
Advanced Mute Control
SPI/I2C
MC/SCL/ATT1
MISO/ADR1/FMT
Clock Halt
Detection
GPIO6/FLT
GPIO5/ATT0
GPIO4/MAST
GPIO3/AGNS
GPIO2/ADR2/DOUT
GPIO
Program
RAM
PCM5242
LRCK
CPVDD (3.3V)
AVDD (3.3V)
DVDD (1.8V or 3.3V)
GND
Power
Supply
PLL
Clock
BCK
MCK
UVP/
Reset
Charge
Pump
VCom
POR
CAPP
CAPM
VNEG
UVP/XSMT
Typical Performance (3.3V Power Supply)
Parameter
PCM5242
SNR
114dB
Dynamic Range
THD+N at - 1dBFS
Full Scale Differential Output
114dB
–94dB
4.2VRMS (GND center)
Normal 8× Oversampling Digital Filter Latency: 20tS
Low Latency 8× Oversampling Digital Filter Latency: 3.5tS
Sampling Frequency
8kHz to 384kHz
System Clock Multiples (fSCK): 64, 128, 192, 256, 384, 512, 768, 1024,
1152, 1536, 2048, 3072; up to 50 MHz
2
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SLASE12A –JULY 2014–REVISED OCTOBER 2014
Table of Contents
8.6 Audio Processing .................................................... 22
8.7 DAC and Differential Analog Outputs ..................... 44
8.8 Reset and System Clock Functions........................ 47
8.9 Device Functional Modes........................................ 54
Applications and Implementation ...................... 60
9.1 Application Information............................................ 60
9.2 Typical Application .................................................. 60
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Simplified System Diagram .................................. 1
Revision History..................................................... 3
Pin Configuration and Functions......................... 4
6.1 Control Mode Effect On Pin Assignments ................ 4
6.2 Pin Assignments ....................................................... 4
Specifications......................................................... 7
7.1 Absolute Maximum Ratings ...................................... 7
7.2 Handling Ratings....................................................... 7
7.3 Recommended Operating Conditions....................... 7
7.4 Thermal Information.................................................. 7
7.5 Electrical Characteristics........................................... 8
7.6 Switching Characteristics........................................ 11
7.7 Timing Requirements: SCK Input ........................... 11
7.8 Timing Requirements: PCM Audio Data................. 12
7.9 Timing Requirements: XSMT.................................. 13
7.10 Typical Characteristics.......................................... 14
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 16
8.3 Terminology ............................................................ 16
8.4 Audio Data Interface ............................................... 17
8.5 XSMT Pin (Soft Mute / Soft Un-Mute) ................... 21
9
10 Power Supply Recommendations ..................... 62
10.1 Power Supply Distribution and Requirements ...... 62
10.2 Recommended Powerdown Sequence................. 63
7
10.3 External Power Sense Undervoltage Protection
mode (supported only when DVDD = 3.3V) ........... 65
10.4 Power-On Reset Function..................................... 66
10.5 PCM5242 Power Modes ....................................... 68
11 Layout................................................................... 71
11.1 Layout Guidelines ................................................. 71
12 Programming and Registers Reference............ 72
12.1 Coefficient Data Formats ...................................... 72
12.2 Power Down and Reset Behavior......................... 72
12.3 PCM5242 Register Map........................................ 73
13 Device and Documentation Support ............... 120
13.1 Community Resources........................................ 120
13.2 Trademarks......................................................... 120
13.3 Electrostatic Discharge Caution.......................... 120
8
14 Mechanical, Packaging, and Orderable
Information ......................................................... 120
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision Initial (July 2014) to Revision A
Page
•
•
Changed From: A 4-page Product Preview To: A Production datasheet .............................................................................. 1
Changed Description text in the first paragraph From: "The PCM5242 devices are a family.." To: "The PCN5242 is a
monolithic.." ............................................................................................................................................................................ 1
•
Changed Description text in third paragraoh From: "The PCM5242 provides 2.1VRMS.." To: "The PCM5242 provides
4.2VRMS.. ................................................................................................................................................................................. 1
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SLASE12A –JULY 2014–REVISED OCTOBER 2014
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6 Pin Configuration and Functions
6.1 Control Mode Effect On Pin Assignments
The PCM5242 supports control from I2C, SPI and Hardware Modes (referred to as HW mode). Selection of
modes is done using Mode1 and Mode2 pins. (See Table 1)
SPI Mode is selected by pulling MODE1 to DVDD.
I2C Mode is selected by pulling MODE1 to DGND and Mode2 to DVDD.
Hardware Control Mode is selected by pulling both MODE1 and MODE2 pins to DGND.
6.2 Pin Assignments
32-Pin RHB (QFN, Top View)
32 31 30 29 28 27 26 25
32 31 30 29 28 27 26 25
24
32 31 30 29 28 27 26 25
24
XSMT
LDOO
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
MODE2
MODE1
GPO
XSMT
LDOO
1
2
3
4
5
6
7
8
XSMT
LDOO
1
2
3
4
5
6
7
8
MODE2
MODE1
ADR2
MS
23
22
21
20
19
18
17
23
22
21
20
19
18
17
MODE1
GPIO2
GPIO3
GPIO4
DGND
DVDD
DGND
DVDD
DGND
DVDD
AGNS
MAST
GPIO3
GPIO4
GND
GND
GND
CPVDD
CAPP
CPVDD
CAPP
CPVDD
CAPP
ATT0
ATT1
ATT2
GPIO5
SCL
GPIO5
MC
CPGND
CPGND
CPGND
CAPM
CAPM
SDA
CAPM
MOSI
9
10 11 12 13 14 15 16
9
10 11 12 13 14 15 16
9
10 11 12 13 14 15 16
Figure 1. I2C Control
Figure 2. SPI Control
Table 1. PCM5242 Pin Functions
Figure 3. Hardware Control
PIN
MODE, NAME
I/O DESCRIPTION
PIN
I2C
SPI
HW
XSMT
1
2
I
-
Soft mute control(1) Soft mute (Low) / soft un-mute (High)
Internal logic supply rail pin for decoupling, 1.8V
Digital ground
LDOO
DGND
DVDD
CPVDD
CAPP
3
-
4
-
Digital power supply, 3.3V or 1.8V
5
-
Charge pump power supply, 3.3V
6
O
-
Charge pump flying capacitor pin for positive rail
Charge pump ground
CPGND
CAPM
VNEG
OUTLP
OUTLN
OUTRN
OUTRP
AVDD
7
8
O
O
Charge pump flying capacitor pin for negative rail
Negative charge pump rail pin for decoupling, -3.3V
Positive Differential Analog output from DAC left channel
Negative Differential Analog output from DAC left channel
Negative Differential Analog output from DAC right channel
Positive Differential Analog output from DAC right channel.
Analog power supply, 3.3V
9
10
11
12
13
14
15
-
-
AGND
Analog ground
(1) Failsafe LVCMOS Schmitt trigger input.
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SLASE12A –JULY 2014–REVISED OCTOBER 2014
Pin Assignments (continued)
Table 1. PCM5242 Pin Functions (continued)
PIN
MODE, NAME
PIN
I/O DESCRIPTION
I2C
SPI
HW
VCOM output (Optional mode selected by register; default setting is VREF
VCOM
O
I
I2C, SPI mode.) When in VREF mode (default), this pin ties to GND. When in VCOM
16
mode, decoupling capacitor to GND is required.
DEMP
ATT2
HW
DEMP: De-emphasis control for 44.1kHz sampling rate: Off (Low) / On (High)
SDA
SCL
I/O I2C
Data for I2C(2)(1)
MOSI
MC
17
18
SPI
Input data for SPI(1)
I
HW
I2C
Digital gain and attenuation control pin
Input clock for I2C(1)
I
SPI
HW
Input clock for SPI(1)
ATT1
ATT0
Digital gain and attenuation control pin
(3)
GPIO5
I2C, SPI General purpose digital input and output port
HW Digital gain and attenuation control pin
I2C, SPI General purpose digital input and output port
19
20
21
I/O
I/O
I/O
(3)
GPIO4
GPIO3
I2S Master clock select pin : Master (High) BCK/LRCK outputs, Slave (Low)
BCK/LRCK inputs
MAST
AGNS
HW
(3)
I2C, SPI General purpose digital input and output port
HW
I2C
Analog gain selector : 0dB 2VRMS output (Low), -6dB 1VRMS output (High)
2nd LSB address select bit for I2C(3)
ADR2
I/O
O
(3)
GPIO2
MODE1
MS
22
23
SPI
HW
General purpose digital input and output port
GPO
General Purpose Output (Low level)
Mode control selection pin(1)
MODE1 = Low, MODE2 = Low : Hardwired mode
MODE1 = Low, MODE2 = High: I2C mode
MODE1 = High: SPI mode
I
MODE2
MODE2
FLT
I2C, HW MODE2 (See definition in Mode 1 description)
24
25
I
SPI MS pin (chip select for SPI)
GPIO6
I/O I2C, SPI General purpose digital input and output port
I
I
HW
Filter select : Normal latency (Low) / Low latency (High)
SCK
BCK
DIN
26
27
28
29
30
31
System clock input(1)
I/O Audio data bit clock input (slave) or output (master)(1)
I
-
-
Audio data input(1)
NC
No connect
LRCK
I/O Audio data word clock input (slave) or output (master)(1)
ADR1
I2C
I/O SPI
HW
LSB address select bit for I2C
MISO
(GPIO1)
Primary output data for SPI readback. Secondary; general purpose digital
input/output port controlled by register
Audio format selection : I2S (Low) / Left justified (High)
32
FMT
(2) Open-drain configuration in out mode.
(3) Internal Pulldown
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Table 2. Gain and Attenuation in Hardwired Mode
ATT PIN CONDITION
(ATT2 : ATT1 : ATT0)
GAIN AND ATTENUATION LEVEL
( 0 0 0 )
( 0 0 1 )
( 0 1 0 )
( 0 1 1 )
( 1 0 0 )
( 1 0 1 )
( 1 1 0 )
( 1 1 1 )
0 dB
+ 3 dB
+ 6 dB
+ 9 dB
+ 12 dB
+ 15 dB
- 6 dB
- 3 dB
6
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SLASE12A –JULY 2014–REVISED OCTOBER 2014
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
3.9
UNIT
AVDD, CPVDD, DVDD
Supply Voltage
LDOO wtih DVDD at 1.8V
2.25
2.25
3.9
DVDD at 1.8V
Digital Input Voltage
V
DVDD at 3.3V
Analog Input Voltage
3.9
7.2 Handling Ratings
MIN
MAX
UNIT
Tstg
Storage Temperature
–40
125
2500
1500
°C
Human body model (HBM), per
–2500
–1500
ANSI/ESDA/JEDEC JS-001, all pins(1)
Electrostatic
Discharge
V(ESD)
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins
(1) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows
safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN NOM
MAX UNIT
VCOM mode
VREF mode
1.8V DVDD
3.3V DVDD
3.0
3.2
3.3
3.3
1.8
3.3
3.3
3.46
V
Referenced to
AGND(1)
AVDD
DVDD
Analog power supply voltage range
Digital power supply voltage range
3.46
1.65
3.1
1.95
V
Referenced to
DGND(1)
3.46
CPVDD
MCLK
LOL, LOR
CLout
Charge pump supply voltage range
Master Clock Frequency
Referenced to CPGND(1)
3.1
3.46
50
V
MHz
kΩ
Stereo line output load resistance
Digital output load capacitance
Operating Junction Temperature Range
2
10
10
pF
TJ
–25
85
°C
(1) All grounds on board are tied together; they must not differ in voltage by more than 0.2V max, for any combination of ground signals.
7.4 Thermal Information
THERMAL METRIC
RHB (32 PINS)
UNIT
RθJA
Junction-to-ambient thermal resistance
72.2
17.5
35.0
0.4
RθJC(top)
RθJB
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
ψJB
34.5
n/a
RθJC(bottom)
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7.5 Electrical Characteristics
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512fS and 24-bit data unless
otherwise noted.
PARAMETER
Resolution
Digital Input/Output
Logic Family: 3.3V LVCMOS compatible
TEST CONDITIONS
MIN
TYP
MAX
UNIT
16
24
32
Bits
VIH
VIL
IIH
0.7×DVDD
Input logic level
Input logic current
Output logic level
V
µA
V
0.3×DVDD
10
VIN = VDD
VIN = 0V
IIL
–10
VOH
VOL
IOH = –4mA
IOL = 4mA
0.8×DVDD
0.7×DVDD
0.22×DVDD
Logic Family 1.8V LVCMOS compatible
VIH
VIL
IIH
Input logic level
V
µA
V
0.3×DVDD
10
VIN = VDD
Input logic current
Output logic level
IIL
VIN = 0V
–10
VOH
IOH = –2mA
IOL = 2mA
0.8×DVDD
VOL
0.22×DVDD
–87
Dynamic Performance (PCM Mode)(1)(2)
THD+N at -1 dB(2)
fS = 48kHz
–94
–94
–94
114
114
114
114
114
114
123
123
123
fS = 96kHz
fS = 192kHz
Dynamic range(2)
EIAJ, A-weighted, fS = 48kHz
EIAJ, A-weighted, fS = 96kHz
EIAJ, A-weighted, fS = 192kHz
EIAJ, A-weighted, fS = 48kHz
EIAJ, A-weighted, fS = 96kHz
EIAJ, A-weighted, fS = 192kHz
EIAJ, A-weighted, fS = 48kHz
EIAJ, A-weighted, fS = 96kHz
EIAJ, A-weighted, fS = 192kHz
fS = 48kHz
108
dB
Signal-to-noise ratio(2)
Signal to noise ratio with analog
mute(2)(3)
113
113
113
Channel Separation
100 / 95 109 / 103
100 / 95 109 / 103
100 / 95 109 / 103
fS = 96kHz
dB
fS = 192kHz
(1) Filter condition: THD+N: 20Hz HPF, 20kHz AES17 LPF Dynamic range: 20Hz HPF, 20kHz AES17 LPF, A-weighted Signal-to-noise
ratio: 20Hz HPF, 20kHz AES17 LPF, A-weighted Channel separation: 20Hz HPF, 20kHz AES17 LPF Analog performance specifications
are measured using the System Two Cascade™ audio measurement system by Audio Precision™ in the RMS mode.
(2) Output load is 10kΩ, with 470Ω output resistor and a 2.2nF shunt capacitor (see recommended output filter).
(3) Assert XSMT or both L-ch and R-ch PCM data are BPZ
8
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Electrical Characteristics (continued)
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512fS and 24-bit data unless
otherwise noted.
PARAMETER
Analog Output
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Single Ended Output voltage
Differential Output Voltage
Gain error
2.1
4.2
VRMS
VRMS
–6
–6
±2.0
±0.5
6
6
% of FSR
Gain mismatch, channel-to-
channel
% of FSR
Bipolar zero error
Load impedance
At bipolar zero
–2
5
±1.0
2
0.45fS
±0.02
mV
kΩ
Filter Characteristics–1: Normal (8x)
Pass band
kHz
Stop band
0.55fS
–60
Stop band attenuation
Pass-band ripple
dB
s
Delay time
20tS
3.5tS
1.2tS
Filter Characteristics–2: Low Latency (8x)
Pass band
0.47fS
±0.0001
0.40fS
±0.05
kHz
Stop band
0.55fS
–52
Stop band attenuation
Pass-band ripple
dB
s
Delay time
Filter Characteristics–3: Asymmetric FIR (8x)
Pass band
Stop band
kHz
0.72fS
–52
Stop band attenuation
Pass-band ripple
Delay time
dB
s
Filter Characteristics–4: High-Attenuation (8x)
Pass band
0.45fS
±0.0005
kHz
Stop band
0.45fS
Stop band attenuation
Pass-band ripple
Delay time
–100
dB
s
33.7tS
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Electrical Characteristics (continued)
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512fS and 24-bit data unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply Requirements
DVDD
DVDD
AVDD
Digital supply voltage
Digital supply voltage
Analog supply voltage
Target DVDD = 1.8V
1.65
3.0
1.8
3.3
3.3
3.3
11
1.95
3.6
3.6
3.6
14
VDC
VDC
VDC
VDC
Target DVDD = 3.3V
3.0
CPVDD Charge-pump supply voltage
3.0
fS = 48kHz, Input is Bipolar Zero data
fS = 96kHz, Input is Bipolar Zero data
fS = 192kHz, Input is Bipolar Zero data
fS = 48kHz, Input is 1kHz -1dBFS data
fS = 96kHz, Input is 1kHz -1dBFS data
fS = 192kHz, Input is 1kHz -1dBFS data
fS = N/A, Power Down Mode
IDD
DVDD supply current at 1.8V
12
mA
14
11
14
IDD
IDD
IDD
DVDD supply current at 1.8V
DVDD supply current at 1.8V(4)
DVDD supply current at 3.3V
12
mA
mA
mA
14
0.3
12
0.6
15
fS = 48kHz, Input is Bipolar Zero data
fS = 96kHz, Input is Bipolar Zero data
fS = 192kHz, Input is Bipolar Zero data
fS = 48kHz, Input is 1kHz -1dBFS data
fS = 96kHz, Input is 1kHz -1dBFS data
fS = 192kHz, Input is 1kHz -1dBFS data
fS = N/A, Power Down Mode
13
15
12
15
IDD
IDD
ICC
DVDD supply current at 3.3V
DVDD supply current at 3.3V(4)
AVDD + CPVDD Supply Current
13
mA
mA
mA
15
0.5
11
0.8
16
fS = 48kHz, Input is Bipolar Zero data
fS = 96kHz, Input is Bipolar Zero data
fS = 192kHz, Input is Bipolar Zero data
fS = 48kHz, Input is 1kHz -1dBFS data
fS = 96kHz, Input is 1kHz -1dBFS data
fS = 192kHz, Input is 1kHz -1dBFS data
fS = N/A, Power Down Mode
11
11
24
32
ICC
AVDD + CPVDD Supply Current
AVDD + CPVDD Supply Current(4)
Power Dissipation, DVDD = 1.8V
24
mA
mA
mW
24
ICC
0.2
59.4
61.2
64.8
99
0.4
78
fS = 48kHz, Input is Bipolar Zero data
fS = 96kHz, Input is Bipolar Zero data
fS = 192kHz, Input is Bipolar Zero data
fS = 48kHz, Input is 1kHz -1dBFS data
fS = 96kHz, Input is 1kHz -1dBFS data
fS = 192kHz, Input is 1kHz -1dBFS data
130.8
Power Dissipation, DVDD = 1.8V
100.8
104.4
1.2
79.2
82.5
89.1
118.8
122.1
128.7
2.3
mW
mW
mW
Power Dissipation, DVDD = 1.8V(4) fS = N/A, Power Down Mode
fS = 48kHz, Input is Bipolar Zero data
103
155
4.0
Power Dissipation, DVDD = 3.3V
Power Dissipation, DVDD = 3.3V
fS = 96kHz, Input is Bipolar Zero data
fS = 192kHz, Input is Bipolar Zero data
fS = 48kHz, Input is 1kHz -1dBFS data
fS = 96kHz, Input is 1kHz -1dBFS data
fS = 192kHz, Input is 1kHz -1dBFS data
mW
mW
Power Dissipation, DVDD = 3.3V(4) fS = N/A, Power Down Mode
(4) Power Down Mode, with LRCK, BCK, and SCK halted at Low level.
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7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Data Format (PCM Mode)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio data interface format
Audio data bit length
Audio data format
I2S, left justified, right justified and TDM
16, 20, 24, 32-bit acceptable
MSB First, 2s Complement
(1)
fS
Clocks
Sampling frequency
8
384
kHz
System clock frequency
64, 128, 192, 256, 384, 512, 768, 1024, 1152,
1536, 2048, or 3072
fSCK, up to 50Mhz
Clock divider uses fractional divide
D > 0, P=1
6.7
1
20
20
MHz
MHz
(2)
PLL Input Frequency
Clock divider uses integer divide
D = 0, P=1
(1) One sample time si defined as the reciprocal of the sampling frequency. 1tS = 1/fS
(2) With the appropriate P coefficient setting, the PLL accepts up to 50MHz. This clock is then divided to meet the ≤ 20MHz requirement.
See PLL Calculation.
7.7 Timing Requirements: SCK Input
Figure 4 shows the timing requirements for the system clock input. For optimal performance, use a clock source
with low phase jitter and noise.
MIN
20
8
TYP
MAX
UNIT
tSCY
System clock pulse cycle time
System clock pulse width, High
1000
ns
DVDD = 1.8V
DVDD = 3.3V
DVDD = 1.8V
DVDD = 3.3V
tSCKH
ns
ns
9
8
tSCKL
System clock pulse width, Low
9
tSCKH
"H"
0.7*DVDD
0.3*DVDD
System Clock
(SCK)
"L"
tSCKL
tSCY
Figure 4. Timing Requirements for SCK Input
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7.8 Timing Requirements: PCM Audio Data
MIN
40
16
16
8
TYP
MAX
UNIT
ns
tBCY
tBCL
tBCH
tBL
BCK Pulse Cycle Time
BCK Pulse Width LOW
ns
BCK Pulse Width HIGH
ns
BCK Rising Edge to LRCK Edge
BCK frequency at DVDD = 3.3V
BCK frequency at DVDD = 1.8V
LRCK Edge to BCK Rising Edge
DATA Set Up Time
ns
tBCK
tBCK(1.8V)
tLB
24.576
12.288
MHz
MHz
ns
8
8
8
tDS
ns
tDH
DATA Hold Time
ns
tDOD
DATA delay time from BCK falling edge
15
ns
LRCK
0.5 * DVDD
(Input)
tLB
tBCH
tBCL
BCK
0.5 * DVDD
0.5 * DVDD
0.5 * DVDD
(Input)
tBCY
tBL
DATA
(Input)
tDS
tDH
tDOD
DATA
(Output)
Figure 5. PCM5242 Serial Audio Timing - Slave
In software mode, the PCM5242 can act as an I2S master, generating BCK and LRCK as outputs from the SCK
input.
Table 3. I2S Master Mode Registers
Register
Function
Page0, Register 9, D(0), D(4), and D(5)
Register 32, D(6:0)
I2S Master mode select
BCK divider and LRCK divider
Register 33, D(7:0)
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The I2S master timing is shown in Figure 6.
MIN
40
TYP
MAX
UNIT
ns
tBCY
BCK Pulse Cycle Time
tBCL
BCK Pulse Width LOW
16
ns
tBCH
BCK Pulse Width HIGH
16
ns
tBCK
BCK frequency at DVDD = 3.3V
BCK frequency at DVDD = 1.8V
LRCKx delay time from BCKx falling edge
DATA Set Up Time
24.576
12.288
20
MHz
MHz
ns
tBCK(1.8V)
tLRD
–10
8
tDS
ns
tDH
DATA Hold Time
8
ns
tDOD
DATA delay time from BCK falling edge at DVDD = 3.3V
DATA delay time from BCK falling edge at DVDD = 1.8V
15
20
ns
tDOD(1.8V)
ns
tBCH
tBCL
BCK
0. 5 * DVDD
0. 5 * DVDD
(Output)
tLRD
tBCY
LRCK
(Output)
tDOD
DATA
0. 5 * DVDD
(Output)
tDS
tDH
DATA
(Input)
0. 5 * DVDD
Figure 6. PCM5242 Serial Audio Timing - Master
7.9 Timing Requirements: XSMT
MIN
TYP
MAX
20
UNIT
ns
tr
tf
Rise time
Fall time
20
ns
0.9 * DVDD
0.1 * DVDD
XSMT
tr
tf
<20ns
<20ns
Figure 7. XSMT Timing for Soft Mute and Soft Un-Mute
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7.10 Typical Characteristics
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless
otherwise noted.
10
10
-10
-10
-30
-30
-50
-50
-70
-70
-90
-90
-110
-110
-100
-80
-60
-40
-20
0
-100
-80
-60
-40
-20
0
Input Level (dBFS)
Input Level (dBFS)
Figure 8. 1 THD+N versus Input Level
Figure 9. 2 THD+N versus Input Level
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
5
10
Frequency (kHz)
15
20
0
5
10
Frequency (kHz)
15
20
Figure 11. 2 FFT Plot At -60db Input
Figure 10. 1 FFT Plot At -60db Input
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
5
10
15
20
0
5
10
Frequency (kHz)
15
20
Frequency (kHz)
Figure 13. 2 FFT Plot at BPZ
Figure 12. 1 FFT Plot At Bipolar Zero Data (BPZ)
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Typical Characteristics (continued)
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless
otherwise noted.
-20
-40
-60
-80
-100
-120
-140
-160
-180
0
5
10
Frequency (kHz)
15
20
Frequency (kHz)
Figure 15. 2 FFT Plot at BPZ With Amute
Figure 14. 1 FFT Plot at BPZ With Analog Mute (Amute)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-100
-120
-140
-160
-120
-140
-160
0
50
100
150
Frequency (kHz)
200
250
300
0
50
100
150
200
250
300
Frequency (kHz)
Figure 17. 2 FFT Plot at -60dB to 300khz
Figure 16. 1 FFT Plot at -60dB to 300khz
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8 Detailed Description
8.1 Overview
The integrated PLL on the device provided adds the flexibility to remove the system clock (commonly known as
master clock), allowing a 3-wire I2S connection and reducing system EMI. In addition, the PLL is completely
programmable, allowing the device to become the I2S clock master and drive a DSP serial port as a slave. The
PLL also accepts a non-standard clock (up to 50MHz) as a source to generate the audio related clock (for
example 24.576MHz).
Powersense undervoltage protection utilizes a two-level mute system. Upon clock error or system power failure,
the device digitally attenuates the data (or last known good data), then mutes the analog circuit.
Compared with existing DAC technology, the PCM5242 offers up to 20dB lower out-of-band noise, reducing EMI
and aliasing in downstream amplifiers/ADCs. (from traditional 100kHz OBN measurements all the way to 3MHz).
The PCM5242 accepts industry-standard audio data formats with 16- to 32-bit data. Sample rates up to 384kHz
are supported.
8.2 Functional Block Diagram
Current
Segment
DAC
DIN (I2S)
Digital
Volume
Control
Differential
Line Outputs
DOUT (I2S)
(through
any GPIO)
Current
Segment
DAC
Zero Data
Detector
MOSI/SDA/ATT2
MS/MODE2
MODE1
Advanced Mute Control
SPI/I2C
MC/SCL/ATT1
MISO/ADR1/FMT
Clock Halt
Detection
GPIO6/FLT
GPIO5/ATT0
GPIO4/MAST
GPIO3/AGNS
GPIO2/ADR2/DOUT
GPIO
Program
RAM
PCM5242
LRCK
BCK
CPVDD (3.3V)
AVDD (3.3V)
DVDD (1.8V or 3.3V)
GND
Power
Supply
PLL
Clock
UVP/
Reset
Charge
MCK
VCom
Pump
POR
CAPP
CAPM
VNEG
UVP/XSMT
8.3 Terminology
Control registers in this datasheet are given by REGISTER BIT/BYTE NAME (Page.x HEX ADDRESS). SE
refers to "Single Ended" analog inputs, DIFF refers to "Differential" analog inputs. SCK (System Clock) and
MCLK (Master Clock) are used interchangeably. Sampling frequency is symbolized by "fS". Full scale is
symbolized by "FS". Sample time as a unit is symbolized by "tS".
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8.4 Audio Data Interface
8.4.1 Audio Serial Interface
The audio interface port is a 3-wire serial port with the signals LRCK, BCK, and DIN. BCK is the serial audio bit
clock, used to clock the serial data present on DIN into the serial shift register of the audio interface. Serial data
is clocked into the PCM5242 on the rising edge of BCK. LRCK is the serial audio left/right word clock. LRCK
polarity for Left/Right is given by the format selected.
Table 4. PCM5242 Audio Data Formats, Bit Depths and Clock Rates
MAX LRCK
CONTROL MODE
FORMAT
DATA BITS
SCK RATE [x fS]
BCK RATE [x fS]
FREQUENCY [fS]
Up to 192kHz
384kHz
128 – 3072
64, 128
64, 48, 32
64, 48, 32
125, 256
125, 256
128
I2S/LJ
32, 24, 20, 16
Software Control
(SPI or I2S)
Up to 48kHz
96kHz
128 – 3072
128 – 512
128, 192, 256
128 – 3072
64, 128
TDM/DSP
I2S/LJ
32, 24, 20, 16
32, 24, 20, 16
192kHz
Up to 192kHz
384kHz
64, 48, 32
64, 48, 32
Hardware Control
The PCM5242 requires the synchronization of LRCK and system clock, but does not need a specific phase
relation between LRCK and system clock.
If the relationship between LRCK and system clock changes more than ±5 SCK, internal operation is initialized
within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between
LRCK and system clock is completed.
If the relationship between LRCK and BCK are invalid more than 4 LRCK periods, internal operation is initialized
within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between
LRCK and BCK is completed.
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8.4.2 PCM Audio Data Formats
The PCM5242 supports industry-standard audio data formats, including standard I2S and left-justified. Data
formats are selected via Register (Pg0Reg40). All formats require binary 2s-complement, MSB-first audio data;
up to 32-bit audio data is accepted.
The PCM5242 also supports right-justified and TDM/DSP in software control mode. I2S, LJ, RJ, and TDM/DSP
are selected using Register (Pg0Reg40). All formats require binary 2s complement, MSB-first audio data. Up to
32 bits are accepted. Default setting is I2S and 24 bit word length.
1tS
R-channel
L-channel
LRCK
BCK
Audio data word = 16-bit, BCK = 32, 48, 64fS
1
2
15 16
1
1
1
2
15 16
DATA
MSB
LSB
MSB
LSB
Audio data word = 24-bit, BCK = 48, 64fS
-
,
2
1
2
24
2
23 24
DATA
MSB
LSB
MSB
LSB
Audio data word = 32-bit, BCK = 64fS
1
2
31 32
2
31 32
DATA
MSB
LSB
MSB
LSB
Figure 18. Left Justified Audio Data Format
1tS
LRCK
BCK
L-channel
R-channel
Audio data word = 16-bit, BCK = 32, 48, 64fS
1
2
15 16
1
2
15 16
DATA
MSB
LSB
MSB
LSB
Audio data word = 24-bit, BCK = 48, 64fS
2
1
2
23 24
1
23 24
DATA
MSB
LSB
MSB
LSB
Audio data word = 32-bit, BCK = 64fS
1
2
31 32
1
2
31 32
DATA
MSB
LSB
MSB
LSB
I2S Data Format; L-channel = LOW, R-channel = HIGH
Figure 19. I2S Audio Data Format
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The following data formats are only available in software mode.
Right Justified Data Format; L-channel = HIGH, R-channel = LOW
Figure 20. Right Justified Audio Data Format
TDM/DSP Data Format; L-channel = FIRST, R-channel = LAST with OFFSET = 0
Figure 21. TDM/DSP 1 Audio Data Format
NOTE
In TDM Modes, Duty Cycle of LRCK should be 1x BCK at minimum. Rising edge is
considered frame start.
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TDM/DSP Data Format; L-channel = FIRST, R-channel = LAST with OFFSET = 1
Figure 22. TDM/DSP 2 Audio Data Format
TDM/DSP Data Format; L-channel = FIRST, R-channel = LAST with OFFSET = N
Figure 23. TDM/DSP 3 Audio Data Format
8.4.3 Zero Data Detect
The PCM5242 has a zero-detect function. When the device detects the continuous zero data for both left and
right channels, or separate channels, Analog mutes are set to both OUTL and OUTR, or separate OUTL and
OUTR. These are controlled by Page0, Register 65, D(2:1) as shown in Table 5.
Continuous Zero data cycles are counted by LRCK, and the threshold of decision for analog mute can be set by
Page 0, Register 59, D(6:4) for L-ch, and D(2:0) for Rch as shown in Table 6. Default values are 0 for both
channels.
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In Hardware mode, the device uses default values.
Table 5. Zero Data Detection Mode
ATMUTECTL
Value
Function
Independently L-ch or R-ch are zero data for zero data
detection
0
Bit : 2
Both L-ch and R-ch have to be zero data for zero data
detection
1 (Default)
0
Zero detection and analog mute are disabled for R-ch
Zero detection analog mute are enabled for R-ch
Zero detection analog mute are disabled for L-ch
Zero detection analog mute are enabled for L-ch
Bit : 1
Bit : 0
1 (Default)
0
1 (Default)
Table 6. Zero Data Detection Time
ATMUTETIML /
ATMUTETIMR
Number of LRCKs
Time @ 48kHz
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1024
5120
21 ms
106 ms
10240
25600
51200
102400
256000
512000
213 ms
533 ms
1.066 sec
2.133 sec
5.333 sec
10.66 sec
8.5 XSMT Pin (Soft Mute / Soft Un-Mute)
An external digital host controls the PCM5242 soft mute function by driving the XSMT pin with a specific
minimum rise time (tr) and fall time (tf) for soft mute and soft un-mute. The PCM5242 requires tr and tf times of
less than 20ns. In the majority of applications, this is no problem, however, traces with high capacitance may
have issues.
When the XSMT pin is shifted from high to low (3.3V to 0V), a soft digital attenuation ramp begins. -1dB
attenuation is then applied every sample time from 0dBFS to - ∞. The soft attenuation ramp takes 104 samples.
When the XSMT pin is shifted from low to high (0V to 3.3V), a soft digital “un-mute” is started. 1dB gain steps are
applied every sample time from - ∞ to 0dBFS. The un-mute takes 104 samples.
In systems where XSMT is not required, it can be directly connected to AVDD.
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8.6 Audio Processing
8.6.1 PCM5242 Audio Processing Options
8.6.1.1 Overview
The PCM5242 features a fully-programmable miniDSP core. The algorithms for the miniDSP must be loaded into
the device after power up. The miniDSP has direct access to the digital stereo audio stream, offering the
possibility for advanced DSP algorithms with very low group delay. The miniDSP can run up to 1024 instructions
on every audio sample at a 48kHz sample rate.
The PCM5242 features a programmable miniDSP core that offers Hybrid-Flows which are a RAM/ROM
combination of code. Common functions are embedded in ROM, and custom RAM flows, created by TI can be
run on the miniDSP core. The algorithms for the miniDSP must be loaded into the device after power up. The
miniDSP can run up to 1024 instructions on every audio sample at a 48kHz sample rate. Development is done
using Purepath Console software.
NOTE
At higher sampling frequencies, fewer instruction cycles are available. (For example, 512
instructions can be done in a 96kHz frame.)
The PCM5242 supports two different code sources. ROM based process flow (See the next section for how to
select) and RAM based process flow. In program 31 (RAM based), different algorithms can be called from ROM -
such as EQ, DRC and Zero Crossing volume control. Please see the PurePath Studio Development Environment
for more details.
8.6.1.2 miniDSP Instruction Register
Registers on Page 152-169 are 25-bit instructions for the miniDSP engine. For details see Table 49. 7 bits of
Instr(32:25) in Base register +0 are reserved bits. 1 bit of Instr(24) - (LSB) in Base register +0 is MSB bit of 25 bit
instruction. These instructions control miniDSP operation. When the fully programmable miniDSP mode is
enabled and the DAC channel is powered up, the read and write access to these registers is disabled.
8.6.1.3 Digital Output
The PCM5242 supports an SDOUT output. This can be selected within the process flow, and driven out of a
GPIO pin selected in the register map (e.g. Page 0 / Register 80). Users should note that the I2S output will be
attenuated by 0.5dB. A full scale (FS) output will actually be FS-0.5dB. This can be compensated for within the
process flow using PurePath Studio. The I2S output can be a separate audio stream to the analog DAC output,
allowing 2.1 and 2.2 systems to be implimented. By default, the SDOUT is not linked to the volume control
registers on Page 0 / Register 60, 61, 62. However, it is possible to configure the SDOUT component in
Purepath studio to mirror that register.
8.6.1.4 Software
Software development for the PCM5242 is supported through TI's comprehensive PurePath Console; a powerful,
easy-to-use tool designed specifically to simplify software development on the PCM5242 miniDSP audio
platform. The Graphical Development Environment consists of number of Hybrid Flows that can be downloaded
to the device and run on the miniDSP.
Please visit the PCM5242 product folder on www.ti.com to learn more about PurePath Console and the latest
status on available, ready-to-use DSP algorithms.
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Audio Processing (continued)
8.6.2 Interpolation Filter
The PCM5242 provides 4 types of interpolation filters, selectable by writing to Page 0, Register 43, D(4:0).
Additional RAM based Hybrid Flows can be implemented by selecting Program 31, and downloading instructions
and coefficients to the device.
Table 7. ROM Preset Programs
Program number
D(4:0)
0 0000
0 0001
0 0010
0 0011
0 0100
0 0101
0 0110
0 0111
:
Description
Minimum Cycles
0
1
Reserved
Normal x8/x4/x2/x1 Interpolation Filter(1)
Low Latency x8/x4/x2/x1 Interpolation Filter(1)
High Attenuation x8/x4/x2 Interpolation Filter(1)
Reserved
256
256
512
2
3
4
5
Preset Process Flow
n/a
6
Reserved
Asymmetric FIR Interpolation Filter(1)
7
512
:
Reserved
31
1 1111
RAM program / Hybrid Flows
(1) fS 44.1kHz De-emphasis filter is supported.
The PCM5242supports four sampling modes (single rate, dual rate, quad rate, and octal rate) which produce
different oversampling rates (OSR) in the interpolation digital filter operation. These are shown in Table 8.
Table 8. Sampling Modes and Oversampling Rates
Sampling Mode
Sampling Frequency (fS) kHz
Oversampling Rate (OSR)
8
16
Single Rate
32
8 or 16
44.1
48
88.2
96
Dual Rate
4
176.4
192
384
Quad Rate
Octal Rate
2
1 (Bypass)
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Table 9. Normal x8 Interpolation Filter, Single Rate
Parameter
Condition
Value (Typical)
Value (Max)
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 ……. 0.45fS
0.55fS ….. 7.455fS
±0.01
–60
dB
20tS
S
0
−20
1.0
0.8
0.6
−40
0.4
−60
0.2
−80
0.0
−100
−120
−0.2
−0.4
0
1
2
3
4
0
50
100
150
200
Samples
250
300
350
400
Frequency (x fS)
G012
G023
Figure 24. Normal x8 Interpolation Filter Frequency
Response
0.05
Figure 25. Normal x8 Interpolation Filter Impulse
Response
0.04
0.03
0.02
0.01
0.00
−0.01
−0.02
−0.03
−0.04
−0.05
0.0
0.1
0.2
0.3
0.4
0.5
Frequency (x fS)
G034
Figure 26. Normal x8 Interpolation Filter Passband Ripple
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Table 10. Normal x4 Interpolation Filter, Dual Rate
Parameter
Condition
Value (Typical)
Value (Max)
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 ……. 0.45fS
0.55fS ….. 3.455fS
±0.01
–60
dB
20tS
S
1.0
0.8
0
−20
0.6
−40
0.4
−60
0.2
−80
0.0
−100
−120
−0.2
−0.4
0
20
40
60
80
Samples
100
120
140
160
0
1
2
Frequency (x fS)
G020
G009
Figure 27. Normal x4 Interpolation Filter Frequency
Response
0.05
Figure 28. Normal x4 Interpolation Filter Impulse
Response
0.04
0.03
0.02
0.01
0.00
−0.01
−0.02
−0.03
−0.04
−0.05
0.0
0.25
Frequency (x fS)
0.5
G031
Figure 29. Normal x4 Interpolation Filter Passband Ripple
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Table 11. Normal x2 Interpolation Filter, Quad Rate
Parameter
Condition
Value (Typical)
Value (Max)
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 ……. 0.45fS
0.55fS ….. 1.455fS
±0.01
–60
dB
20tS
S
1.0
0.8
0
−20
0.6
−40
0.4
−60
0.2
−80
0.0
−100
−120
−0.2
−0.4
0
10
20
30
40
50
Samples
60
70
80
90 100
0
0.5
1
Frequency (x fS)
G017
G006
Figure 30. Normal x2 Interpolation Filter Frequency
Response
0.05
Figure 31. Normal x2 Interpolation Filter Impulse
Response
0.04
0.03
0.02
0.01
0.00
−0.01
−0.02
−0.03
−0.04
−0.05
0.0
0.25
Frequency (x fS)
0.5
G028
Figure 32. Normal x2 Interpolation Filter Passband Ripple
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Table 12. Low latency x8 Interpolation Filter, Single Rate
Parameter
Condition
Value (Typical)
Value (Max)
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 ……. 0.45fS
0.55fS ….. 7.455fS
±0.001
–52
dB
3.5tS
S
0
−20
1.0
0.8
0.6
−40
0.4
−60
0.2
0.0
−80
−0.2
−0.4
−0.6
−100
−120
0
1
2
3
4
0
50
100
150
200
Samples
250
300
350
400
Frequency (x fS)
G011
G022
Figure 33. Low latency x8 Interpolation Filter
Frequency Response
Figure 34. Low latency x8 Interpolation Filter
Impulse Response
0.00010
0.00008
0.00006
0.00004
0.00002
0.00000
−0.00002
−0.00004
−0.00006
−0.00008
−0.00010
0.0
0.1
0.2
0.3
0.4
0.5
Frequency (x fS)
G033
Figure 35. Low latency x8 Interpolation Filter Passband Ripple
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Table 13. Low latency x4 Interpolation Filter, Dual Rate
Parameter
Condition
Value (Typical)
Value (Max)
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 ……. 0.45fS
0.55fS ….. 3.455fS
±0.001
–52
dB
3.5tS
S
1.0
0
−20
0.8
0.6
−40
0.4
0.2
−60
0.0
−80
−0.2
−0.4
−0.6
−100
−120
0
20
40
60
80
Samples
100 120 140 160 180
0
1
2
Frequency (x fS)
G019
G008
Figure 36. Low latency x4 Interpolation Filter
Figure 37. Low latency x4 Interpolation Filter
Impulse Response
Frequency Response
0.0001
0.00008
0.00006
0.00004
0.00002
0
−0.00002
−0.00004
−0.00006
−0.00008
−0.0001
0.0
0.25
Frequency (x fS)
0.5
G030
Figure 38. Low latency x4 Interpolation Filter Passband Ripple
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Table 14. Low latency ×2 Interpolation Filter, Quad Rate
Parameter
Condition
Value (Typical)
Value (Max)
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 ……. 0.45fS
0.55fS ….. 1.455fS
±0.001
–52
dB
3.5tS
S
1.0
0.8
0
−20
0.6
−40
0.4
−60
0.2
−80
0.0
−100
−120
−0.2
−0.4
0
10
20
30
40
50
Samples
60
70
80
90 100
0
0.5
1
Frequency (x fS)
G016
G005
Figure 39. Low latency x2 Interpolation Filter
Figure 40. Low latency x2 Interpolation Filter
Impulse Response
Frequency Response
0.0001
0.00008
0.00006
0.00004
0.00002
0
−0.00002
−0.00004
−0.00006
−0.00008
−0.0001
0.0
0.25
Frequency (x fS)
0.5
G030
Figure 41. Low latency x2 Interpolation Filter Passband Ripple
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Table 15. Asymmetric FIR x8 Interpolation Filter, Single Rate
Parameter
Condition
Value (Typical)
Value (Max)
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 ……. 0.40fS
0.72fS ….. 7.28fS
±0.05
–50
dB
1.2tS
S
0
−20
1
0.8
0.6
0.4
0.2
0
−40
−60
−80
−100
−120
−0.2
−0.4
0
0
1
2
3
4
10
20
30
40
50
60
70
80
Samples
Frequency ( × fS)
G003
G006
Figure 42. Asymmetric FIR x8 Interpolation Filter
Frequency Response, Single Rate
Figure 43. Asymmetric FIR x8 Interpolation Filter
Impulse Response, Single Rate
0.2
0.15
0.1
0.05
0
−0.05
−0.1
−0.15
−0.2
0
0.1
0.2
0.3
0.4
0.5
Frequency ( × fS)
G009
Figure 44. Asymmetric FIR x8 Interpolation Filter Passband Ripple, Single Rate
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Table 16. Asymmetric FIR x4 Interpolation Filter, Dual Rate
Parameter
Condition
Value (Typical)
Value (Max)
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 ……. 0.40fS
0.72fS ….. 3.28fS
±0.05
–50
dB
1.2tS
S
0
−20
1
0.8
0.6
0.4
0.2
0
−40
−60
−80
−100
−120
−0.2
−0.4
0
0
1
2
10
20
30
Samples
40
50
60
Frequency (x fS)
G002
G005
Figure 45. Asymmetric FIR x4 Interpolation Filter
Frequency Response, Dual Rate
Figure 46. Asymmetric FIR x4 Interpolation Filter
Impulse Response, Dual Rate
0.2
0.15
0.1
0.05
0
−0.05
−0.1
−0.15
−0.2
0
0.5
1
Frequency ( × fS)
G008
Figure 47. Asymmetric x4 Interpolation Filter Passband Ripple, Dual Rate
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Table 17. Asymmetric FIR x2 Interpolation Filter, Quad Rate
Parameter
Condition
Value (Typical)
Value (Max)
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 ……. 0.40fS
0.72fS ….. 1.28fS
±0.05
–50
dB
1.2tS
S
0
−20
1
0.8
0.6
0.4
0.2
0
−40
−60
−80
−100
−120
−0.2
−0.4
0
0
0.5
1
10
20
30
40
50
Samples
Frequency (x fS)
G001
G004
Figure 48. Asymmetric FIR x2 Interpolation Filter
Frequency Response, Quad Rate
Figure 49. Asymmetric FIR x2 Interpolation Filter
Impulse Response, Quad Rate
0.2
0.15
0.1
0.05
0
−0.05
−0.1
−0.15
−0.2
0
0.25
Frequency (x fS)
0.5
G100
Figure 50. Asymmetric x2 Interpolation Filter Passband Ripple, Quad Rate
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Table 18. High-Attentuation x8 Interpolation Filter, Single Rate
Parameter
Condition
Value (Typical)
Value (Max)
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 ……. 0.45fS
0.55fS ….. 7.455fS
±0.0005
–100
dB
33.7tS
S
0
−20
1
0.8
0.6
0.4
0.2
0
−40
−60
−80
−100
−120
−0.2
−0.4
0
1
2
3
4
0
50 100 150 200 250 300 350 400 450 500 550 600
Samples
Frequency ( × fS)
G003
G006
Figure 51. High-Attentuation x8 Interpolation Filter Figure 52. High-Attentuation x8 Interpolation Filter
Frequency Response, Single Rate
Impulse Response, Single Rate
0.002
0.0015
0.001
0.0005
0
−0.0005
−0.001
−0.0015
−0.002
0
0.1
0.2
0.3
0.4
0.5
Frequency ( × fS)
G009
Figure 53. High-Attentuation x8 Interpolation Filter Passband Ripple, Single Rate
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Table 19. High-Attentuation x4 Interpolation Filter, Dual Rate
Parameter
Condition
Value (Typical)
Value (Max)
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 ……. 0.45fS
0.55fS ….. 3.455fS
±0.0005
–100
dB
33.7tS
S
0
−20
1
0.8
0.6
0.4
0.2
0
−40
−60
−80
−100
−120
−0.2
−0.4
0
0
1
2
50
100
150
Samples
200
250
300
Frequency (x fS)
G004
G005
Figure 54. High-Attentuation x4 Interpolation Filter Figure 55. High-Attentuation x4 Interpolation Filter
Frequency Response, Dual Rate
0.002
Impulse Response, Dual Rate
0.0015
0.001
0.0005
0
−0.0005
−0.001
−0.0015
−0.002
0
0.25
0.5
Frequency (x fS)
G101
Figure 56. High-Attentuation x4 Interpolation Filter Passband Ripple, Dual Rate
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Table 20. High-Attentuation x2 Interpolation Filter, Quad Rate
Parameter
Condition
Value (Typical)
Value (Max)
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 ……. 0.45fS
0.55fS ….. 1.455fS
±0.0005
–100
dB
33.7tS
S
0
−20
1
0.8
0.6
0.4
0.2
0
−40
−60
−80
−100
−120
−0.2
−0.4
0
0.5
1
0
10 20 30 40 50 60 70 80 90 100 110 120
Samples
Frequency (x fS)
G003
G004
Figure 57. High-Attentuation x2 Interpolation Filter Figure 58. High-Attentuation x2 Interpolation Filter
Frequency Response, Quad Rate
0.002
Impulse Response, Quad Rate
0.0015
0.001
0.0005
0
−0.0005
−0.001
−0.0015
−0.002
0
0.25
0.5
Frequency (x fS)
G102
Figure 59. High-Attentuation x2 Interpolation Filter Passband Ripple, Quad Rate
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8.6.3 Fixed Audio Processing Flow (Program 5)
The PCM5242 implements signal processing capabilities and interpolation filtering via processing blocks. These
fixed processing blocks give users the choice of how much and what type of signal processing they may use and
which interpolation filter is applied.
The signal processing blocks available are:
•
•
•
•
•
Biquad filters
Multiband DRC
Mono mixer
Stereo mixer
Master volume
The addresses of the coefficients are fixed when selecting the fixed processing flow, however, if these
components are used in the RAM source mode (Program 31) the registers for coefficients will change. Users can
find more details in Purepath Studio.
NOTE
This process flow requires 1024 instruction cycles. Therefore, it will only function at
sampling frequencies up to 48kHz.
8.6.3.1 Processing Blocks – Detailed Descriptions
Figure 60 shows the fixed processing flow.
(7)
2 BQ
(5)
2 BQ
(1)
6 BQ
(3)
2 BQ
Lch
Rch
2ch
Interpolation
Filter
3 Band
DRC
Stereo
Mixer
DIN
Master
Volume
(2)
6 BQ
(4)
2 BQ
1ch I2S out
(6)
2 BQ
Stereo
Mux
(8)
2 BQ
Coeff-1
Coeff-2
Mono
Mixer
Figure 60. Preset Process Flow
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Figure 61 shows a screen capture of PurePath Studio.
Figure 61. PurePath Studio Screen Capture
8.6.3.2 Biquad Section
The transfer function of each of the biquad filters is given by
N 0 + 2N1z -1 + N 2 z -2
2 2 3 - 2D 1z -1 - D 2 z - 2
H (z )=
(1)
N0
+
Z-1
Z-1
D1*2
D2
N1*2
Z-1
Z-1
N2
Figure 62. Biquad Block
Table 21. Biquad Filter Coefficients
Filter
Channel
Coefficient
Register
N0
N1
N2
D1
D2
N0
N1
N2
D1
D2
C10 (Pg 44, Reg 48,49,50,51)
C11 (Pg 44, Reg 52,53,54,55)
C12 (Pg 44, Reg 56,57,58,59)
C13 (Pg 44, Reg 60,61,62,63)
C14 (Pg 44, Reg 64,65,66,67)
C15 (Pg 44, Reg 68,69,70,71)
C16 (Pg 44, Reg 72,73,74,75)
C17 (Pg 44, Reg 76,77,78,79)
C18 (Pg 44, Reg 80,81,82,83)
C19 (Pg 44, Reg 84,85,86,87)
Lch,
Rch
BIQUAD (1) - 1 BIQUAD (2) - 1
Lch,
Rch
BIQUAD (1) - 2 BIQUAD (2) - 2
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Table 21. Biquad Filter Coefficients (continued)
Filter
Channel
Coefficient
N0
N1
N2
D1
D2
N0
N1
N2
D1
D2
N0
N1
N2
D1
D2
N0
N1
N2
D1
D2
N0
N1
N2
D1
D2
N0
N1
N2
D1
D2
N0
N1
N2
D1
D2
N0
N1
N2
D1
D2
N0
N1
N2
D1
D2
Register
C20 (Pg 44, Reg 88,89,90,91)
C21 (Pg 44, Reg 92,93,94,95)
Lch,
Rch
BIQUAD (1) - 3 BIQUAD (2) - 3
C22 (Pg 44, Reg 96,97,98,99)
C23 (Pg 44, Reg 100,101, 102, 103)
C24 (Pg 44, Reg 104, 105, 106, 107)
C25 (Pg 44, Reg 108, 109, 110, 111)
C26 (Pg 44, Reg 112, 113, 114, 115)
C27 (Pg 44, Reg 116, 117, 118, 119)
C28 (Pg 44, Reg 120, 121, 122, 123)
C29 (Pg 44, Reg 124, 125, 126, 127)
C30 (Pg 45, Reg 8, 9, 10, 11)
Lch,
Rch
BIQUAD (1) - 4 BIQUAD (2) - 4
BIQUAD (1) - 5 BIQUAD (2) - 5
BIQUAD (1) - 6 BIQUAD (2) - 6
BIQUAD (3) - 1 BIQUAD (4) - 1
BIQUAD (3) - 2 BIQUAD (4) - 2
BIQUAD (5) - 1 BIQUAD (6) - 1
BIQUAD (5) - 2 BIQUAD (6) - 2
BIQUAD (7) - 1 BIQUAD (8) - 1
C31 (Pg 45, Reg 12, 13, 14, 15)
C32 (Pg 45, Reg 16, 17, 18, 19)
C33 (Pg 45, Reg 20, 21, 22, 23)
C34 (Pg 45, Reg 24, 25, 26, 27)
C35 (Pg 45, Reg 28, 29, 30, 31)
C36 (Pg 45, Reg 32, 33, 34, 35)
C37 (Pg 45, Reg 36, 37, 38, 39)
C38 (Pg 45, Reg 40, 41, 42, 43)
C39 (Pg 45, Reg 44, 45, 46, 47)
C40 (Pg 45, Reg 48, 49, 50, 51)
C41 (Pg 45, Reg 52, 53, 54, 55)
C42 (Pg 45, Reg 56, 57, 58, 59)
C43 (Pg 45, Reg 60, 61, 62, 63)
C44 (Pg 45, Reg 64, 65, 66, 67)
C45 (Pg 45, Reg 68, 69, 70, 71)
C46 (Pg 45, Reg 72, 73, 74, 75)
C47 (Pg 45, Reg 76, 77, 78, 79)
C48 (Pg 45, Reg 80, 81, 82, 83)
C49 (Pg 45, Reg 84, 85, 86, 87)
C50 (Pg 45, Reg 88, 89, 90, 91)
C51 (Pg 45, Reg 92, 93, 94, 95)
C52 (Pg 45, Reg 96, 97, 98, 99)
C53 (Pg 45, Reg 100, 101, 102, 103)
C54 (Pg 45, Reg 104, 105, 106, 107)
C55 (Pg 45, Reg 108, 109, 110, 111)
C56 (Pg 45, Reg 112, 113, 114, 115)
C57 (Pg 45, Reg 116, 117, 118, 119)
C58 (Pg 45, Reg 120, 121, 122, 123)
C59 (Pg 45, Reg 124, 125, 126, 127)
C60 (Pg 46, Reg 8, 9, 10, 11)
Lch,
Rch
Lch,
Rch
Lch,
Rch
Lch,
Rch
Lch,
Rch
Lch,
Rch
C61 (Pg 46, Reg 12, 13, 14, 15)
C62 (Pg 46, Reg 16, 17, 18, 19)
C63 (Pg 46, Reg 20, 21, 22, 23)
C64 (Pg 46, Reg 24, 25, 26, 27)
Lch,
Rch
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Table 21. Biquad Filter Coefficients (continued)
Filter
Channel
Coefficient
Register
N0
N1
N2
D1
D2
C65 (Pg 46, Reg 28, 29, 30, 31)
C66 (Pg 46, Reg 32, 33, 34, 35)
C67 (Pg 46, Reg 36, 37, 38, 39)
C68 (Pg 46, Reg 40, 41, 42, 43)
C69 (Pg 46, Reg 44, 45, 46, 47)
Lch,
Rch
BIQUAD (7) - 2 BIQUAD (8) - 2
8.6.3.3 Dynamic Range Compression
Dynamic range compression (DRC) improves the overall listening experience. Typical music signals are
characterized by crest factors (the ratio of peak signal power to average signal power) of 12dB or more. To avoid
audible distortion due to clipping of peak signals, the gain of the DAC channel must be adjusted so as not to
cause hard clipping. As a result, the low applied gain during nominal periods causes the perception that the
signal is not loud enough. To overcome this problem, the DRC in the PCM5242 continuously monitors the output
of the DAC Digital Volume control to detect its power level with respect to 0dB full-scale. When the power level is
low, the DRC increases the input signal gain to make it sound louder, and reduces the gain during peaks to
avoid hard clipping. The DRC enables louder audio during nominal periods with a clearer, more pleasant
listening experience.
The 3-band DRC function applies DRC to 3 different mono/stereo signals with 3 different time constants. The
same DRC curve is applied on all the signals, enabling a multi-band DRC solution. The underlying DRC
algorithm is the same as that available with the DRC component in PurePath Studio. In this instance, the DRC
gain acts on each signal in time-multiplexed order, for example, 1-2-3, 1-2-3, 1-2-3.
Table 22. DRC Coefficients
Coefficient
Register
Description
DRC_MB_1_DRC_1_DRCAE
DRC_MB_1_DRC_1_DRC1AE
DRC_MB_1_DRC_1_DRCAA
DRC_MB_1_DRC_1_DRC1AA
DRC_MB_1_DRC_1_DRCAD
DRC_MB_1_DRC_1_DRC1AD
DRC_MB_1_DRC_2_DRCAE
DRC_MB_1_DRC_2_DRC1AE
DRC_MB_1_DRC_2_DRCAA
DRC_MB_1_DRC_2_DRC1AA
DRC_MB_1_DRC_2_DRCAD
DRC_MB_1_DRC_2_DRC1AD
DRC_MB_1_DRC_3_DRCAE
DRC_MB_1_DRC_3_DRC1AE
DRC_MB_1_DRC_3_DRCAA
DRC_MB_1_DRC_3_DRC1AA
DRC_MB_1_DRC_3_DRCAD
DRC_MB_1_DRC_3_DRC1AD
DRC_MB_1_DRC_DRCK0
DRC_MB_1_DRC_DRCK1
DRC_MB_1_DRC_DRCK2
DRC_MB_1_DRC_DRCMT1
DRC_MB_1_DRC_DRCMT2
DRC_MB_1_DRC_DRCOFF1
DRC_MB_1_DRC_DRCOFF2
DRC_MB_1_MinusOne_Q22
C70 (Pg 46, Reg 48, 49, 50, 51)
C71 (Pg 46, Reg 52, 53, 54, 55)
C72 (Pg 46, Reg 56, 57, 58, 59)
C73 (Pg 46, Reg 60, 61, 62, 63)
C74 (Pg 46, Reg 64, 65, 66, 67)
C75 (Pg 46, Reg 68, 69, 70, 71)
C76 (Pg 46, Reg 72, 73, 74, 75)
C77 (Pg 46, Reg 76, 77, 78, 79)
C78 (Pg 46, Reg 80, 81, 82, 83)
C79 (Pg 46, Reg 84, 85, 86, 87)
C80 (Pg 46, Reg 88, 89, 90, 91)
C81 (Pg 46, Reg 92, 93, 94, 95)
C82 (Pg 46, Reg 96, 97, 98, 99)
C83 (Pg 46, Reg 100, 101, 102, 103)
C84 (Pg 46, Reg 104, 105, 106, 107)
C85 (Pg 46, Reg 108, 109, 119, 111)
C86 (Pg 46, Reg 112, 113, 114, 115)
C87 (Pg 46, Reg 116, 117, 118, 119)
C88 (Pg 46, Reg 120, 121, 122, 123)
C89 (Pg 46, Reg 124, 125, 126, 127)
C90 (Pg 47, Reg 8, 9, 10, 11)
C91 (Pg 47, Reg 12, 13, 14, 15)
C92 (Pg 47, Reg 16, 17, 18, 19)
C93 (Pg 47, Reg 20, 21, 22, 23)
C94 (Pg 47, Reg 24, 25, 26, 27)
C95 (Pg 47, Reg 28, 29, 30, 31)
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Table 22. DRC Coefficients (continued)
Coefficient
Register
Description
DRC_MB_1_MinusTwo_Q22
DRC_MB_1_One_M2
DRC_MB_1_Zero
C96 (Pg 47, Reg 32, 33, 34, 35)
C97 (Pg 47, Reg 36, 37, 38, 39)
C98 (Pg 47, Reg 40, 41, 42, 43)
C99 (Pg 47, Reg 44, 45, 46, 47)
C100 (Pg 47, Reg 48, 49, 50, 51)
C101 (Pg 47, Reg 52, 53, 54, 55)
C102 (Pg 47, Reg 56, 57, 58, 59)
C103 (Pg 47, Reg 60, 61, 62, 63)
C104 (Pg 47, Reg 64, 65, 66, 67)
C105 (Pg 47, Reg 68, 69, 70, 71)
C106 (Pg 47, Reg 72, 73, 74, 75)
C107 (Pg 47, Reg 76, 77, 78, 79)
C108 (Pg 47, Reg 80, 81, 82, 83)
C109 (Pg 47, Reg 84, 85, 86, 87)
C110 (Pg 47, Reg 88, 89, 90, 91)
C111 (Pg 47, Reg 92, 93, 94, 95)
C112 (Pg 47, Reg 96, 97, 98, 99)
C113 (Pg 47, Reg 100, 101, 102, 103)
C114 (Pg 47, Reg 104, 105, 106, 107)
C115 (Pg 47, Reg 108, 109, 119, 111)
C116 (Pg 47, Reg 112, 113, 114, 115)
C117 (Pg 47, Reg 116, 117, 118, 119)
C118 (Pg 47, Reg 120, 121, 122, 123)
C119 (Pg 47, Reg 124, 125, 126, 127)
C120 (Pg 48, Reg 8, 9, 10, 11)
C121 (Pg 48, Reg 12, 13, 14, 15)
C122 (Pg 48, Reg 16, 17, 18, 19)
C123 (Pg 48, Reg 20, 21, 22, 23)
C124 (Pg 48, Reg 24, 25, 26, 27)
C125 (Pg 48, Reg 28, 29, 30, 31)
C126 (Pg 48, Reg 32, 33, 34, 35)
C127 (Pg 48, Reg 36, 37, 38, 39)
C128 (Pg 48, Reg 40, 41, 42, 43)
C129 (Pg 48, Reg 44, 45, 46, 47)
C130 (Pg 48, Reg 48, 49, 50, 51)
C131 (Pg 48, Reg 52, 53, 54, 55)
C132 (Pg 48, Reg 56, 57, 58, 59)
C133 (Pg 48, Reg 60, 61, 62, 63)
C134 (Pg 48, Reg 64, 65, 66, 67)
C135 (Pg 48, Reg 68, 69, 70, 71)
C136 (Pg 48, Reg 72, 73, 74, 75)
C137 (Pg 48, Reg 76, 77, 78, 79)
C138 (Pg 48, Reg 80, 81, 82, 83)
C139 (Pg 48, Reg 84, 85, 86, 87)
C140 (Pg 48, Reg 88, 89, 90, 91)
C141 (Pg 48, Reg 92, 93, 94, 95)
C142 (Pg 48, Reg 96, 97, 98, 99)
DRC_MB_1_En_dB
DRC_MB_1_Minus__Zero_dB
DRC_MB_1_60_dB
DRC_MB_1_Minus_60_dB
DRC_MB_1_12_dB
DRC_MB_1_Offset
DRC_MB_1_K
DRC_MB_1_x / DRC_MB_1_DRC
DRC_MB_1_48_dB
DRC_MB_1_Minus_48_dB
DRC_MB_1_c1_3
DRC_MB_1_c1_2
DRC_MB_1_c1_1
DRC_MB_1_c1_0
DRC_MB_1_O1_1
DRC_MB_1_S1_1
DRC_MB_1_O1_2
DRC_MB_1_S1_2
DRC_MB_1_O1_3
DRC_MB_1_S1_3
DRC_MB_1_One_1_Q17
DRC_MB_1_Scale1
DRC_MB_1_x1Coeff
DRC_MB_1_c2_3
DRC_MB_1_c2_2
DRC_MB_1_c2_1
DRC_MB_1_c2_0
DRC_MB_1_O2_1
DRC_MB_1_S2_1
DRC_MB_1_O2_2
DRC_MB_1_S2_2
DRC_MB_1_O2_3
DRC_MB_1_S2_3
DRC_MB_1_One_2_Q17
DRC_MB_1_Scale2
DRC_MB_1_x2Coeff
DRC_MB_1_R1_1
DRC_MB_1_R1_2
DRC_MB_1_R2_1
DRC_MB_1_R2_2
DRC_MB_1_Band1_GainC
DRC_MB_1_Band2_GainC
DRC_MB_1_Band3_GainC
DRC_MB_1_MinusOne_M1
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Table 22. DRC Coefficients (continued)
Coefficient
Register
Description
DRC_MB_1_One_M1
DRC_MB_1_Band1_GainE
DRC_MB_1_Band2_GainE
DRC_MB_1_Band3_GainE
DRC_MB_1_minus_One_M2
C143 (Pg 48, Reg 100, 101, 102, 103)
C144 (Pg 48, Reg 104, 105, 106, 107)
C145 (Pg 48, Reg 108, 109, 110, 111)
C146 (Pg 48, Reg 112, 113, 114, 115)
C147 (Pg 48, Reg 116, 117, 118, 119)
8.6.3.4 Stereo Mixer
Three stereo inputs are mixed into one stereo output with input signal gain given by Equation 2.
Out _ L(n)=
(Input _ L(i,n)· Gain(i))
å
where
•
i=1:2,3
(2)
Figure 63 and Table 23 show the strereo mixer operation.
Gain1
Gain2
Gain3
L1
R1
L2
R2
x
x
x
x
x
x
Lch
Rch
L3
R3
Figure 63. Stereo Mixer Block
Table 23. Stereo Mixer Coefficients
Coefficient
Register
Description
Stereo_Mixer_1_MixGain1
Stereo_Mixer_1_MixGain2
Stereo_Mixer_1_MixGain3
C148 (Pg 48, Reg 120, 121, 122, 123)
C149 (Pg 48, Reg 124, 125, 126, 127)
C150 (Pg 49, Reg 8, 9, 10, 11)
8.6.3.5 Stereo Multiplexer
The Stereo Multiplexer selects one or 2 from 4 stereo input channels.
Select
L1
Lch
R1
L2
Rch
R2
Figure 64. Stereo Multiplexer Block
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Table 24. Stereo Multiplexer Select Coefficient
Coefficient
Register
Description
Stereo_Mux_1_MuxSelect
C152 (Pg 49, Reg 16, 17, 18, 19)
Table 25. Stereo Multiplexer Input Coefficient
Coefficient
Register
Description
C_to_D_1_Coefval
C_to_D_2_Coefval
C153 (Pg 49, Reg 20, 21, 22, 23)
8.6.3.6 Mono Mixer
The Mono Mixer computes a weighted sum of 2 input channels and produces an output.
Gain1
Gain2
Ch-1
x
x
Mono output
Ch-2
Figure 65. Mono Mixer Block
Table 26. Mono Mixer Coefficients
Coefficient
Register
Description
Mono_Mixer_1_MixGain1
Mono_Mixer_1_MixGain2
C154 (Pg 49, Reg 24, 25, 26, 27)
C155 (Pg 49, Reg 28, 29, 30, 31)
8.6.3.7 Master Volume Control
The Master Volume controls the volume using a linear ramp and zero crossing detection for transitions.
Table 27. Mono Mixer Coefficients
Coefficient
Register
Description
Volume_ZeroX_1_volcmd
Volume_ZeroX_1_volout
C158 (Pg 49, Reg 40, 41, 42, 43)
C159 (Pg 49, Reg 44, 45, 46, 47)
Volume_ZeroX_1_volout_loudne
ss
C160 (Pg 49, Reg 48, 49, 50, 51)
Volume_ZeroX_1_MinusOne_M2 C161 (Pg 49, Reg 52, 53, 54, 55)
Volume_ZeroX_1_workingval_1_
C162 (Pg 49, Reg 56, 57, 58, 59)
pre_CRAM
Volume_ZeroX_1_volout_pre1
C163 (Pg 49, Reg 60, 61, 62, 63)
C164 (Pg 49, Reg 64, 65, 66, 67)
C165 (Pg 49, Reg 68, 69, 70, 71)
C166 (Pg 49, Reg 72, 73, 74, 75)
Volume_ZeroX_1_workingval_2_
pre_CRAM
Volume_ZeroX_1_volout_pre2
Volume_ZeroX_1_workingval_3_
pre_CRAM
Volume_ZeroX_1_volout_pre3
Volume_ZeroX_1_One_M2
Volume_ZeroX_1_Zero
MinusOne_Int
C167 (Pg 49, Reg 76, 77, 78, 79)
C168 (Pg 49, Reg 80, 81, 82, 83)
C169 (Pg 49, Reg 84, 85, 86, 87)
C170 (Pg 49, Reg 88, 89, 90, 91)
C171 (Pg 49, Reg 92, 93, 94, 95)
C172 (Pg 49, Reg 96, 97, 98, 99)
C173 (Pg 49, Reg 100, 101, 102, 103)
C174 (Pg 49, Reg 104, 105, 106, 107)
MinusOne_M1
One_M2
One_M1
Zero
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8.6.3.8 Miscellaneous Coefficients
Table 28. Miscellaneous Coefficients
Coefficient
Register
Description
DRC_MB_1_DataBlock
DRC_MB_1_CoeffBlock
Volume_ZeroX_1_DataBlock
Volume_ZeroX_1_CoeffBlock
plus_one
C175 (Pg 49, Reg 108, 109, 110, 111)
C176 (Pg 49, Reg 112, 113, 114, 115)
C177 (Pg 49, Reg 116, 117, 118, 119)
C178 (Pg 49, Reg 120, 121, 122, 123)
C179 (Pg 49, Reg 124, 125, 126, 127)
C180 (Pg 50, Reg 8, 9, 10, 11)
ADD_OF_filter_in_L
ADD_OF_filter_in_R
C181 (Pg 50, Reg 12, 13, 14, 15)
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8.7 DAC and Differential Analog Outputs
8.7.1 Analog Outputs
The PCM5242 devices include a two-channel DAC, with differential outputs. Each pin has a full-scale output
voltage is 2.1Vrms with ground center output. This equates to a 4.2Vrms differential output. A dc-coupled load is
supported in addition to an ac-coupled load, if the load resistance conforms to the specification. The PCM5242
DAC outputs on the OUTLP, OUTLN, OUTRP, and OUTRN terminals have market-leading low out-of-band
noise, which offer up to 20dB lower out-of-band noise compared with existing DAC technology.
Many applications require an external low-pass RC filter (470Ω + 1.2nF) to provide sufficient out-of-band noise
rejection. This RC filter provides the added advantage of improved protection against ESD damage.
The PCM5242 can also support single ended outputs, using OUTLP and OUTRP respectively. A single 470Ω
and 2.2nF capacitor can be used on each pin in single ended mode.
The choice between VREF and VCOM modes affects the maximum output level. This is explained in Voltage
Reference and Output Levels.
Optional RC Low-Pass Filter
P Output
4.3nF
470W
470W
N Output
6
OUTLP
OUTLN
OUTRN
OUTRP
+
RC LPF
Left Differential Output
7
8
9
-
-
Right Differential Output RC LPF
+
Figure 66. Optional Low Pass Filters
8.7.2 Choosing Between VREF and VCOM Modes
VREF mode is the default configuration. This mode allows full 2.1Vrms signal output. As shown in Recommended
Operating Conditions, the minimum AVDD to avoid clipping is 3.2V.
VCOM mode allows setting a custom common-mode voltage when required by the application. This somewhat
limits the output signal swing before clipping.
8.7.2.1 Voltage Reference and Output Levels
The PCM5242 has an internal, fixed band-gap reference voltage, with default operation in VREF mode. No
external decoupling capacitor is required for this mode.
The PCM5242 can be operated with a common-mode voltage output (VCOM mode) at the VCOM pin by setting
Page 1, Register 1, D(0) to 1. In this mode, an external decoupling capacitor is required.
When using this DAC in VREF mode, the output-signal voltage is independent of the power-supply voltage: The
D/A conversion gain in VREF mode yields a 2.1Vrms output voltage with a digital full-scale input. However, in
VREF mode, an output waveform may clip due to the limitations that may be present in the analog power supply
voltage. On the other hand, the full-scale output voltage in VCOM mode is proportional to the analog power
supply AVDD. Example, (2.1 × AVDD / 3.3) Vrms
.
8.7.2.2 Mode Switching Sequence, From VREF Mode to VCOM Mode
Following register setting sequence is recommended for changing VREF mode to VCOM mode.
1. Page 0 / Register 2
RQST = 1: Standby mode
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DAC and Differential Analog Outputs (continued)
2. Page 1 / Register 8
3. Page 1 / Register 9ꢀ
4.
RCMF = 1: Fast ramp up → on
VCPD = 0: VCOM is power on
Wait 3ms with external capacitor = 1µF
RCMF = 0: Fast ramp up → off
OSEL = 1: VCOM mode
5. Page 1 / Register 8
6. Page 1 / Register 1
7. Page 0 / Register 2
RQST = 0: Normal mode
8.7.3 Digital Volume Control
A basic digital volume control with range from 24 dB to -103 dB and mute is available on each channels by Page
0, Resister 61, D(7:0) for L-ch and Register 62, D(7:0) for R-ch. These volume controls all have 0.5 dB step
programmability over most gain and attenuation ranges. Table 29 lists the detailed gain versus programmed
setting for this basic volume control. Volume can be changed for both L-ch and R-ch at the same time or
independently by Page 0, Register 60, D(1:0). When D(1:0) set 00 (default), independent control is selected.
When D(1:0) set 01, R-ch accords with L-ch volume. When D(1:0) set 10, L-ch accords with R-ch volume. To set
D(1:0) to 11 is prohibited.
NOTE
This volume control is done externally to the miniDSP and only influences the analog DAC
output. Any changes to the SDOUT data should be done in the miniDSP process flow
Table 29. Digital Volume Control Settings
Gain
Setting
Gain
(dB)
Binary Data
Comments
0
1
0000-0000
0000-0001
:
24.0
23.5
:
Positive maximum
:
46
47
48
49
50
51
:
0010-1110
0010-1111
0011-0000
0011-0001
0011-0010
0011-0011
:
1.0
0.5
0.0
No attenuation (default)
- 0.5
- 1.0
- 1.5
:
253
254
255
1111-1101
1111-1110
1111-1111
- 102.5
- 103
- ∞
Negative maximum
Negative infinite (Mute)
Ramp-up frequency and ramp-down frequency can be controlled by Page 0, Register 63, D(7:6) and D(3:2) as
shown in Table 30. Also Ramp-up step and ramp-down step can be controlled by Page 0, Register 63 D(5:4) and
D(1:0) as shown in Table 31.
Table 30. Ramp Up or Down Frequency
Ramp up
speed
Ramp down
frequency
Every N fS
Comments
Every N fS
Comments
00
01
10
11
1
Default
00
01
10
11
1
Default
2
2
4
4
Direct change
Direct change
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Table 31. Ramp Up or Down Step
Ramp down
Ramp up step
Step dB
Comments
step
Step dB
Comments
00
01
10
11
4.0
2.0
1.0
0.5
00
01
-4.0
-2.0
-1.0
-0.5
Default
10
11
Default
8.7.3.1 Emergency Ramp Down
Digital volume emergency ramp down by is provided for situations such as I2S clock error and power supply
failure. Ramp-down speed is controlled by Page 0, Register 64, D(7:6). Ramp-down step can be controlled by
Page 0 Register 64, D(5:4). Default is ramp-down by every fS cycle with -4dB step.
8.7.4 Analog Gain Control
Analog gain control can be selected between 2Vrms FS (0dB) or 1Vrms FS (-6dB). Gain is controlled via hardware
by the AGNS pin, and via software (SPI/I2C), Page 1, Register 2, D4(L-ch) / D0(R-ch).
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8.8 Reset and System Clock Functions
8.8.1 Clocking Overview
The PCM5242 devices have flexible systems for clocking. Internally, the device requires a number of clocks,
mostly at related clock rates to function correctly. All of these clocks can be derived from the Serial Audio
Interface in one form or another.
Serial Audio
Interface
(Input)
Delta
Sigma
Modulator
miniDSP
Current
Segments
I
Line Driver
V
fS (24bit)
16fS (24bit)
128fS (~8 bit)
+
(inc interpolator)
-3V3
-3v3 Charge
Pump
CPCK
Figure 67. Audio flow with respective clocks
As shown in Figure 67 the basic data flow at basic sample rate (fS). Once the data is brought into the serial audio
interface, it gets processed, interpolated and modulated all the way to 128 × fS before arriving at the current
segments for the final digital to analog conversion.
The clock tree is shown in Figure 68.
PLLEN (Pg0, Reg 4 0x04)
SCK
DSPCK (miniDSP Clock )
Divider
DDSP (Pg0, Reg 27 0x1B)
SREF (Pg0, Reg 13 0x0D)
SDAC (Pg0, Reg 14
0x0E)
BCK
DAC
CLK
PLL
SCK
DACCK (DAC Clock )
GPIO*
SCK
Divider
Source
GPIO* Mux
K * R / P
PLLCKIN
PLLCK
DDAC (Pg0, Reg 28 0x1C)
CPCK (Charge Pump Clock )
Divider
Divider
DNCP (Pg0, Reg 29 0x1D)
K = J.D
J = 1,2,3,…..,62,63
D= 0000,0001,….,9998,9999
R= 1,2,3,4,….,15,16
P= 1,2,….,127,128
OSRCK (Oversampling Ratio Clock )
MUX
Divide
by 2
DOSR (Pg0, Reg 30 0x1E)
I16E (Pg0, Reg 34 0x22)
Figure 68. PCM5242 Clock Distribution Tree
The Serial Audio Interface typically has 4 connections SCK (System Master Clock), BCK (Bit Clock), LRCK (Left
Right Word Clock) and Data. The device has an internal PLL that is used to take either SCK or BCK and create
the higher rate clocks required by the miniDSP and the DAC clock.
In situations where the highest audio performance is required, it’s suggested that the SCK is brought to the
device, along with BCK and LRCK. The device should be configured so that the PLL is only providing a clock
source to the miniDSP. By ensuring that the DACCK (DAC Clock) is being driven by the external SCK source,
jitter evident in the PLL (in all PLL's) is kept out of the DAC, Charge Pump and Oversampling system.
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Reset and System Clock Functions (continued)
Everything else should be a division of the incoming SCK. This is done by setting DAC CLK Source Mux (SDAC
in the diagram above) to use SCK as a source, rather than the output of the SCK/PLL Mux. Code Examples for
this are available in SLAC622
When the Auto Clock Configuration bit is set (Page0/ Register 0x25), no additional clocks configuration is
required. However, when setting custom PLL values etc, the target output rates should match those shown in the
recommended PLL values of Table 50.
8.8.2 Clock Slave Mode With Master Clock (SCK) Input (4 Wire I2S)
The PCM5242 requires a system clock to operate the digital interpolation filters and advanced segment DAC
modulators. The system clock is applied at the SCK input and supports up to 50MHz. The PCM5242 system-
clock detection circuit automatically senses the system-clock frequency. Common audio sampling frequencies in
the bands of 8kHz, 16kHz, (32kHz - 44.1kHz - 48kHz), (88.2kHz - 96kHz), (176.4kHz -192kHz), and 384kHz with
±4% tolerance are supported. Values in the parenthises are "grouped" when detected, e.g. 88.2kHZ and
96kHz are detected as "double rate", 32kHz, 44.1kHz and 48kHz will be detected as "single rate".
In the presence of a valid bit SCK, BCK and LRCK in software mode, the device will autoconfigure the clock tree
and PLL to drive the miniDSP as required.
The sampling frequency detector sets the clock for the digital filter, Delta Sigma Modulator (DSM) and the
Negative Charge Pump (NCP) automatically. Table 32 shows examples of system clock frequencies for common
audio sampling rates.
SCK rates that are not common to standard audio clocks, between 1MHz and 50MHz, are only supported in
software mode by configuring various PLL and clock-divider registers. This programmability allows the device to
become a clock master and drive the host serial port with LRCK and BCK, from a non-audio related clock (for
example, using 12MHz to generate 44.1kHz (LRCK) and 2.8224MHz (BCK) ).
Table 32. System Master Clock Inputs for Audio Related Clocks
System Clock Frequency (fSCK) (MHz)
Sampling
Frequency
64 fS
128 fS
192 fS
256 fS
2.0480
384 fS
3.0720
512 fS
4.0960
768 fS
6.1440
1024 fS
8.1920
1152 fS
9.2160
1536 fS
12.2880
24.5760
49.1520
2048 fS
16.3840
36.8640
3072 fS
24.5760
49.1520
(1)
8 kHz
16 kHz
–
1.0240(2) 1.5360(2)
2.0480(2) 3.0720(2)
4.0960(2) 6.1440(2)
5.6488(2) 8.4672(2)
6.1440(2) 9.2160(2)
11.2896(2) 16.9344
12.2880(2) 18.4320
(1)
–
4.0960
6.1440
8.1920
12.2880
24.5760
33.8688
36.8640
16.3840
32.7680
45.1584
49.1520
18.4320
36.8640
(1)
(1)
(1)
32 kHz
–
8.1920
12.2880
16.9344
18.4320
33.8688
36.8640
16.3840
22.5792
24.5760
45.1584
49.1520
–
–
(1)
(1)
(1)
(1)
(1)
44.1 kHz
48 kHz
–
11.2896
12.2880
22.5792
24.5760
45.1584
49.1520
–
–
–
–
(1)
(1)
(1)
(1)
(1)
–
–
–
–
–
(1)
(1)
(1)
(1)
(1)
(1)
(1)
88.2 kHz
96 kHz
–
–
–
–
–
–
–
(1)
(1)
(1)
(1)
(1)
(1)
(1)
–
–
–
–
–
–
–
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
176.4 kHz
192 kHz
384 kHz
–
22.5792
24.5760
49.1520
33.8688
36.8640
–
–
–
–
–
–
–
–
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
–
–
–
–
–
–
–
–
–
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
24.5760
–
–
–
–
–
–
–
–
–
–
(1) This system clock rate is not supported for the given sampling frequency.
(2) This system clock rate is supported by PLL mode.
See Timing Requirements: PCM Audio Data for clock timing requirements.
8.8.3 Clock Slave Mode with BCK PLL to Generate Internal Clocks (3-Wire PCM)
The system clock PLL mode allows designers to use a simple 3-wire I2S audio source. The 3-wire source
reduces the need for a high frequency SCK, making PCB layout easier, and reduces high frequency
electromagnetic interference.
In hardwired mode, the internal PLL is disabled as soon as an external SCK is supplied.
In hardwired mode, the device starts up expecting an external SCK input, but if BCK and LRCK start correctly
while SCK remains at ground level for 16 successive LRCK periods, then the internal PLL starts, automatically
generating an internal SCK from the BCK reference. Specific BCK rates are required to generate an appropriate
master clock. Table 33 describes the minimum and maximum BCK per LRCK for the integrated PLL to
automatically generate an internal SCK.
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In software mode, the user must set all the PLL registers and clock divider registers for referencing BCK. See
Clock Generation Using The PLL for more information. Recommended values can be found in Table 50.
Table 33. BCK Rates (MHz) by LRCK Sample Rate for
PCM5242 PLL Operation
BCK (fS)
Sample f (kHz)
32
-
64
8
-
16
-
1.024
2.048
2.8224
3.072
6.144
12.288
24.576
32
1.024
1.4112
1.536
3.072
6.144
12.288
44.1
48
96
192
384
8.8.4 Clock Generation Using The PLL
The PCM5242 supports a wide range of options to generate the required clocks for the DAC section as well as
interface and other control blocks as shown in Figure 68.
The clocks for the PLL require a source reference clock. This clock is sourced as the incoming BCK or SCK. In
software mode, a GPIO can also be used.
The source reference clock for the PLL reference clock is selected by programming the SRCREF value on Page
0, Register 13, D(6:4). The PCM5242 provides several programmable clock dividers to achieve a variety of
sampling rates for the DAC and clocks for the NCP, OSR, and the miniDSP. OSRCK for OSR must be set at
16fS frequency by DOSR on Page0, Register 30, D(6:0). See Figure 68.
If PLL functionality is not required, set the PLLEN value on Page 0, Register 4, D(0) to 0. In this situation, an
external SCK is required.
Table 34. PLL Configuration Registers
Clock multiplexer
SREF
Function
Bits
PLL Reference
Function
Page 0, Register 13, D(6:4)
Bits
Divider
DDSP
miniDSP clock divider
DAC clock divider
NCP clock divider
OSR clock divider
External BCK Div
External LRCK Div
Page 0, Register 27, D(6:0)
Page 0, Register 28, D(6:0)
Page 0, Register 29, D(6:0)
Page 0, Register 30, D(6:0)
Page 0, Register 32, D(6:0)
Page 0, Register 33, D(7:0)
DACCK
CPCK
OSRCK
DBCK
DLRK
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8.8.5 PLL Calculation
The PCM5242 has an on-chip PLL with fractional multiplication to generate the clock frequency needed by the
audio DAC, Negative Charge Pump, Modulator and Digital Signal Processing blocks. The programmability of the
PLL allows operation from a wide variety of clocks that may be available in the system. The PLL input (PLLCKIN)
supports clock frequencies from 1MHz to 50MHz and is register programmable to enable generation of required
sampling rates with fine precision.
The PLL is enabled by default. The PLL can be turned on by writing to Page 0, Register 4, D(0). When the PLL
is enabled, the PLL output clock PLLCK is given by Equation 3:
PLLCKIN x R x J.D
P
PLLCKIN x R x K
P
PLLCK =
or PLLCK =
(3)
R = 1, 2, 3,4, ... , 15, 16
J = 4,5,6, . . . 63, and D = 0000, 0001, 0002, . . . 9999
K = [J value].[D value]
P = 1, 2, 3, ... 15
R, J, D, and P are programmable. J is the integer portion of K (the numbers to the left of the decimal point), while
D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision).
8.8.5.1 Examples:
•
•
•
•
If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004
When the PLL is enabled and D = 0000, the following conditions must be satisfied:
•
•
•
•
1MHz ≤ ( PLLCKIN / P ) ≤ 20MHz
64MHz ≤ (PLLCKIN x K x R / P ) ≤ 100MHz (in VREF mode)
72MHz ≤ (PLLCKIN x K x R / P ) ≤ 86MHz (in VCOM mode)
1 ≤ J ≤ 63
When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied:
•
•
•
•
•
6.667MHz ≤ PLLCLKIN / P ≤ 20MHz
64MHz ≤ (PLLCKIN x K x R / P ) ≤ 100MHz (in VREF mode)
72MHz ≤ (PLLCK IN x K x R / P ) ≤ 86MHz (in VCOM mode)
4 ≤ J ≤ 11
R = 1
When the PLL is enabled,
•
•
fS = (PLLCLKIN × K × R) / (2048 × P)
The value of N is selected so that fS × N = PLLCLKIN x K x R / P is in the allowable range.
Example: MCLK = 12MHz and fS = 44.1kHz, (N=2048)
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264
Example: MCLK = 12MHz and fS = 48.0kHz, (N=2048)
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920
Values are written to the registers in Table 35.
8.8.5.1.1 Recommended PLL settings
Recommended values for the PLL can be found after the register descriptions in this datasheet. Different values
are defined based on the device configuration for VREF or VCOM mode.
Other configurations are possible, at your own risk.
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Below are details of the register locations, as well as the nomenclature for the table of registers found at the end
of this document.
Table 35. PLL Registers
Divider
PLLE
Function
PLL enable
PLL P
Bits
Page 0, Register 4, D(0)
Page 0, Register 20, D(3:0)
Page 0, Register 21, D(5:0)
Page 0, Register 22, D(5:0)
Page 0, Register 23, D(7:0)
Page 0, Register 24, D(3:0)
PPDV
PJDV
PLL J
PDDV
PRDV
PLL D
PLL R
Table 36. PLL Configuration Recommendations
Column
fS (kHz)
RSCK
Description
Sampling frequency
Ratio between sampling frequency and SCK frequency (SCK frequency = RSCK x sampling frequency)
System master clock frequency at SCK input (pin 20)
SCK (MHz)
PLL VCO (MHz) PLL VCO frequency as PLLCK in Figure 68
One of the PLL coefficients in Equation 3
PLL REF (MHz) Internal reference clock frequency which is produced by SCK / P
P
M = K * R
K = J.D
R
The final PLL multiplication factor computed from K and R as described in Equation 3
One of the PLL coefficients in Equation 3
One of the PLL coefficients in Equation 3
PLL fS
DSP fS
NMAC
Ratio between fS and PLL VCO frequency (PLL VCO / fS)
Ratio between miniDSP operating clock rate and fS (PLL fS / NMAC)
The miniDSP clock divider value in Table 34
DSP CLK (MHz) The miniDSP operating frequency as DSPCK in Figure 68
MOD fS
Ratio between DAC operating clock frequency and fS (PLL fS / NDAC)
DAC operating frequency as DACCK in
MOD f (kHz)
NDAC
DAC clock divider value in Table 34
OSR clock divider value in Table 34 for generating OSRCK in Figure 68. DOSR must be chosen so that MOD fS / DOSR
= 16 for correct operation.
DOSR
NCP
CP f
NCP (negative charge pump) clock divider value in Table 34
Negative charge pump clock frequency (fS * MOD fS / NCP)
Percentage of error between PLL VCO / PLL fS and fS (mismatch error).
% Error
•
•
This number is typically zero but can be non-zero especially when K is not an integer (D is not zero).
This number may be non-zero only when the PCM5242 acts as a master.
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8.8.6 Clock Master Mode from Audio Rate Master Clock
In Master Mode, the device generates bit clock (BCK) and left-right clock (LRCK) and outputs them on the
appropriate pins. To configure the device in this mode, first put the device into reset, then use registers BCKO
and LRKO (Pg 0, Reg 9 0x09). Then reset the LRCK and BCK divider counters using bits RBCK and RLRK (Pg
0, Reg 12 0x0C). Finally exit reset.
An example of this is given in Register Programming Examples SLAC622.
Figure 69 shows a simplified serial port clock tree for the device in master mode.
Audio Related System Clock(SCK)
SCK
Divider
Q=1...128
BCKO(Bit Clock Output In Master Mode)
BCK
LRCKO (LR Clock Output In Master Mode)
Divider
Q=1...128
LRCK
Figure 69. Simplified clock tree for SCK sourced master mode
In master mode, SCK is an input and BCK/LRCK are outputs. BCK and LRCK are integer divisions of SCK.
Master mode with a non-audio rate master clock source will require external GPIO’s to use the PLL in standalone
mode.
The PLL will also need to be configured to ensure that the onchip miniDSP processor can be driven at its
maximum clock rate.
Register changes that need to be done include switching the device into master mode, and setting the divider
ratio.
Here is an example of using 24.576MCLK as a master clock source and driving the BCK and LRCK with integer
dividers to create 48kHz.
In this mode, the DAC section of the device is also running from the PLL output. While the PLL inside the
PCM5242 is one that has been spec’d well enough to achieve the stated performance, using the SCK CMOS
Oscillator source will have less jitter.
To switch the DAC clocks (SDAC in the Figure 68) the following registers should be modified
•
•
Clock Tree Flex Mode ( Page 253, Registers 0x3F and 0x40)
DAC & OSR Source Clock Register (Page 0, Reg 14) – set to 0x30 (SCK input, and OSR is set to whatever
the DAC source is)
•
The DAC clock divider should be 16FS.
–
–
–
16*48kHz = 768kHz
24.576MHz (SCK in) / 768kHz = 32
Therefor, divide ratio for register DDAC (Page 0, Reg 28 0x1C) should be set to 32. The may the register
is mapped gives 0x00 = 1, so 32 must be converter to 0x1F (31dec).
An example configuration can be found in SLAC622
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8.8.7 Clock Master from a Non-Audio Rate Master Clock
The classic example here is running 12MHz Master clock for a 48kHz sampling system. Given the clock tree for
the device (shown in Figure 68), a non-audio clock rate cannot be brought into the SCK to the PLL in master
mode. Therefore, the PLL source must be configured to be a GPIO pin, and the output brought back into another
GPIO pin.
NON AUDIO SCK
GPIOx
PLL
GPIOy
NEW
AUDIO
Master Mode
BCK Integer
Divider
SCK
SCK
Master Mode
LRCK Integer
Divider
BCK OUT
BCK
LRCK OUT
LRCK
Figure 70. Application diagram for using non-audio clock sources to generate audio clocks
The clock flow through the system is shown above. The newly generated SCK must be brought out of the device
on a GPIO pin, then brought into the SCK pin for integer division to create BCK and LRCK outputs.
NOTE
Pull up resistors should be used on BCK and LRCK in this mode to ensure the device
doesn't go into sleep mode.
A code example for configuring this mode is provided in SLAC622
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8.9 Device Functional Modes
8.9.1 Choosing A Control Mode
SPI Mode is selected by connecting MODE1 to DVDD. SPI mode uses four signal lines and allows higher-speed
full-duplex communication between the host and the PCM5242.
I2C Mode is selected by connecting MODE1 to DGND and Mode2 to DVDD. I2C uses two signal lines for half-
duplex communication, and is widely used in a variety of devices.
Hardware Control Mode is selected by connecting both MODE1 and MODE2 pins to DGND. Hardware control is
useful in applications that do not require on-the-fly device-reconfiguration changes in operating features such as
gain or filter latency selection.
See Pin Assignments for a comparison of pin assignments for the 32-terminal QFN.
8.9.1.1 Software Control
8.9.1.1.1 SPI Interface
The SPI interface is a 4-wire synchronous serial port which operates asynchronously to the serial audio interface
and the system clock (SCK). The serial control interface is used to program and read the on-chip mode registers.
The control interface includes MISO (pin 24), MOSI (pin 11), MC (pin 12), and MS (pin 18). MISO (Master In
Slave Out) is the serial data output, used to read back the values of the mode registers; MOSI (Master Out Slave
In) is the serial data input, used to program the mode registers.
MC is the serial bit clock, used to shift data in and out of the control port by falling edge of MC, and MS is the
mode control enable with LOW active, used to enable the internal mode register access. If feedback from the
device is not required, the MISO pin can be assigned to GPIO1 by register control.
8.9.1.1.1.1 Register Read/Write Operation
All read/write operations for the serial control port use 16-bit data words. Figure 71 shows the control data word
format. The most significant bit is the read/write bit. For write operations, the bit must be set to 0. For read
operations, the bit must be set to 1. There are seven bits, labeled IDX[6:0], that hold the register index (or
address) for the read and write operations. The least significant eight bits, D[7:0], contain the data to be written
to, or the data that was read from, the register specified by IDX[6:0].
Figure 71 and Figure 72 show the functional timing diagram to write or read through the serial control port. MS is
held at a logic-1 state until a register access. To start the register write or read cycle, set MS to logic 0. Sixteen
clocks are then provided on MC, corresponding to the 16 bits of the control data word on MOSI and read-back
data on MISO. After the eighth clock cycle has completed, the data from the indexed-mode control register
appears on MISO during the read operation. After the sixteenth clock cycle has completed, the data is latched
into the indexed-mode control register during the write operation. To write or read subsequent data, MS is set to
logic 1 once (See tMHH in Figure 76).
MSB
LSB
D0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 R/W
D7
D6
D5
D4
D3
D2
D1
Register Index (or Address)
Register Data
Figure 71. Control Data Word Format; MDI
NOTE
B8 is used for selection of “Write” or “Read”. Setting = 0 indicates a “Write”, while = 1
indicates a ”Read”. Bits 15–9 are used for register address. Bits 7–0 are used for register
data. Multiple-byte write or read (up to 8 bytes) is supported while MS is kept low. The
address field becomes the initial address, automatically incrementing for each byte.
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Device Functional Modes (continued)
MS
MC
A6 A5 A4 A3 A2 A1 A0
W
D7 D6 D5 D4 D3 D2 D1 D0
MOSI
MISO
HI-Z
Figure 72. Serial Control Format; Write, Single Byte
MS
MC
ADDR
BYTE 0
BYTE 1
BYTE 2
BYTE 3
HI-Z
BYTE 4
BYTE 5
BYTE 6
BYTE 7
MOSI
MISO
W
Figure 73. Serial Control Format; Write, Multiple Byte
MS
MC
MOSI
MISO
A6 A5 A4 A3 A2 A1 A0
R
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
HI-Z
HI-Z
Figure 74. Serial Control Format; Read
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Device Functional Modes (continued)
MS
MC
ADDR
BYTE 0
BYTE 0
BYTE 1
BYTE 1
BYTE 2
BYTE 2
BYTE 3
BYTE 3
BYTE 4
BYTE 4
BYTE 5
BYTE 5
BYTE 6
BYTE 6
BYTE 7
MOSI
MISO
R
HI-Z
HI-Z
BYTE 7
Figure 75. Serial Control Format; Read, Multiple Byte
Figure 76. Control Interface Timing
Table 37. Control Interface Timing
Parameters
Min
100
40
Max
Units
tMCY
tMCL
tMCH
tMHH
tMSS
tMSH
tMDH
tMDS
tMOS
MC Pulse Cycle Time
MC Low Level Time
MC High Level Time
MS High Level Time
MS ↓ Edge to MC ↑ Edge
MS Hold Time(1)
40
20
30
ns
30
MDI Hold Time
15
MDI Set-up Time
15
MC Rise Edge to MDO Stable
20
(1) MC falling edge for LSB to MS rising edge.
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8.9.1.1.2 I2C Interface
The PCM5242 supports the I2C serial bus and the data transmission protocol for standard and fast mode as a
slave device.
In I2C mode, the control terminals are changed as follows.
Table 38. I2C Pins and Functions
Signal
SDA
Pin
11
12
16
24
I/O
Description
I2C data
I2C clock
I2C address 2
I2C address 1
I/O
SCL
I
I
I
ADR2
ADR1
8.9.1.1.2.1 Slave Address
Table 39. I2C Slave Address
MSB
1
LSB
0
0
1
1
ADR2
ADR1
R/ W
The PCM5242 has 7 bits for its own slave address. The first five bits (MSBs) of the slave address are factory
preset to 10011 (0x9x). The next two bits of the address byte are the device select bits which can be user-
defined by the ADR1 and ADR0 terminals. A maximum of four devices can be connected on the same bus at
one time. This gives a range of 0x98, 0x9A, 0x9C and 0x9E. Each PCM5242 responds when it receives its own
slave address.
8.9.1.1.2.2 Register Address Auto-Increment Mode
MSB
INC
LSB
A0
A6
A5
A4
A3
A2
A1
Figure 77. Auto Increment Mode
Auto-increment mode allows multiple sequential register locations to be written to or read back in a single
operation, and is especially useful for block write and read operations.
8.9.1.1.2.3 Packet Protocol
A master device must control packet protocol, which consists of start condition, slave address, read/write bit,
data if write or acknowledge if read, and stop condition. The PCM5242 supports only slave receivers and slave
transmitters.
SDA
SCL
9
1–7
8
9
1–8
9
1–8
9
Sp
St
Slave address
R/W
ACK
DATA
ACK
DATA
ACK
ACK
Start
condition
Stop
condition
R/W: Read operation if 1; otherwise, write operation
ACK: Acknowledgement of a byte if 0
DATA: 8 bits (byte)
Figure 78. Packet Protocol
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Table 40. Write Operation - Basic I2C Framework
Transmitter
Data Type
M
M
M
S
M
S
M
S
S
M
St
slave address
R/
ACK
DATA
ACK
DATA
ACK
ACK
Sp
Table 41. Read Operation - Basic I2C Framework
Transmitter
Data Type
M
M
M
S
S
M
S
M
M
M
St
slave address
R/
ACK
DATA
ACK
DATA
ACK
NACK
Sp
M = Master Device; S = Slave Device; St = Start Condition Sp = Stop Condition
8.9.1.1.2.4 Write Register
A master can write to any PCM5242 registers using single or multiple accesses. The master sends a PCM5242
slave address with a write bit, a register address with auto-increment bit, and the data. If auto-increment is
enabled, the address is that of the starting register, followed by the data to be transferred. When the data is
received properly, the index register is incremented by 1 automatically. When the index register reaches 0x7F,
the next value is 0x0. Table 42 shows the write operation.
Table 42. Write Operation
Transmitter
Data Type
M
M
M
S
M
S
M
S
M
S
S
M
reg
addr
write
data 1
write
data 2
St
slave addr
W
ACK
inc
ACK
ACK
ACK
ACK
Sp
M = Master Device; S = Slave Device; St = Start Condition Sp = Stop Condition; W = Write; ACK = Acknowledge
8.9.1.1.2.5 Read Register
A master can read the PCM5242 register. The value of the register address is stored in an indirect index register
in advance. The master sends a PCM5242 slave address with a read bit after storing the register address. Then
the PCM5242 transfers the data which the index register points to. When auto-increment is enabled, the index
register is incremented by 1 automatically. When the index register reaches 0x7F, the next value is 0x0. Table 43
shows the read operation.
Table 43. Read Operation
Transmitter
Data Type
M
M
M
S
M
S
M
M
M
S
S
M
M
M
slave
addr
reg
addr
slave
addr
St
W
ACK
inc
ACK
Sr
R
ACK
data
ACK
NACK
Sp
M = Master Device; S = Slave Device; St = Start Condition; Sr = Repeated start condition; Sp = Stop Condition;
W = Write; R = Read; NACK = Not acknowledge
8.9.1.1.2.6 Timing Characteristics
Repeated
START
START
STOP
tSDA-R
tSDA-F
tP-SU
tBUF
tD-HD
tD-SU
SDA
tLOW
tRS-HD
tSP
tSCL-R
SCL
tS-HD
tHI
tRS-SU
tSCL-F
Figure 79. Register Access Timing
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Table 44. I2C Bus Timing
SYMBOL
PARAMETER
SCL clock frequency
CONDITIONS
Standard
Fast
MIN
MAX
100
UNIT
kHz
fSCL
400
kHz
Standard
4.7
1.3
tBUF
tLOW
tHI
Bus free time between a STOP and START condition
Low period of the SCL clock
High period of the SCL clock
Setup time for (repeated)START condition
Hold time for (repeated)START condition
Data setup time
µs
µs
Fast
Standard
Fast
4.7
1.3
Standard
Fast
4.0
µs
ns
µs
ns
µs
ns
600
Standard
Fast
4.7
tRS-SU
600
tS-HD
Standard
Fast
4.0
tRS-HD
600
Standard
Fast
250
tD-SU
ns
ns
ns
ns
ns
ns
ns
100
Standard
Fast
0
900
900
tD-HD
Data hold time
0
Standard
Fast
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
4.0
1000
300
tSCL-R
tSCL-R1
tSCL-F
tSDA-R
tSDA-F
tP-SU
Rise time of SCL signal
Standard
Fast
1000
300
Rise time of SCL signal after a repeated START
condition and after an acknowledge bit
Standard
Fast
1000
300
Fall time of SCL signal
Standard
Fast
1000
300
Rise time of SDA signal
Fall time of SDA signal
Setup time for STOP condition
Standard
Fast
1000
300
Standard
Fast
µs
ns
pF
ns
600
CB
tSP
Capacitive load for SDA and SCL line
Pulse width of spike suppressed
400
50
Fast
Noise margin at High level for each connected device
(including hysteresis)
VNH
0.2VDD
V
8.9.2 Choosing Between VREF and VCOM Modes
See Choosing Between VREF and VCOM Modes for information on configuring these modes.
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application
Differential outputs DAC's are regularly used where higher performance is required from them compared to
single ended output DACs. They offer twice as much output voltage for the same power supply, along with noise
cancelling effect of differential signaling. The PCM5242 makes an ideal front end for both analog input speaker
amplifiers and headphone amplifiers with its higher voltage differential output and low noise floor.
9.2.1 High Fidelity Smartphone Application
A new trend in portable applications are termed "Hifi Smartphones". In these systems, a standard portable audio
codec continues to be used for telephony, while a separate, higher performance DAC and Headphone Amplifier
is used for music playback.
Figure 80 shows a complete circuit schematic for such a system. The digital audio is fed into a high performance
DAC. The PCM5242 is a 32-bit, stereo DAC.
Vcc+
Vcc-
1.0mF
0603
10mF/25V
10mF/25V
0603 X5R
0603 X5R
+3.3V
0.1mF/16V
TPA6120A2RGY
QFN14-RGY
PowerPAD
PCM5242RHB
QFN32-RHB
PowerPAD
10mF/10V
0603 X5R
0402 X7R
0.1mF/25V
0.1mF/25V
0.1mF/25V 0.1mF/25V
0402 X7R
0402 X7R
0402 X7R
0402 X7R
24 23 22 21 20 19 18 17
402W
402W
25
16
15
14
13
12
11
10
9
GPIO6/FLT
SCK
VCOM/DEMP
AGND
0603
0603
26
27
28
29
30
31
32
14
8
12 10
1000pF/50V
RIN+
1
2
6
7
BCK
AVDD
LIN+
LIN-
RIN-
HEADPHONE OUTPUT
3
4
5
0603 COG
402W
402W
NC
NC
NC
NC
OUTRP
OUTRN
OUTLN
OUTLP
DIN
OUTRP
OUTRN
OUTLN
OUTLP
VNEG
1
RIN-
LIN-
LIN+
0603
0603
11
NC
PCM5242RHB
QFN32-RHB
39.2W
3
2
RIGHT
LEFT
13
9
402W
402W
NC
LOUT
0805 1/8W
TPA6120A2
RIN+
0603
0603
39.2W
LRCK
ROUT
0805 1/8W
1000pF/50V
ADR1/MISO/FMT
3.5mm
402W
402W
806W
0603 COG
806W
0603
806W
0603
1
2
3
4
5
6
7
8
2.2mF/25V
0603
0603
+1.8V
0603
0805 X7R
806W
10.0kW
0402
0603
XSMT
2.2mF/25V
0805 X7R
2
1
2.2mH
TPS65135
SOFT MUTE
+3.3V
0.1mF/16V
0402 X7R
16
15
1
14
13
10
9
Vcc+
L1
L2
L2
0.1mF/16V 2.2mF/25V
+3.3V to +5/-5V POWER SUPPLY
0402 X7R
0805 X7R
L1
10mF/6.3V
VIN
EN
OUTP
OUTP
FB
+3.3V
365kW
0805 1/8W
8
+1.8V
10mF/6.3V
100LS
0603 X5R
4
7
0.1mF/16V
0402 X7R
VAUX
PGND
TPS65135
QFN16-RTE
0603 X5R
11
12
5
6
FBG
0.1mF/16V 10mF/10V
120kW
0805 1/8W
PowerPAD
3
0402 X7R
0603 X5R
PGND OUTN
GND OUTN
2
0.1mF/16V
0402 X7R
10mF/6.3V
487kW
0805 1/8W
0603 X5R
Vcc-
Figure 80. High Fidelity Smartphone Application
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Typical Application (continued)
9.2.1.1 Design Requirements
•
•
•
•
•
•
Directpath output to headphone amplifier
1VRMS output, as 2VRMS may cause hearing damage into low impedance headphones
Stereo differential inputs (DAC is differential)
Be transparent to the user. (DAC SNR and THD+N performance all the way to the headphone)
Automatic fS switching up to 384kHz
3-wire I2S source
9.2.1.2 Detailed Design Procedure
For optimal performance, the TPA6120A2 is configured for use with differential inputs, stereo use, and a gain of
1V/V.
The TPA6120A2 requires a bipolar power supply to drive a ground centered output. The application employs a
TPS65135 DC-DC converter that generates ±5V from a single 3.3V supply.
The PCM5242 DAC is configured for a 1VRMS output so that clipping is avoided should the 3.3V power supply
sag. The PCM5242 offers a ground centered output, so that no DC blocking capacitors are required between it
and the TPA6120A2. (Page 1, Register 2)
9.2.1.2.1 Initialization Script
w 98 00 01 # PCM5242 to Page 1
w 98 02 11 # PCM5242 output to 1 Vrms
w 98 00 00 # PCM5242 back to page 0
w 98 3B 66 # set auto mute time to six seconds of audio zero.
w 98 3C 01 # Left Vol register controls both
w 98 3D 4F # Change left channel volume, right will follow.
w 98 3F BB # set vol changes for every 4 samples, 0.5 sample steps.
9.2.1.3 Application Performance Plot
-20
-40
-60
-80
-100
-120
-140
-160
0
5
10
Frequency (kHz)
15
20
Figure 81. 2 FFT Plot At -60db Input
In this particular application, the TPA6120A2's performance is transparent and the performance of the system is
dictated by the PCM5242 DAC, even into a 32-Ω headphone load.
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10 Power Supply Recommendations
10.1 Power Supply Distribution and Requirements
The PCM5242 is powered through the following pins:
AVDD 3.3V
DVDD 3.3V
LDO 1.8V
Digital Core
Primary ADC’s
PLL
(DSP’s, Logic etc)
Secondary
ADC’s
Oscillator
Analog Circuits
Digital Circuits
Power Circuits
1.8V LDO
PGA’s
Clock Halt Detect
Reference
Mic Bias
Figure 82. Power Distribution Tree within PCM5242
Table 45. Power Supply Pin Descriptions
NAME
USAGE / DESCRIPTION
Analog Voltage Supply - should be 3.3V. Powers the ADC, PGA, Reference, and Secondary
ADC
AVDD
Digital Voltage Supply - This is used as the I/O voltage control and the input to the onchip
LDO.
DVDD
CPVDD
Charge Pump Voltage Supply - should be 3.3V
Output from the Onchip LDO. Should be used with a 0.1uF decoupling cap. Can be driven
(used as power input) with a 1.8V supply to bypass the onchip LDO for lower power
consumption.
LDOO
AGND
DGND
Analog Ground
Digital Ground
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10.2 Recommended Powerdown Sequence
Under certain conditions, the PCM5242 can exhibit some pop on power down. Pops are caused by the device
not having enough time to detect power loss and start the muting process.
The PCM5242 has two auto-mute functions to mute the device upon power loss (intentional or unintentional).
XSMT = 0
When the XSMT pin is pulled low, the incoming PCM data is attenuated to 0, closely followed by a hard analog
mute. This process takes 150 sample times (ts) + 0.2mS.
Because this mute time is mainly dominated by the sampling frequency, systems sampling at 192kHz will mute
much faster than a 48kHz system.
Clock Error Detect
When clock error is detected on the incoming data clock, the PCM5242 switches to an internal oscillator, and
continues to the drive the output, while attenuating the data from the last known value. Once this process is
complete, the PCM5242 outputs are hard muted to ground.
10.2.1 Planned Shutdown
These auto-muting processes can be manipulated by system designs to mute before power loss in the following
ways:
1. Assert XSMT low 150tS + 0.2mS before power is removed.
3.3V
VDD
0V
150tS + 0.2ms
High
XSMT
Low
High
2
I S Clocks
SCK, BCK, LRCK
Low
Time
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Recommended Powerdown Sequence (continued)
2. Stop I2S clocks (SCK, BCK, LRCK) 3ms before powerdown as shown below:
3.3V
VDD
0V
High
XSMT
Low
3msec
High
I2S Clocks
SCK, BCK, LRCK
Low
Time
10.2.2 Unplanned Shutdown
Many systems use a low-noise regulator to provide an AVDD 3.3V supply for the DAC. The XSMT Pin can take
advantage of such a feature to measure the pre-regulated output from the system SMPS to mute the output
before the entire SMPS discharges. Figure 83 shows how to configure such a system to use the XSMT pin. The
XSMT pin can also be used in parallel with a GPIO pin from the system microcontroller/DSP or Power Supply.
“mute” signal
MCU GPIO
GND
XSMT
110V / 220V
Linear
Regulator
PCM5xxx
Audio DAC
6V
3.3V
SMPS
10
F
GND
GND
Figure 83. Using the XSMT Pin
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10.3 External Power Sense Undervoltage Protection mode (supported only when DVDD = 3.3V)
The XSMT pin can also be used to monitor a system voltage, such as the 24VDC LCD TV backlight, or 12VDC
system supply using a voltage divider created with two resistors. (See Figure 84 )
•
If the XSMT pin makes a transition from “1” to “0” over 6ms or more, the device switches into external under-
voltage protection mode. This mode uses two trigger levels.
•
•
When the XSMT pin level reaches 2V, soft mute process begins.
When the XSMT pin level reaches 1.2V, analog mute engages, regardless of digital audio level, and analog
shutdown begins. (DAC and related circuitry powers down).
A timing diagram to show this is shown in Figure 85.
NOTE
The XSMT input pin voltage range is from -0.3V to DVDD + 0.3V.The ratio of external
resistors must produce a voltage within this input range. Any increase in power supply
(such as power supply positive noise or ripple) can pull the XSMT pin higher than
DVDD+0.3V.
For example, if the PCM5242 is monitoring a 12V input, and dividing the voltage by 4, then the voltage at XSMT
during ideal power supply conditions is 3V. A voltage spike higher than 14.4V causes a voltage greater than 3.6V
(DVDD+0.3) on the XSMT pin, potentially damaging the device.
Providing the divider is set appropriately, any DC voltage can be monitored.
System
VDD
12V
supply
7.25kW
XSMT
2.75kW
Figure 84. XSMT in External UVP Mode
Digital Attenuation Followed by Analog Mute
0.9 * DVDD
2.0 V
1.2 V
Analog Mute
XSMT
0.1 * DVDD
tf
Figure 85. XSMT Timing for Undervoltage Protection
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10.4 Power-On Reset Function
Power-On Reset, DVDD 3.3V Supply
The PCM5242 includes a power-on reset function shown in Figure 86. With VDD > 2.8V, the power-on reset
function is enabled. After the initialization period, the PCM5242 is set to its default reset state.
3.3V
2.8V
AVDD, DVDD,
CPVDD
Internal Reset
Reset Removal
Internal Reset
4 ms
I2S Clocks
SCK, BCK, LRCK
Figure 86. Power-On Reset Timing, DVDD = 3.3V
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Power-On Reset Function (continued)
Power-On Reset, DVDD 1.8V Supply
The PCM5242 includes a power-on reset function shown in Figure 87 operating at DVDD=1.8V. With AVDD
greater than approximately 2.8V, CPVDD greater than approximately 2.8V, and DVDD greater than
approximately 1.5V, the power-on reset function is enabled. After the initialization period, the PCM5242 is set to
its default reset state.
3.3V
2.8V
AVDD, CPVDD
1.8V
1.5V
DVDD, LDOO
Internal Reset
Reset Removal
Internal Reset
4 ms
I2S Clocks
SCK, BCK, LRCK
Figure 87. Power-On Reset Timing, DVDD = 1.8V
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10.5 PCM5242 Power Modes
10.5.1 Setting Digital Power Supplies and I/O Voltage Rails
The internal digital core of the PCM5242 runs from a 1.8V supply. This can be generated by the internal LDO, or
by an external 1.8V supply.
DVDD is used to set the I/O voltage, and to be used as the input to the onchip LDO that creates the 1.8V
required by the digital core.
For systems that require 3.3V IO support, but lower power consumption, DVDD should be connected to 3.3V and
LDOO can be connected to an external 1.8V source. Doing so will disable the onchip LDO.
When setting IO voltage to be 1.8V, both DVDD and LDOO must be provided with an external 1.8V supply.
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PCM5242 Power Modes (continued)
10.5.2 Power Save Modes
The PCM5242 offers two power-save modes; standby and power-down.
When a clock error (SCK, BCK, and LRCK) or clock halt is detected, the PCM5242 automatically enters standby
mode. The DAC and line driver are also powered down. The device can also be placed in standby mode via
software command.
When BCK and LRCK remain at a low level for more than 1 second, the PCM5242 automatically enters power-
down mode. Power-down mode disables the negative charge pump and bias/reference circuit, in addition to
those disabled in standby mode. The device can also be placed in power-down mode via software command.
The detection time of BCK and LRCK halt can be controlled by Page 0, Register 44, D(2:0).
When expected Audio clocks (SCK, BCK, LRCK) are applied to the PCM5242, the device starts its powerup
sequence automatically. The detection time for BCK and LRCK halt is programmable.
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PCM5242 Power Modes (continued)
10.5.3 Power Save Parameter Programming
Register
Description
Page 0, Register 2, D(4)
Page 0, Register 2, D(0)
Software standby mode command
Software power-down command
Software power-up sequence command (required after software standby or power-
down)
Page 0, Register 2, D(4) and D(0)
Page 0, Register 44, D(2:0)
Detection time of BCK and LRCK halt
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11 Layout
11.1 Layout Guidelines
•
The PCM5242 is a simple device to layout. Most engineers use a shared common ground for the entire
device. GND can be consider AGND and DGND connected.
•
Good system partitioning should keep digital clock and interface traces away from the differential analog
outputs for highest analog performance. This reduces any high speed clock return currents influencing the
analog outputs.
•
•
•
Power supply and charge pump decoupling capacitors should be placed as close as possible to the device.
The thermal pad on the underside of the package should be connected to GND.
The top layer should be used for routing signals, whilst the bottom layer can be used for GND.
MCU or Connect to
3.3V/GND
24 23 22 21 20 19 18 17
GPIO6
SCK
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VCOM
AGND
3.3V
AVDD
BCK
DIN
LINEOUTRP
LINEOUTRL
LINEOUTLR
LINEOUTLP
VNEG
PCM Data
Source
Thermal Pad
(GND)
NC
Amplifier
NC
LRCK
ADR1/MISO/GPIO1
3.3V / GND
1
2
3
4
5
6
7
8
3.3V
3.3V
Figure 88. PCM5252 Layout Example
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12 Programming and Registers Reference
12.1 Coefficient Data Formats
All mixer gain coefficients are 24-bit coefficients using a 4.20 number format. Numbers formatted as 4.20
numbers have 4 bits to the left of the binary point and 20 bits to the right of the binary point. If the most
significant bit is logic 0, the number is a positive number. If the most significant bit is a logic 1, then the number is
a negative number. In this case, every bit must be inverted, a 1 added to the result.
12.2 Power Down and Reset Behavior
Register values including those in the Coefficient Memory and Instruction Memory should remain when the
device is put into power down mode. (PG0 Reg 0x02).
Register values in the device are reset to defaults when bit 0 or 4 of (Pg0, Reg 0x01) is set to 1. Please see the
register description for more information.
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12.3 PCM5242 Register Map
In any page, register 0 is the Page Select Register. The register value selects the Register Page from 0 to 255
for next read or write command.
Table 46. Register Map Overview (continued)
Table 46. Register Map Overview
59
Auto mute time
Digital volume
Auto mute
Register
Number
Description
60 - 64
65
Page 0
75 - 79
80 - 85
86, 87
88, 89
90
Reserved
0
Page select register
Analog control register
Standby, Powerdown requests
Mute
GPIOn output selection
GPIO control
Reserved
1
2
3
DSP overflow
Sample rate status
Reserved
4
PLL Lock Flag, PLL enable
Reserved
91 - 94
95 - 107
108
5
6
SPI MISO function select
De-emphasis enable, SDOUT select
GPIO enables
Analog mute monitor
Reserved
7
109 - 118
119
8
GPIO input
9
BCK, LRCLK configuration
DSP GPIO Input
120
Auto Mute flags
Reserved
10
121
11
Reserved
Page 1
1
12
Master mode BCK, LRCLK reset
PLL clock source select
Reserved
Output amplitude type
Analog gain control
Reserved
13
2
14 - 19
20 - 24
25, 26
27
3, 4
PLL dividers
5
Undervoltage protection
Analog mute control
Analog gain boost
VCOM configuration
Reserved
6
DSP clock divider
DAC clock divider
NCP clock divider
OSR clock divider
Reserved
7
28
8, 9
29
Page 44
1
30
Coefficient memory (CRAM) control
31
Pages 44 - 52 Coefficient buffer - A (256 coeffs x 24 bits) : See
Table 47
32, 33
34
Master mode dividers
fS speed mode
Pages 62 - 70 Coefficient buffer - B (256 coeffs x 24 bits) : See
Table 48
35, 36
IDAC (number of DSP clock cycles available in
one audio frame)
Pages 152 -
186
Instruction buffer (1024 instruction x 25 bits),
I512 - I1023 are reserved.: See Table 49
37
Ignore various errors
Reserved
I2S configuration
Pages 187 -
252
Reserved
38,39
40, 41
42
Page 253
DAC data path
63, 64
Clock Flex Mode
Reserved
43
DSP program selection
Clock missing detection period
Pages 254 -
255
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The PCM5242 has a register map split into multiple pages. Pages 0 and 1 control of the DAC and other on-chip
peripherals. Pages 44 through 52 are used for Coefficient A memory, while Pages 62-70 are coefficient B
memory. Pages 152-186 contain the miniDSP instruction memory. Page 253 is where the Clock Flex Mode
register is located.
PCM5242 Register Page Structure
Page:
0
1
44-52
62-70
152-186
253
Func: Control
Analog
Control
Coeffient A
Coeffient B
Instruction
Desc: General
Analog
Control
256 24-bit coefficients,
30 coefficients per
page,
256 24-bit coefficients,
30 coefficients per
page,
1024 24-bit instructions,
30 instructions per
page,
Control and
Configuration
4 registers per
coefficient
4 registers per
coefficient
4 registers per
instruction
Table 47. Coefficient Buffer-A Map
Coeff NO
Page NO
Base Register
Base Register+0
Coef(23:16)
Coef(23:16)
..
Base Register+1
Coef(15:8)
Coef(15:8)
..
Base Register+2
Coef(7:0)
Coef(7:0)
..
Base Register+3
Reserved.
Reserved.
..
C0
44
44
..
8
C1
12
..
..
C29
C30
..
44
45
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C59
C60
..
45
46
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C89
C90
..
46
47
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C119
C120
..
47
48
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C149
C150
..
48
49
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C179
C180
..
49
50
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C209
C210
..
50
51
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C239
C240
..
51
52
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C255
52
68
Coef(23:16)
Coef(15:8)
Coef(7:0)
Reserved.
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Table 48. Coefficient Buffer-B Map
Coeff NO
C0
Page NO
62
62
..
Base Register
Base Register+0
Coef(23:16)
Coef(23:16)
..
Base Register+1
Coef(15:8)
Coef(15:8)
..
Base Register+2
Coef(7:0)
Coef(7:0)
..
Base Register+3
Reserved.
Reserved.
..
8
C1
12
..
..
C29
C30
..
62
63
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C59
C60
..
63
64
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C89
C90
..
64
65
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C119
C120
..
65
66
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C149
C150
..
66
67
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C179
C180
..
67
68
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C209
C210
..
68
69
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C239
C240
..
69
70
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C255
70
68
Coef(23:16)
Coef(15:8)
Coef(7:0)
Reserved.
minidsp
Table 49. miniDSP Instruction Map
Coeff NO
Page NO
152
152
..
Base Register
Base Register+0
Instr(31:24)
Instr(31:24)
..
Base Register+1
Instr(23:16)
Instr(23:16)
..
Base Register+2
Instr(15:8)
Instr(15:8)
..
Base Register+3
Instr(7:0)
Instr(7:0)
..
I0
8
I1
12
..
..
I29
I30
..
152
153
..
124
8
Instr(31:24)
Instr(31:24)
..
Instr(23:16)
Instr(23:16)
..
Instr(15:8)
Instr(15:8)
..
Instr(7:0)
Instr(7:0)
..
..
I59
I60
..
153
154
..
124
8
Instr(31:24)
Instr(31:24)
..
Instr(23:16)
Instr(23:16)
..
Instr(15:8)
Instr(15:8)
..
Instr(7:0)
Instr(7:0)
..
..
I89
I90
..
154
155
..
124
8
Instr(31:24)
Instr(31:24)
..
Instr(23:16)
Instr(23:16)
..
Instr(15:8)
Instr(15:8)
..
Instr(7:0)
Instr(7:0)
..
..
I119
I120
..
155
156
..
124
8
Instr(31:24)
Instr(31:24)
..
Instr(23:16)
Instr(23:16)
..
Instr(15:8)
Instr(15:8)
..
Instr(7:0)
Instr(7:0)
..
..
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Table 49. miniDSP Instruction Map (continued)
I149
I150
..
156
157
..
124
8
Instr(31:24)
Instr(31:24)
..
Instr(23:16)
Instr(23:16)
..
Instr(15:8)
Instr(15:8)
..
Instr(7:0)
Instr(7:0)
..
..
I179
I180
..
157
158
..
124
8
Instr(31:24)
Instr(31:24)
..
Instr(23:16)
Instr(23:16)
..
Instr(15:8)
Instr(15:8)
..
Instr(7:0)
Instr(7:0)
..
..
I209
I210
..
158
159
..
124
8
Instr(31:24)
Instr(31:24)
..
Instr(23:16)
Instr(23:16)
..
Instr(15:8)
Instr(15:8)
..
Instr(7:0)
Instr(7:0)
..
..
I239
I240
..
159
160
..
124
8
Instr(31:24)
Instr(31:24)
..
Instr(23:16)
Instr(23:16)
..
Instr(15:8)
Instr(15:8)
..
Instr(7:0)
Instr(7:0)
..
..
I269
I270
..
160
161
..
124
8
Instr(31:24)
Instr(31:24)
..
Instr(23:16)
Instr(23:16)
..
Instr(15:8)
Instr(15:8)
..
Instr(7:0)
Instr(7:0)
..
..
I299
I300
..
161
162
..
124
8
Instr(31:24)
Instr(31:24)
..
Instr(23:16)
Instr(23:16)
..
Instr(15:8)
Instr(15:8)
..
Instr(7:0)
Instr(7:0)
..
..
I329
I330
..
162
163
..
124
8
Instr(31:24)
Instr(31:24)
..
Instr(23:16)
Instr(23:16)
..
Instr(15:8)
Instr(15:8)
..
Instr(7:0)
Instr(7:0)
..
..
I359
I360
..
163
164
..
124
8
Instr(31:24)
Instr(31:24)
..
Instr(23:16)
Instr(23:16)
..
Instr(15:8)
Instr(15:8)
..
Instr(7:0)
Instr(7:0)
..
..
I389
I390
..
164
165
..
124
8
Instr(31:24)
Instr(31:24)
..
Instr(23:16)
Instr(23:16)
..
Instr(15:8)
Instr(15:8)
..
Instr(7:0)
Instr(7:0)
..
..
I419
I420
..
165
166
..
124
8
Instr(31:24)
Instr(31:24)
..
Instr(23:16)
Instr(23:16)
..
Instr(15:8)
Instr(15:8)
..
Instr(7:0)
Instr(7:0)
..
..
I449
I450
..
166
167
..
124
8
Instr(31:24)
Instr(31:24)
..
Instr(23:16)
Instr(23:16)
..
Instr(15:8)
Instr(15:8)
..
Instr(7:0)
Instr(7:0)
..
..
I479
I480
..
167
168
..
124
8
Instr(31:24)
Instr(31:24)
..
Instr(23:16)
Instr(23:16)
..
Instr(15:8)
Instr(15:8)
..
Instr(7:0)
Instr(7:0)
..
..
I509
I510
I511
..
168
169
169
..
124
8
Instr(31:24)
Instr(31:24)
Instr(31:24)
..
Instr(23:16)
Instr(23:16)
Instr(23:16)
..
Instr(15:8)
Instr(15:8)
Instr(15:8)
..
Instr(7:0)
Instr(7:0)
Instr(7:0)
..
12
..
I539
I540
..
169
170
..
124
8
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
..
I569
I570
..
170
171
..
124
8
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
..
I599
I600
171
172
124
8
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
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Table 49. miniDSP Instruction Map (continued)
..
..
..
..
..
..
..
I629
I630
..
172
173
..
124
8
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
..
I659
I660
..
173
174
..
124
8
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
..
I689
I690
..
174
175
..
124
8
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
..
I719
I720
..
175
176
..
124
8
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
..
I749
I750
..
176
177
..
124
8
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
..
I779
I780
..
177
178
..
124
8
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
..
I809
I810
..
178
179
..
124
8
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
..
I839
I840
..
179
180
..
124
8
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
..
I869
I870
..
180
181
..
124
8
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
..
I899
I900
..
181
182
..
124
8
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
..
I929
I930
..
182
183
..
124
8
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
..
I959
I960
..
183
184
..
124
8
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
..
I989
I990
..
184
185
..
124
8
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
..
I1019
I1020
..
185
186
..
124
8
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
Reserved.
Reserved.
..
..
I1023
186
20
Reserved.
Reserved.
Reserved.
Reserved.
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12.3.1 Detailed Register Descriptions
12.3.1.1 Register Map Summary
Register Map Summary
Page 0
Dec
1
Hex
01
02
03
04
06
07
08
09
0A
0C
0D
0E
12
13
14
15
16
17
18
1B
1C
1D
1E
20
21
22
23
24
25
28
29
2A
2B
2C
3B
3C
3D
3E
3F
40
41
50
51
b7
RSV
b6
b5
RSV
b4
b3
RSV
b2
b1
b0
RSV
RSTM
RQST
RQML
PLCK
RSV
RSV
RSTR
2
RSV
RSV
RSV
RSV
RSV
RSV
RQPD
RQMR
PLLE
3
RSV
RSV
RSV
RSV
RSV
RSV
4
RSV
RSV
RSV
RSV
RSV
RSV
6
RSV
RSV
RSV
RSV
RSV
RSV
FSMI1
RSV
FSMI0
SDSL
7
RSV
RSV
RSV
DEMP
G5OE
BCKO
DSPG4
RSV
RSV
RSV
8
RSV
RSV
G6OE
BCKP
DSPG5
RSV
G4OE
RSV
G3OE
RSV
G2OE
RSV
G1OE
LRKO
9
RSV
RSV
10
12
13
14
18
19
20
21
22
23
24
27
28
29
30
32
33
34
35
36
37
40
41
42
43
44
59
60
61
62
63
64
65
80
81
DSPG7
RSV
DSPG6
RSV
DSPG3
RSV
DSPG2
RSV
DSPG1
RBCK
RSV
DSPG0
RLRK
RSV
SREF2
SDAC2
RSV
SREF1
SDAC1
RSV
SREF0
SDAC0
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
GREF2
RSV
GREF1
RSV
GREF0
RQSY
PPDV0
PJDV0
PDDV8
PDDV0
PRDV0
DDSP0
DDAC0
DNCP0
DOSR0
DBCK0
DLRK0
FSSP0
IDAC8
IDAC0
IPLK
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
PPDV3
PJDV3
PDDV11
PDDV3
PRDV3
DDSP3
DDAC3
DNCP3
DOSR3
DBCK3
DLRK3
RSV
PPDV2
PJDV2
PDDV10
PDDV2
PRDV2
DDSP2
DDAC2
DNCP2
DOSR2
DBCK2
DLRK2
RSV
PPDV1
PJDV1
PDDV9
PDDV1
PRDV1
DDSP1
DDAC1
DNCP1
DOSR1
DBCK1
DLRK1
FSSP1
IDAC9
IDAC1
DCAS
ALEN1
AOFS1
AUPR1
PSEL1
CMDP1
AMTR1
PCTL1
VOLL1
VOLR1
VNUS1
RSV
RSV
RSV
PJDV5
PDDV13
PDDV5
RSV
PJDV4
PDDV12
PDDV4
RSV
RSV
RSV
PDDV7
RSV
PDDV6
RSV
RSV
DDSP6
DDAC6
DNCP6
DOSR6
DBCK6
DLRK6
RSV
DDSP5
DDAC5
DNCP5
DOSR5
DBCK5
DLRK5
RSV
DDSP4
DDAC4
DNCP4
DOSR4
DBCK4
DLRK4
I16E
RSV
RSV
RSV
RSV
DLRK7
RSV
IDAC15
IDAC7
RSV
IDAC14
IDAC6
IDFS
IDAC13
IDAC5
IDBK
IDAC12
IDAC4
IDSK
IDAC11
IDAC3
IDCH
RSV
IDAC10
IDAC2
IDCM
RSV
RSV
RSV
AFMT1
AOFS5
AUPL1
RSV
AFMT0
AOFS4
AUPL0
PSEL4
RSV
ALEN0
AOFS0
AUPR0
PSEL0
CMDP0
AMTR0
PCTL0
VOLL0
VOLR0
VNUS0
RSV
AOFS7
RSV
AOFS6
RSV
AOFS3
RSV
AOFS2
RSV
RSV
RSV
PSEL3
RSV
PSEL2
CMDP2
AMTR2
RSV
RSV
RSV
RSV
RSV
AMTL2
RSV
AMTL1
RSV
AMTL0
RSV
RSV
RSV
RSV
VOLL7
VOLR7
VNDF1
VEDF1
RSV
VOLL6
VOLR6
VNDF0
VEDF0
RSV
VOLL5
VOLR5
VNDS1
VEDS1
RSV
VOLL4
VOLR4
VNDS0
VEDS0
RSV
VOLL3
VOLR3
VNUF1
RSV
VOLL2
VOLR2
VNUF0
RSV
RSV
ACTL2
G1SL2
G2SL2
AMLE1
G1SL1
G2SL1
AMRE0
G1SL0
G2SL0
RSV
RSV
RSV
G1SL4
G2SL4
G1SL3
G2SL3
RSV
RSV
RSV
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Register Map Summary (continued)
82
83
52
53
54
55
56
57
5A
5B
5C
5D
5E
5F
6C
6D
72
73
76
77
78
79
7A
7B
7C
7D
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
DTBR7
RSV
RSV
RSV
RSV
RSV
RSV
BOTM
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
G3SL4
G4SL4
G5SL4
G6SL4
GOUT4
GINV4
L1OV
DTFS0
RSV
G3SL3
G4SL3
G5SL3
G6SL3
GOUT3
GINV3
R1OV
DTSR3
RSV
G3SL2
G4SL2
G5SL2
G6SL2
GOUT2
GINV2
L2OV
DTSR2
RSV
G3SL1
G4SL1
G5SL1
G6SL1
GOUT1
GINV1
R2OV
DTSR1
RSV
G3SL0
G4SL0
G5SL0
G6SL0
GOUT0
GINV0
SFOV
84
RSV
RSV
85
RSV
RSV
86
RSV
GOUT5
GINV5
RSV
87
RSV
90
RSV
91
DTFS2
RSV
DTFS1
RSV
DTSR0
DTBR8
DTBR0
fSval
92
93
DTBR6
CDST
RSV
DTBR5
PLL-L
RSV
DTBR4
LrckBck
LTSH
RSV
DTBR3
fS-SCKr
RSV
DTBR2
SCKval
CKMF
RSV
DTBR1
BCKval
CSRF
AMLM
RSV
94
95
CERF
108
109
114
115
118
119
120
121
122
123
124
125
Page 1
Dec
1
RSV
RSV
RSV
AMRM
SHTM
MTST0
FSMM0
PSTM0
RSV
RSV
RSV
SDTM
RSV
RSV
RSV
RSV
RSV
RSV
RSV
MTST1
FSMM1
PSTM1
GPIN1
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
PSTM3
GPIN3
RSV
PSTM2
GPIN2
RSV
RSV
GPIN5
RSV
GPIN4
AMFL
RSV
RSV
AMFR
DAMD
EIFM
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
G1MC2
G3MC2
G5MC2
G1MC1
G3MC1
G5MC1
G1MC0
G3MC0
G5MC0
RSV
G2MC2
G4MC2
G6MC2
G2MC1
G4MC1
G6MC1
G2MC0
G4MC0
G6MC0
RSV
RSV
Hex
01
02
05
06
07
08
09
b7
b6
b5
b4
b3
b2
b1
RSV
RSV
UEPD
RSV
RSV
RSV
RSV
b0
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
LAGN
RSV
RSV
AGBL
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
OSEL
RAGN
UIPD
2
5
6
AMCT
AGBR
RCMF
VCPD
7
8
9
Page 44
Dec
1
Hex
01
b7
b6
b5
b4
b3
b2
b1
b0
RSV
RSV
RSV
RSV
ACRM
AMDC
ACRS
ACSW
Page 253
Dec
63
Hex
3F
b7
b6
b5
b4
b3
b2
b1
b0
PLLFLEX17 PLLFLEX16 PLLFLEX15 PLLFLEX14 PLLFLEX13 PLLFLEX12 PLLFLEX11 PLLFLEX10
PLLFLEX27 PLLFLEX26 PLLFLEX25 PLLFLEX24 PLLFLEX23 PLLFLEX22 PLLFLEX21 PLLFLEX20
64
40
12.3.1.2 Page 0 Registers
Page 0 / Register 1
Dec
1
Hex
01
b7
b6
b5
b4
RSTM
0
b3
b2
b1
b0
RSTR
0
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
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RSV
Reserved
Reserved. Do not access.
Reset Modules
RSTM
This bit resets the interpolation filter and the DAC modules. Since the DSP is also reset, the coeffient RAM
content will also be cleared by the DSP. This bit is auto cleared and can be set only in standby mode.
Default value: 0
0: Normal
1: Reset modules
Reset Registers
RSTR
This bit resets the mode registers back to their initial values. The RAM content is not cleared, but the execution
source will be back to ROM. This bit is auto cleared and must be set only when the DAC is in standby mode
(resetting registers when the DAC is running is prohibited and not supported).
Default value: 0
0: Normal
1: Reset mode registers
Page 0 / Register 2
Dec
Hex
02
b7
b6
b5
b4
RQST
0
b3
b2
b1
b0
RQPD
0
2
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
RQST
Standby Request
When this bit is set, the DAC will be forced into a system standby mode, which is also the mode the system
enters in the case of clock errors. In this mode, most subsystems will be powered down but the charge pump
and digital power supply.
Default value: 0
0: Normal operation
1: Standby mode
RQPD
Powerdown Request
When this bit is set, the DAC will be forced into powerdown mode, in which the power consumption would be
minimum as the charge pump is also powered down. However, it will take longer to restart from this mode. This
mode has higher precedence than the standby mode, i.e. setting this bit along with bit 4 for standby mode will
result in the DAC going into powerdown mode.
Default value: 0
0: Normal operation
1: Powerdown mode
Page 0 / Register 3
Dec
Hex
03
b7
b6
b5
b4
RQML
0
b3
b2
b1
b0
RQMR
0
3
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
RQML
Mute Left Channel
This bit issues soft mute request for the left channel. The volume will be smoothly ramped down/up to avoid
pop/click noise.
Default value: 0
0: Normal volume
1: Mute
RQMR
Mute Right Channel
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This bit issues soft mute request for the right channel. The volume will be smoothly ramped down/up to avoid
pop/click noise.
Default value: 0
0: Normal volume
1: Mute
Page 0 / Register 4
Dec
4
Hex
04
b7
b6
b5
b4
b3
b2
b1
b0
PLLE
1
RSV
RSV
RSV
PLCK
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
PLCK
PLL Lock Flag (Read Only)
This bit indicates whether the PLL is locked or not. When the PLL is disabled this bit always shows that the
PLL is not locked.
0: The PLL is locked
1: The PLL is not locked
PLL Enable
PLLE
This bit enables or disables the internal PLL. When PLL is disabled, the master clock will be switched to the
SCK.
Default value: 1
0: Disable PLL
1: Enable PLL
Page 0 / Register 6
Dec
Hex
06
b7
b6
b5
b4
b3
b2
b1
FSMI1
0
b0
FSMI0
0
6
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
FSMI[1:0]
SPI MISO function sel
These bits select the function of the SPI_MISO pin when in SPI mode. If the pin is set as GPIO, register
readout via SPI is not possible.
Default value: 00
00: SPI_MISO
01: GPIO1
Others: Reserved (Do not set)
Page 0 / Register 7
Dec
7
Hex
07
b7
b6
b5
b4
DEMP
0
b3
b2
b1
b0
SDSL
0
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
DEMP
De-Emphasis Enable
This bit enables or disables the de-emphasis filter. The default coefficients are for 44.1kHz sampling rate, but
can be changed by reprogramming the appropriate coeffients in RAM.
Default value: 0
0: De-emphasis filter is disabled
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1: De-emphasis filter is enabled
SDOUT Select
SDSL
This bit selects what is being output as SDOUT via GPIO pins.
Default value: 0
0: SDOUT is the DSP output (post-processing)
1: SDOUT is the DSP input (pre-processing)
Page 0 / Register 8
Dec
Hex
08
b7
b6
b5
G6OE
0
b4
G5OE
0
b3
G4OE
0
b2
G3OE
0
b1
G2OE
0
b0
G1OE
0
8
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
G6OE
G5OE
G4OE
G3OE
G2OE
G1OE
GPIO6 Output Enable
This bit sets the direction of the GPIO6 pin
Default value: 0
0: GPIO6 is input
1: GPIO6 is output
GPIO5 Output Enable
This bit sets the direction of the GPIO5 pin
Default value: 0
0: GPIO5 is input
1: GPIO5 is output
GPIO4 Output Enable
This bit sets the direction of the GPIO4 pin
Default value: 0
0: GPIO4 is input
1: GPIO4 is output
GPIO3 Output Enable
This bit sets the direction of the GPIO3 pin
Default value: 0
0: GPIO3 is input
1: GPIO3 is output
GPIO2 Output Enable
This bit sets the direction of the GPIO2 pin
Default value: 0
0: GPIO2 is input
1: GPIO2 is output
GPIO1 Output Enable
This bit sets the direction of the GPIO1 pin
Default value: 0
0: GPIO1 is input
1: GPIO1 is output
Page 0 / Register 9
Dec
Hex
09
b7
b6
b5
BCKP
0
b4
BCKO
0
b3
b2
b1
b0
LRKO
0
9
RSV
RSV
RSV
RSV
RSV
Reset Value
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RSV
SLASE12A –JULY 2014–REVISED OCTOBER 2014
Reserved
Reserved. Do not access.
BCK Polarity
BCKP
This bit sets the inverted BCK mode. In inverted BCK mode, the DAC assumes that the LRCK and DIN edges
are aligned to the rising edge of the BCK. Normally they are assumed to be aligned to the falling edge of the
BCK.
Default value: 0
0: Normal BCK mode
1: Inverted BCK mode
BCK Output Enable
BCKO
This bit sets the BCK pin direction to output for I2S master mode operation. In I2S master mode the PCM5xxx
outputs the reference BCK and LRCK, and the external source device provides the DIN according to these
clocks. Use Page 0 / Register 32 to program the division factor of the SCK to yield the desired BCK rate
(normally 64FS)
Default value: 0
0: BCK is input (I2S slave mode)
1: BCK is output (I2S master mode)
LRCLK Output Enable
LRKO
This bit sets the LRCK pin direction to output for I2S master mode operation. In I2S master mode the PCM5xxx
outputs the reference BCK and LRCK, and the external source device provides the DIN according to these
clocks. Use Page 0 / Register 33 to program the division factor of the BCK to yield 1FS for LRCK.
Default value: 0
0: LRCK is input (I2S slave mode)
1: LRCK is output (I2S master mode)
Page 0 / Register 10
Dec
10
Hex
0A
b7
DSPG7
0
b6
DSPG6
0
b5
DSPG5
0
b4
DSPG4
0
b3
DSPG3
0
b2
DSPG2
0
b1
DSPG1
0
b0
DSPG0
0
Reset Value
DSPG[7:0]
DSP GPIO Input
The DSP accepts a 24-bit external control signals input. The value set in this register will go to bit 16:8 of this
external input.
Default value: 00000000
Page 0 / Register 12
Dec
12
Hex
0C
b7
b6
b5
b4
b3
b2
b1
RBCK
0
b0
RLRK
0
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
Master Mode BCK Divider Reset
RBCK
This bit, when set to 0, will reset the SCK divider to generate BCK clock for I2S master mode. To use I2S
master mode, the divider must be enabled and programmed properly.
Default value: 0
0: Master mode BCK clock divider is reset
1: Master mode BCK clock divider is functional
Master Mode LRCK Divider Reset
RLRK
This bit, when set to 0, will reset the BCK divider to generate LRCK clock for I2S master mode. To use I2S
master mode, the divider must be enabled and programmed properly.
Default value: 0
0: Master mode LRCK clock divider is reset
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1: Master mode LRCK clock divider is functional
Page 0 / Register 13
Dec
13
Hex
0D
b7
b6
SREF2
0
b5
SREF1
0
b4
SREF0
0
b3
b2
b1
b0
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
SREF[2:0]
PLL Reference
This bit select the source clock for internal PLL. This bit is ignored and overriden in clock auto set mode.
Default value: 000
000: The PLL reference clock is SCK
001: The PLL reference clock is BCK
010: Reserved
011: The PLL reference clock is GPIO (selected using Page 0 / Register 18)
others: Reserved (PLL reference is muted)
PLL Reference
SREF
Default value: 0
Page 0 / Register 14
Dec
14
Hex
0E
b7
b6
SDAC2
0
b5
SDAC1
0
b4
SDAC0
0
b3
b2
b1
b0
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
SDAC[2:0]
DAC clock source
These bits select the source clock for DAC clock divider.
Default value: 000
This Register requires use of the Clock Flex Register
000: Master clock (PLL/SCK and OSC auto-select)
001: PLL clock
010: Reserved
011: SCK clock
100: BCK clock
others: Reserved (muted)
Page 0 / Register 18
Dec
18
Hex
12
b7
b6
b5
b4
b3
b2
GREF2
0
b1
GREF1
0
b0
GREF0
0
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
GPIO Source for PLL reference clk
GREF[2:0]
These bits select the GPIO pins as clock input source when GPIO is selected as the PLL reference clock
source.
Default value: 000
This register requires use of the Clock Flex Register.000: GPIO1
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001: GPIO2
010: GPIO3
011: GPIO4
100: GPIO5
101: GPIO6
others: Reserved (muted)
Page 0 / Register 19
Dec
19
Hex
13
b7
b6
b5
b4
b3
b2
b1
b0
RQSY
0
RSV
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
RQSY
Sync request
This bit, when set to 1 will issue the clock resynchronization by synchronously resets the DAC, CP and OSR
clocks. The actual clock resynchronization takes place when this bit is set back to 0, where the DAC, CP and
OSR clocks are resumed at the beginning of the audio frame.
Default value: 0
0: Resume DAC, CP and OSR clocks synchronized to the beginning of audio frame
1: Halt DAC, CP and OSR clocks as the beginning of resynchronization process
Page 0 / Register 20
Dec
20
Hex
14
b7
b6
b5
b4
b3
PPDV3
0
b2
PPDV2
0
b1
PPDV1
0
b0
PPDV0
0
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
PPDV[3:0]
PLL P
These bits set the PLL divider P factor. These bits are ignored in clock auto set mode.
Default value: 0000
0000: P=1
0001: P=2
...
1110: P=15
1111: Prohibited (do not set this value)
Page 0 / Register 21
Dec
21
Hex
15
b7
b6
b5
PJDV5
0
b4
PJDV4
0
b3
PJDV3
0
b2
PJDV2
0
b1
PJDV1
0
b0
PJDV0
0
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
PJDV[5:0]
PLL J
These bits set the J part of the overall PLL multiplication factor J.D * R. These bits are ignored in clock auto set
mode.
Default value: 000000
000000: Prohibited (do not set this value)
000001: J=1
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000010: J=2
...
111111: J=63
Page 0 / Register 22
Dec
22
Hex
16
b7
b6
b5
PDDV13
0
b4
PDDV12
0
b3
PDDV11
0
b2
PDDV10
0
b1
PDDV9
0
b0
PDDV8
0
RSV
RSV
Reset Value
Page 0 / Register 23
23
17
PDDV7
0
PDDV6
0
PDDV5
0
PDDV4
0
PDDV3
0
PDDV2
0
PDDV1
0
PDDV0
0
Reset Value
RSV
Reserved
Reserved. Do not access.
PDDV[13:0]
PLL D (MSB)
These bits set the D part of the overall PLL multiplication factor J.D * R. These bits are ignored in clock auto
set mode.
Default value: 00000000000000
0 (in decimal): D=0000
1 (in decimal): D=0001
...
9999 (in decimal): D=9999
others: Prohibited (do not set)
Page 0 / Register 24
Dec
24
Hex
18
b7
b6
b5
b4
b3
PRDV3
0
b2
PRDV2
0
b1
PRDV1
0
b0
PRDV0
0
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
PRDV[3:0]
PLL R
These bits set the R part of the overall PLL multiplication factor J.D * R. These bits are ignored in clock auto
set mode.
Default value: 0000
0000: R=1
0001: R=2
...
1111: R=16
Page 0 / Register 27
Dec
27
Hex
1B
b7
b6
DDSP6
0
b5
DDSP5
0
b4
DDSP4
0
b3
DDSP3
0
b2
DDSP2
0
b1
DDSP1
0
b0
DDSP0
0
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
DDSP[6:0]
DSP Clock Divider
These bits set the source clock divider value for the DSP clock. These bits are ignored in clock auto set mode.
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Default value: 0000000
0000000: Divide by 1
0000001: Divide by 2
...
1111111: Divide by 128
Page 0 / Register 28
Dec
28
Hex
1C
b7
b6
DDAC6
0
b5
DDAC5
0
b4
DDAC4
0
b3
DDAC3
0
b2
DDAC2
0
b1
DDAC1
0
b0
DDAC0
0
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
DDAC[6:0]
DAC Clock Divider
These bits set the source clock divider value for the DAC clock. These bits are ignored in clock auto set mode.
Default value: 0000000
0000000: Divide by 1
0000001: Divide by 2
...
1111111: Divide by 128
Page 0 / Register 29
Dec
29
Hex
1D
b7
b6
DNCP6
0
b5
DNCP5
0
b4
DNCP4
0
b3
DNCP3
0
b2
DNCP2
0
b1
DNCP1
0
b0
DNCP0
0
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
DNCP[6:0]
NCP Clock Divider
These bits set the source clock divider value for the CP clock. These bits are ignored in clock auto set mode.
Default value: 0000000
0000000: Divide by 1
0000001: Divide by 2
...
1111111: Divide by 128
Page 0 / Register 30
Dec
30
Hex
1E
b7
b6
DOSR6
0
b5
DOSR5
0
b4
DOSR4
0
b3
DOSR3
0
b2
DOSR2
0
b1
DOSR1
0
b0
DOSR0
0
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
DOSR[6:0]
OSR Clock Divider
These bits set the source clock divider value for the OSR clock. These bits are ignored in clock auto set mode.
Default value: 0000000
0000000: Divide by 1
0000001: Divide by 2
...
1111111: Divide by 128
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Page 0 / Register 32
Dec
32
Hex
20
b7
b6
DBCK6
0
b5
DBCK5
0
b4
DBCK4
0
b3
DBCK3
0
b2
DBCK2
0
b1
DBCK1
0
b0
DBCK0
0
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
DBCK[6:0]
Master Mode BCK Divider
These bits set the SCK divider value to generate I2S master BCK clock.
Default value: 0000000
0000000: Divide by 1
0000001: Divide by 2
...
1111111: Divide by 128
Page 0 / Register 33
Dec
33
Hex
21
b7
DLRK7
0
b6
DLRK6
0
b5
DLRK5
0
b4
DLRK4
0
b3
DLRK3
0
b2
DLRK2
0
b1
DLRK1
0
b0
DLRK0
0
Reset Value
DLRK[7:0]
Master Mode LRCK Divider
These bits set the I2S master BCK clock divider value to generate I2S master LRCK clock.
Default value: 00000000
00000000: Divide by 1
00000001: Divide by 2
...
11111111: Divide by 256
Page 0 / Register 34
Dec
34
Hex
22
b7
b6
b5
b4
I16E
0
b3
b2
b1
FSSP1
0
b0
FSSP0
0
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
I16E
Reserved
Reserved. Do not access.
16x Interpolation
This bit enables or disables the 16x interpolation mode
Default value: 0
0: 8x interpolation
1: 16x interpolation
FSSP[1:0]
FS Speed Mode
These bits select the FS operation mode, which must be set according to the current audio sampling rate.
These bits are ignored in clock auto set mode.
Default value: 00
00: Single speed (FS ≤ 48 kHz)
01: Double speed (48 kHz < FS ≤ 96 kHz)
10: Quad speed (96 kHz < FS ≤ 192 kHz)
11: Octal speed (192 kHz < FS ≤ 384 kHz)
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Page 0 / Register 35
Dec
35
Hex
23
b7
IDAC15
0
b6
IDAC14
0
b5
IDAC13
0
b4
IDAC12
0
b3
IDAC11
0
b2
IDAC10
0
b1
IDAC9
0
b0
IDAC8
1
Reset Value
Page 0 / Register 36
36
24
IDAC7
0
IDAC6
0
IDAC5
0
IDAC4
0
IDAC3
0
IDAC2
0
IDAC1
0
IDAC0
0
Reset Value
IDAC[15:0]
IDAC (MSB)
These bits specify the number of DSP clock cycles available in one audio frame. The value should match the
DSP clock FS ratio. These bits are ignored in clock auto set mode.
Default value: 0000000100000000
Page 0 / Register 37
Dec
37
Hex
25
b7
b6
IDFS
0
b5
IDBK
0
b4
IDSK
0
b3
IDCH
0
b2
IDCM
0
b1
DCAS
0
b0
IPLK
0
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
IDFS
Ignore FS Detection
This bit controls whether to ignore the FS detection. When ignored, FS error will not cause a clock error.
Default value: 0
0: Regard FS detection
1: Ignore FS detection
IDBK
IDSK
IDCH
IDCM
Ignore BCK Detection
This bit controls whether to ignore the BCK detection against LRCK. The BCK must be stable between 32FS
and 256FS inclusive or an error will be reported. When ignored, a BCK error will not cause a clock error.
Default value: 0
0: Regard BCK detection
1: Ignore BCK detection
Ignore SCK Detection
This bit controls whether to ignore the SCK detection against LRCK. Only some certain SCK ratios within some
error margin are allowed. When ignored, an SCK error will not cause a clock error.
Default value: 0
0: Regard SCK detection
1: Ignore SCK detection
Ignore Clock Halt Detection
This bit controls whether to ignore the SCK halt (static or frequency is lower than acceptable) detection. When
ignored an SCK halt will not cause a clock error.
Default value: 0
0: Regard SCK halt detection
1: Ignore SCK halt detection
Ignore LRCK/BCK Missing Detection
This bit controls whether to ignore the LRCK/BCK missing detection. The LRCK/BCK need to be in low state
(not only static) to be deemed missing. When ignored an LRCK/BCK missing will not cause the DAC go into
powerdown mode.
Default value: 0
0: Regard LRCK/BCK missing detection
1: Ignore LRCK/BCK missing detection
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DCAS
Disable Clock Divider Autoset
This bit enables or disables the clock auto set mode. When dealing with uncommon audio clock configuration,
the auto set mode must be disabled and all clock dividers must be set manually. Addtionally, some clock
detectors might also need to be disabled. The clock autoset feature will not work with PLL enabled in VCOM
mode. In this case this feature has to be disabled and the clock dividers must be set manually.
Default value: 0
0: Enable clock auto set
1: Disable clock auto set
Ignore PLL Lock Detection
IPLK
This bit controls whether to ignore the PLL lock detection. When ignored, PLL unlocks will not cause a clock
error. The PLL lock flag at Page 0 / Register 4, bit 4 is always correct regardless of this bit.
Default value: 0
0: PLL unlocks raise clock error
1: PLL unlocks are ignored
Page 0 / Register 40
Dec
40
Hex
28
b7
b6
b5
AFMT1
0
b4
AFMT0
0
b3
b2
b1
ALEN1
1
b0
ALEN0
0
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
AFMT[1:0]
I2S Data Format
These bits control both input and output audio interface formats for DAC operation.
Default value: 00
00: I2S
01: TDM/DSP
10: RTJ
11: LTJ
ALEN[1:0]
I2S Word Length
These bits control both input and output audio interface sample word lengths for DAC operation.
Default value: 10
00: 16 bits
01: 20 bits
10: 24 bits
11: 32 bits
Page 0 / Register 41
Dec
41
Hex
29
b7
AOFS7
0
b6
AOFS6
0
b5
AOFS5
0
b4
AOFS4
0
b3
AOFS3
0
b2
AOFS2
0
b1
AOFS1
0
b0
AOFS0
0
Reset Value
AOFS[7:0]
I2S Shift
These bits control the offset of audio data in the audio frame for both input and output. The offset is defined as
the number of BCK from the starting (MSB) of audio frame to the starting of the desired audio sample.
Default value: 00000000
00000000: offset = 0 BCK (no offset)
00000001: ofsset = 1 BCK
00000010: offset = 2 BCKs
. . .
11111111: offset = 256 BCKs
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Page 0 / Register 42
Dec
42
Hex
2A
b7
b6
b5
AUPL1
0
b4
AUPL0
1
b3
b2
b1
AUPR1
0
b0
AUPR0
1
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
AUPL[1:0]
Left DAC Data Path
These bits control the left channel audio data path connection.
Default value: 01
00: Zero data (mute)
01: Left channel data
10: Right channel data
11: Reserved (do not set)
Right DAC Data Path
AUPR[1:0]
These bits control the right channel audio data path connection.
Default value: 01
00: Zero data (mute)
01: Right channel data
10: Left channel data
11: Reserved (do not set)
Page 0 / Register 43
Dec
43
Hex
2B
b7
b6
b5
b4
PSEL4
0
b3
PSEL3
0
b2
PSEL2
0
b1
PSEL1
0
b0
PSEL0
1
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
PSEL[4:0]
DSP Program Selection
These bits select the DSP program to use for audio processing.
Default value: 00001
00000: Reserved (do not set)
00001: 8x/4x/2x FIR interpolation filter with de-emphasis
00010: 8x/4x/2x Low latency IIR interpolation filter with de-emphasis
00011: High attenuation x8/x4/x2 interpolation filter with de-emphasis
00100: Reserved
00101: Fixed process flow with configurable parameters
00110: Reserved (do not set)
00111: 8x Ringing-less low latency FIR interpolation filter without de-emphasis
11111: User program in RAM
others: Reserved (do not set)
Page 0 / Register 44
Dec
44
Hex
2C
b7
b6
b5
b4
b3
b2
CMDP2
0
b1
CMDP1
0
b0
CMDP0
0
RSV
RSV
RSV
RSV
RSV
Reset Value
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RSV
Reserved
Reserved. Do not access.
Clock Missing Detection Period
CMDP[2:0]
These bits set how long both BCK and LRCK keep low before the audio clocks deemed missing and the DAC
transitions to powerdown mode.
Default value: 000
000: about 1 second
001: about 2 seconds
010: about 3 seconds
...
111: about 8 seconds
Page 0 / Register 59
Dec
59
Hex
3B
b7
b6
AMTL2
0
b5
AMTL1
0
b4
AMTL0
0
b3
b2
AMTR2
0
b1
AMTR1
0
b0
AMTR0
0
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
Auto Mute Time for Left Channel
AMTL[2:0]
These bits specify the length of consecutive zero samples at left channel before the channel can be auto
muted. The times shown are for 48 kHz sampling rate and will scale with other rates.
Default value: 000
000: 21 ms
001: 106 ms
010: 213 ms
011: 533 ms
100: 1.07 sec
101: 2.13 sec
110: 5.33 sec
111: 10.66 sec
AMTR[2:0]
Auto Mute Time for Right Channel
These bits specify the length of consecutive zero samples at right channel before the channel can be auto
muted. The times shown are for 48 kHz sampling rate and will scale with other rates.
Default value: 000
000: 21 ms
001: 106 ms
010: 213 ms
011: 533 ms
100: 1.07 sec
101: 2.13 sec
110: 5.33 sec
111: 10.66 sec
Page 0 / Register 60
Dec
60
Hex
3C
b7
b6
b5
b4
b3
b2
b1
PCTL1
0
b0
PCTL0
0
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
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RSV
SLASE12A –JULY 2014–REVISED OCTOBER 2014
Reserved
Reserved. Do not access.
Digital Volume Control
These bits control the behavior of the digital volume.
Default value: 00
PCTL[1:0]
00: The volume for Left and right channels are independent
01: Right channel volume follows left channel setting
10: Left channel volume follows right channel setting
11: Reserved (The volume for Left and right channels are independent)
Page 0 / Register 61
Dec
61
Hex
3D
b7
VOLL7
0
b6
VOLL6
0
b5
VOLL5
1
b4
VOLL4
1
b3
VOLL3
0
b2
VOLL2
0
b1
VOLL1
0
b0
VOLL0
0
Reset Value
VOLL[7:0]
Left Digital Volume
These bits control the left channel digital volume. The digital volume is 24 dB to -103 dB in -0.5 dB step.
Default value: 00110000
00000000: +24.0 dB
00000001: +23.5 dB
. . .
00101111: +0.5 dB
00110000: 0.0 dB
00110001: -0.5 dB
...
11111110: -103 dB
11111111: Mute
Page 0 / Register 62
Dec
62
Hex
3E
b7
VOLR7
0
b6
VOLR6
0
b5
VOLR5
1
b4
VOLR4
1
b3
VOLR3
0
b2
VOLR2
0
b1
VOLR1
0
b0
VOLR0
0
Reset Value
VOLR[7:0]
Right Digital Volume
These bits control the right channel digital volume. The digital volume is 24 dB to -103 dB in -0.5 dB step.
Default value: 00110000
00000000: +24.0 dB
00000001: +23.5 dB
. . .
00101111: +0.5 dB
00110000: 0.0 dB
00110001: -0.5 dB
...
11111110: -103 dB
11111111: Mute
Page 0 / Register 63
Dec
63
Hex
3F
b7
VNDF1
0
b6
VNDF0
0
b5
VNDS1
1
b4
VNDS0
0
b3
VNUF1
0
b2
VNUF0
0
b1
VNUS1
1
b0
VNUS0
0
Reset Value
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VNDF[1:0]
VNDS[1:0]
VNUF[1:0]
VNUS[1:0]
Digital Volume Normal Ramp Down Frequency
These bits control the frequency of the digital volume updates when the volume is ramping down. The setting
here is applied to soft mute request, asserted by XSMUTE pin or Page 0 / Register 3.
Default value: 00
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
Digital Volume Normal Ramp Down Step
These bits control the step of the digital volume updates when the volume is ramping down. The setting here is
applied to soft mute request, asserted by XSMUTE pin or Page 0 / Register 3.
Default value: 10
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
Digital Volume Normal Ramp Up Frequency
These bits control the frequency of the digital volume updates when the volume is ramping up. The setting here
is applied to soft unmute request, asserted by XSMUTE pin or Page 0 / Register 3.
Default value: 00
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly restore the volume (Instant unmute)
Digital Volume Normal Ramp Up Step
These bits control the step of the digital volume updates when the volume is ramping up. The setting here is
applied to soft unmute request, asserted by XSMUTE pin or Page 0 / Register 3.
Default value: 10
00: Increment by 4 dB for each update
01: Increment by 2 dB for each update
10: Increment by 1 dB for each update
11: Increment by 0.5 dB for each update
Page 0 / Register 64
Dec
64
Hex
40
b7
VEDF1
0
b6
VEDF0
0
b5
VEDS1
0
b4
VEDS0
0
b3
b2
b1
b0
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
Digital Volume Emergency Ramp Down Frequency
VEDF[1:0]
These bits control the frequency of the digital volume updates when the volume is ramping down due to clock
error or power outage, which usually needs faster ramp down compared to normal soft mute.
Default value: 00
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
Digital Volume Emergency Ramp Down Step
VEDS[1:0]
These bits control the step of the digital volume updates when the volume is ramping down due to clock error
or power outage, which usually needs faster ramp down compared to normal soft mute.
Default value: 00
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00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
Page 0 / Register 65
Dec
65
Hex
41
b7
b6
b5
b4
b3
b2
ACTL2
1
b1
AMLE1
1
b0
AMRE0
1
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
ACTL[2:0]
Auto Mute Control
This bit controls the behavior of the auto mute upon zero sample detection. The time length for zero detection
is set with Page 0 / Register 59.
Default value: 111
0: Auto mute left channel and right channel independently.
1: Auto mute left and right channels only when both channels are about to be auto muted.
Auto Mute Left Channel
AMLE[1:0]
This bit enables or disables auto mute on right channel. Note that when right channel auto mute is disabled and
the Page 0 / Register 65, bit 2 is set to 1, the left channel will also never be auto muted.
Default value: 11
0: Disable right channel auto mute
1: Enable right channel auto mute
Auto Mute Right Channel
AMRE
This bit enables or disables auto mute on left channel. Note that when left channel auto mute is disabled and
the Page 0 / Register 65, bit 2 is set to 1, the right channel will also never be auto muted.
Default value: 1
0: Disable left channel auto mute
1: Enable left channel auto mute
Page 0 / Register 80
Dec
80
Hex
50
b7
b6
b5
b4
G1SL4
0
b3
G1SL3
0
b2
G1SL2
0
b1
G1SL1
0
b0
G1SL0
0
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
G1SL[4:0]
GPIO1 Output Selection
These bits select the signal to output to GPIO1. To actually output the selected signal, the GPIO1 must be set
to output mode at Page 0 / Register 8.
Default value: 00000
00000: off (low)
00001: DSP GPIO1 output
00010: Register GPIO1 output (Page 0 / Register 86, bit 0)
00011: Auto mute flag (asserted when both L and R channels are auto muted)
00100: Auto mute flag for left channel
00101: Auto mute flag for right channel
00110: Clock invalid flag (clock error or clock changing or clock missing)
00111: Serial audio interface data output (SDOUT)
01000: Analog mute flag for left channel (low active)
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01001: Analog mute flag for right channel (low active)
01010: PLL lock flag
01011: Charge pump clock
01100: Reserved
01101: Reserved
01110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD
01111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD
010000: PLL Output/4 (Requires Clock Flex Register)
OTHERS: RESERVED
Page 0 / Register 81
Dec
81
Hex
51
b7
b6
b5
b4
G2SL4
0
b3
G2SL3
0
b2
G2SL2
0
b1
G2SL1
0
b0
G2SL0
0
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
G2SL[4:0]
GPIO2 Output Selection
These bits select the signal to output to GPIO2. To actually output the selected signal, the GPIO2 must be set
to output mode at Page 0 / Register 8.
Default value: 00000
00000: off (low)
00001: DSP GPIO2 output
00010: Register GPIO2 output (Page 0 / Register 86, bit 1)
00011: Auto mute flag (asserted when both L and R channels are auto muted)
00100: Auto mute flag for left channel
00101: Auto mute flag for right channel
00110: Clock invalid flag (clock error or clock changing or clock missing)
00111: Serial audio interface data output (SDOUT)
01000: Analog mute flag for left channel (low active)
01001: Analog mute flag for right channel (low active)
01010: PLL lock flag
01011: Charge pump clock
01100: Reserved
01101: Reserved
01110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD
01111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD
010000: PLL Output/4 (Requires Clock Flex Register)
OTHERS: RESERVED
Page 0 / Register 82
Dec
82
Hex
52
b7
b6
b5
b4
G3SL4
0
b3
G3SL3
0
b2
G3SL2
0
b1
G3SL1
0
b0
G3SL0
0
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
G3SL[4:0]
GPIO3 Output Selection
These bits select the signal to output to GPIO3. To actually output the selected signal, the GPIO3 must be set
to output mode at Page 0 / Register 8.
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Default value: 00000
0000: off (low)
0001: DSP GPIO3 output
0010: Register GPIO3 output (Page 0 / Register 86, bit 2)
00011: Auto mute flag (asserted when both L and R channels are auto muted)
00100: Auto mute flag for left channel
00101: Auto mute flag for right channel
00110: Clock invalid flag (clock error or clock changing or clock missing)
00111: Serial audio interface data output (SDOUT)
01000: Analog mute flag for left channel (low active)
01001: Analog mute flag for right channel (low active)
01010: PLL lock flag
01011: Charge pump clock
01100: Reserved
01101: Reserved
01110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD
01111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD
010000: PLL Output/4 (Requires Clock Flex Register)
OTHERS: RESERVED
Page 0 / Register 83
Dec
83
Hex
53
b7
b6
b5
b4
G4SL4
0
b3
G4SL3
0
b2
G4SL2
0
b1
G4SL1
0
b0
G4SL0
0
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
G4SL[4:0]
GPIO4 Output Selection
These bits select the signal to output to GPIO4. To actually output the selected signal, the GPIO4 must be set
to output mode at Page 0 / Register 8.
Default value: 00000
00000: off (low)
00001: DSP GPIO4 output
00010: Register GPIO4 output (Page 0 / Register 86, bit 3)
00011: Auto mute flag (asserted when both L and R channels are auto muted)
00100: Auto mute flag for left channel
00101: Auto mute flag for right channel
00110: Clock invalid flag (clock error or clock changing or clock missing)
00111: Serial audio interface data output (SDOUT)
01000: Analog mute flag for left channel (low active)
01001: Analog mute flag for right channel (low active)
01010: PLL lock flag
01011: Charge pump clock
01100: Reserved
01101: Reserved
01110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD
01111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD
010000: PLL Output/4 (Requires Clock Flex Register)
OTHERS: RESERVED
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Page 0 / Register 84
Dec
84
Hex
54
b7
b6
b5
b4
G5SL4
0
b3
G5SL3
0
b2
G5SL2
0
b1
G5SL1
0
b0
G5SL0
0
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
G5SL[4:0]
GPIO5 Output Selection
These bits select the signal to output to GPIO5. To actually output the selected signal, the GPIO5 must be set
to output mode at Page 0 / Register 8.
Default value: 00000
00000: off (low)
00001: DSP GPIO5 output
00010: Register GPIO5 output (Page 0 / Register 86, bit 4
00011: Auto mute flag (asserted when both L and R channels are auto muted)
00100: Auto mute flag for left channel
00101: Auto mute flag for right channel
00110: Clock invalid flag (clock error or clock changing or clock missing)
00111: Serial audio interface data output (SDOUT)
01000: Analog mute flag for left channel (low active)
01001: Analog mute flag for right channel (low active)
01010: PLL lock flag
01011: Charge pump clock
01100: Reserved
01101: Reserved
01110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD
01111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD
010000: PLL Output/4 (Requires Clock Flex Register)
OTHERS: RESERVED
Page 0 / Register 85
Dec
85
Hex
55
b7
b6
b5
b4
G6SL4
0
b3
G6SL3
0
b2
G6SL2
0
b1
G6SL1
0
b0
G6SL0
0
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
G6SL[4:0]
GPIO6 Output Selection
These bits select the signal to output to GPIO6. To actually output the selected signal, the GPIO6 must be set
to output mode at Page 0 / Register 8.
Default value: 00000
00000: off (low)
00001: DSP GPIO6 output
00010: Register GPIO6 output (Page 0 / Register 86, bit 5)
00011: Auto mute flag (asserted when both L and R channels are auto muted)
00100: Auto mute flag for left channel
00101: Auto mute flag for right channel
00110: Clock invalid flag (clock error or clock changing or clock missing)
00111: Serial audio interface data output (SDOUT)
01000: Analog mute flag for left channel (low active)
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01001: Analog mute flag for right channel (low active)
01010: PLL lock flag
01011: Charge pump clock
01100: Reserved
01101: Reserved
01110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD
01111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD
010000: PLL Output/4 (Requires Clock Flex Register)
OTHERS: RESERVED
Page 0 / Register 86
Dec
86
Hex
56
b7
b6
b5
GOUT5
0
b4
GOUT4
0
b3
GOUT3
0
b2
GOUT2
0
b1
GOUT1
0
b0
GOUT0
0
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
GOUT5
GPIO6 Output Control
This bit controls the GPIO6 output when the selection at Page 0 / Register 85 is set to 0010 (register output)
Default value: 0
0: Output low
1: Output high
GOUT4
GOUT3
GOUT2
GOUT1
GOUT0
GPIO5 Output Control
This bit controls the GPIO5 output when the selection at Page 0 / Register 84 is set to 0010 (register output)
Default value: 0
0: Output low
1: Output high
GPIO4 Output Control
This bit controls the GPIO4 output when the selection at Page 0 / Register 83 is set to 0010 (register output)
Default value: 0
0: Output low
1: Output high
GPIO3 Output Control
This bit controls the GPIO3 output when the selection at Page 0 / Register 82 is set to 0010 (register output)
Default value: 0
0: Output low
1: Output high
GPIO2 Output Control
This bit controls the GPIO2 output when the selection at Page 0 / Register 81 is set to 0010 (register output)
Default value: 0
0: Output low
1: Output high
GPIO1 Output Control
This bit controls the GPIO1 output when the selection at Page 0 / Register 80 is set to 0010 (register output)
Default value: 0
0: Output low
1: Output high
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Page 0 / Register 87
Dec
87
Hex
57
b7
b6
b5
GINV5
0
b4
GINV4
0
b3
GINV3
0
b2
GINV2
0
b1
GINV1
0
b0
GINV0
0
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
GINV5
GINV4
GINV3
GINV2
GINV1
GINV0
GPIO6 Output Inversion
This bit controls the polarity of GPIO6 output. When set to 1, the output will be inverted for any signal being
selected.
Default value: 0
0: Non-inverted
1: Inverted
GPIO5 Output Inversion
This bit controls the polarity of GPIO5 output. When set to 1, the output will be inverted for any signal being
selected.
Default value: 0
0: Non-inverted
1: Inverted
GPIO4 Output Inversion
This bit controls the polarity of GPIO4 output. When set to 1, the output will be inverted for any signal being
selected.
Default value: 0
0: Non-inverted
1: Inverted
GPIO3 Output Inversion
This bit controls the polarity of GPIO3 output. When set to 1, the output will be inverted for any signal being
selected.
Default value: 0
0: Non-inverted
1: Inverted
GPIO2 Output Inversion
This bit controls the polarity of GPIO2 output. When set to 1, the output will be inverted for any signal being
selected.
Default value: 0
0: Non-inverted
1: Inverted
GPIO1 Output Inversion
This bit controls the polarity of GPIO1 output. When set to 1, the output will be inverted for any signal being
selected.
Default value: 0
0: Non-inverted
1: Inverted
Page 0 / Register 90
Dec
90
Hex
5A
b7
b6
b5
b4
b3
b2
b1
b0
RSV
RSV
RSV
L1OV
R1OV
L2OV
R2OV
SFOV
Reset Value
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RSV
SLASE12A –JULY 2014–REVISED OCTOBER 2014
Reserved
Reserved. Do not access.
Left1 Overflow (Read Only)
L1OV
R1OV
L2OV
R2OV
SFOV
This bit indicates whether the left channel of DSP first output port has overflow. This bit is sticky and is cleared
when read.
0: No overflow
1: Overflow occurred
Right1 Overflow (Read Only)
The bit indicates whether the right channel of DSP first output port has overflow. This bit is sticky and is cleared
when read.
0: No overflow
1: Overflow occurred
Left2 Overflow (Read Only)
This bit indicates whether the left channel of DSP second output port has overflow. This bit is sticky and is
cleared when read.
0: No overflow
1: Overflow occurred
Right2 Overflow (Read Only)
The bit indicates whether the right channel of DSP second output port has overflow. This bit is sticky and is
cleared when read.
0: No overflow
1: Overflow occurred
Shifter Overflow (Read Only)
This bit indicates whether overflow occurred in the DSP shifter (possible sample corruption). This bit is sticky
and is cleared when read.
0: No overflow
1: Overflow occurred
Page 0 / Register 91
Dec
91
Hex
5B
b7
b6
b5
b4
b3
b2
b1
b0
RSV
DTFS2
DTFS1
DTFS0
DTSR3
DTSR2
DTSR1
DTSR0
Reset Value
RSV
Reserved
Reserved. Do not access.
DTFS[2:0]
Detected FS (Read Only)
These bits indicate the currently detected audio sampling rate.
000: Error (Out of valid range)
001: 8 kHz
010: 16 kHz
011: 32-48 kHz
100: 88.2-96 kHz
101: 176.4-192 kHz
110: 384 kHz
DTSR[3:0]
Detected SCK Ratio (Read Only)
These bits indicate the currently detected SCK ratio. Note that even if the SCK ratio is not indicated as error,
clock error might still be flagged due to incompatible combination with the sampling rate. Specifically the SCK
ratio must be high enough to allow enough DSP cycles for minimal audio processing when PLL is disabled. The
absolute SCK frequency must also be lower than 50 MHz.
0000: Ratio error (The SCK ratio is not allowed)
0001: SCK = 32 FS
0010: SCK = 48 FS
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0011: SCK = 64 FS
0100: SCK = 128 FS
0101: SCK = 192 FS
0110: SCK = 256 FS
0111: SCK = 384 FS
1000: SCK = 512 FS
1001: SCK = 768 FS
1010: SCK = 1024 FS
1011: SCK = 1152 FS
1100: SCK = 1536 FS
1101: SCK = 2048 FS
1110: SCK = 3072 FS
Page 0 / Register 92
Dec
92
Hex
5C
b7
b6
b5
b4
b3
b2
b1
b0
RSV
RSV
RSV
RSV
RSV
RSV
RSV
DTBR8
Reset Value
Page 0 / Register 93
93
5D
DTBR7
DTBR6
DTBR5
DTBR4
DTBR3
DTBR2
DTBR1
DTBR0
Reset Value
RSV
Reserved
Reserved. Do not access.
Detected BCK Ratio (MSB) (Read Only)
DTBR[8:0]
These bits indicate the currently detected BCK ratio, i.e. the number of BCK clocks in one audio frame. Note
that for extreme case of BCK = 1 FS (which is not usable anyway), the detected ratio will be unreliable.
Page 0 / Register 94
Dec
94
Hex
5E
b7
b6
b5
b4
b3
b2
b1
b0
RSV
CDST
PLL-L
LrckBck
fS-SCKr
SCKval
BCKval
fSval
Reset Value
RSV
Reserved
Reserved. Do not access.
Clock Detector Status (Read Only)
CDST
This bit indicates whether the SCK clock is present or not.
0: SCK is present
1: SCK is missing (halted)
PLL-L
PLL locked (Read Only)
This bit indicates whether the PLL is locked or not. The PLL will be reported as unlocked when it is disabled.
0: PLL is locked
1: PLL is unlocked
LrckBck
fS-SCKr
LRCK-BCK present (Read Only)
This bit indicates whether the both LRCK and BCK are missing (tied low) or not.
0: LRCK and/or BCK is present
1: LRCK and BCK are missing
Sample rate SCK ratio valid (Read Only)
This bit indicates whether the combination of current sampling rate and SCK ratio is valid for clock auto set.
0: The combination of FS/SCK ratio is valid
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SCKval
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1: Error (clock auto set is not possible)
SCK valid (Read Only)
This bit indicates whether the SCK is valid or not. The SCK ratio must be detectable to be valid. There is a
limitation with this flag, that is, when the low period of LRCK is less than or equal to 5 BCKs, this flag will be
asserted (SCK invalid reported).
0: SCK is valid
1: SCK is invalid
BCKval
fSval
BCK valid (Read Only)
This bit indicates whether the BCK is valid or not. The BCK ratio must be stable and in the range of 32-256FS
to be valid.
0: BCK is valid
1: BCK is invalid
fS valid (Read Only)
This bit indicated whether the audio sampling rate is valid or not. The sampling rate must be detectable to be
valid. There is a limitation with this flag, that is when this flag is asserted and Page 0 / Register 37 is set to
ignore all asserted error flags such that the DAC recovers, this flag will be de-asserted (sampling rate invalid
not reported anymore).
0: Sampling rate is valid
1: Sampling rate is invalid
Page 0 / Register 95
Dec
95
Hex
5F
b7
b6
b5
b4
b3
b2
b1
b0
RSV
RSV
RSV
LTSH
RSV
CKMF
CSRF
CERF
Reset Value
RSV
Reserved
Reserved. Do not access.
Latched Clock Halt (Read Only)
LTSH
This bit indicates whether SCK halt has occurred. The bit is cleared when read.
0: SCK halt has not occurred
1: SCK halt has occurred since last read
Clock Missing (Read Only)
CKMF
CSRF
CERF
This bit indicates whether the LRCK and BCK are missing (tied low).
0: LRCK and/or BCK is present
1: LRCK and BCK are missing
Clock Resync Request (Read Only)
This bit indicates whether the clock resynchronization is in progress.
0: Not resynchronizing
1: Clock resynchronization is in progress
Clock Error (Read Only)
This bit indicates whether a clock error is being reported.
0: Clock is valid
1: Clock is invalid (Error)
Page 0 / Register 108
Dec
108
Hex
6C
b7
b6
b5
b4
b3
b2
b1
b0
RSV
RSV
RSV
RSV
RSV
RSV
AMLM
AMRM
Reset Value
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RSV
Reserved
Reserved. Do not access.
AMLM
Left Analog Mute Monitor (Read Only)
This bit is a monitor for left channel analog mute status.
0: Mute
1: Unmute
AMRM
Right Analog Mute Monitor (Read Only)
This bit is a monitor for right channel analog mute status.
0: Mute
1: Unmute
Page 0 / Register 109
Dec
109
Hex
6D
b7
b6
b5
b4
b3
b2
b1
b0
RSV
RSV
RSV
SDTM
RSV
RSV
RSV
SHTM
Reset Value
RSV
Reserved
Reserved. Do not access.
Short detect monitor (Read Only)
SDTM
This bit indicates whether line output short is occuring.
0: Normal (No short)
1: Line output is being shorted
SHTM
Short detected monitor (Read Only)
This bit indicates whether line output short has occurred since last read. This bit is sticky and is cleared when
read.
0: No short
1: Line output short occurred
Page 0 / Register 114
Dec
114
Hex
72
b7
b6
b5
b4
b3
b2
b1
b0
RSV
RSV
RSV
RSV
RSV
RSV
MTST1
MTST0
Reset Value
RSV
Reserved
Reserved. Do not access.
MTST[1:0]
MUTEZ status (Read Only)
These bits indicate the output of the XSMUTE level decoder for monitoring purpose.
11: 0.7 VDD ≤ XSMUTE
01: 0.3 VDD ≤ XSMUTE < 0.7 VDD
00: 0.3 VDD > XSMUTE
Page 0 / Register 115
Dec
115
Hex
73
b7
b6
b5
b4
b3
b2
b1
b0
RSV
RSV
RSV
RSV
RSV
RSV
FSMM1
FSMM0
Reset Value
RSV
Reserved
Reserved. Do not access.
FS Speed Mode Monitor (Read Only)
FSMM[1:0]
These bits indicate the actual FS operation mode being used. The actual value is the auto set one when clock
auto set is active and register set one when clock auto set is disabled.
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00: Single speed (FS ≤ 48 kHz)
01: Double speed (48 kHz < FS ≤ 96 kHz)
10: Quad speed (96 kHz < FS ≤ 192 kHz)
11: Octal speed (192 kHz < FS ≤ 384 kHz)
Page 0 / Register 118
Dec
118
Hex
76
b7
b6
b5
b4
b3
b2
b1
b0
BOTM
RSV
RSV
RSV
PSTM3
PSTM2
PSTM1
PSTM0
Reset Value
RSV
Reserved
Reserved. Do not access.
DSP Boot Done Flag (Read Only)
BOTM
This bit indicates whether the DSP boot is completed.
0: DSP is booting
1: DSP boot completed
PSTM[3:0]
Power State (Read Only)
These bits indicate the current power state of the DAC.
0000: Powerdown
0001: Wait for CP voltage valid
0010: Calibration
0011: Calibration
0100: Volume ramp up
0101: Run (Playing)
0110: Line output short / Low impedance
0111: Volume ramp down
1000: Standby
Page 0 / Register 119
Dec
119
Hex
77
b7
b6
b5
b4
b3
b2
b1
b0
RSV
RSV
GPIN5
GPIN4
GPIN3
GPIN2
GPIN1
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
GPIN[5:0]
GPIO Input States (Read Only)
This bit indicates the logic level at GPIO6 pin.
0: Low
1: High
Page 0 / Register 120
Dec
120
Hex
78
b7
b6
b5
b4
b3
b2
b1
b0
RSV
RSV
RSV
AMFL
RSV
RSV
RSV
AMFR
Reset Value
RSV
Reserved
Reserved. Do not access.
AMFL
Auto Mute Flag for Left Channel (Read Only)
This bit indicates the auto mute status for left channel.
0: Not auto muted
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1: Auto muted
AMFR
Auto Mute Flag for Right Channel (Read Only)
This bit indicates the auto mute status for right channel.
0: Not auto muted
1: Auto muted
Page 0 / Register 121
Dec
121
Hex
79
b7
b6
b5
b4
b3
b2
b1
b0
DAMD
0
RSV
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
DAMD
DAC Mode
This bit controls the DAC architecture to vary the DAC auditory signature.
Default value: 0
0: Mode1 - New hyper-advanced current-segment architecture
1: Mode2 - Classic PCM1792 advanced current-segment architecture
Page 0 / Register 122
Dec
122
Hex
7A
b7
b6
b5
b4
b3
b2
b1
b0
EIFM
0
RSV
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
External Interpolation Filter Mode
EIFM
This bit enables or disables the PCM1792 External Interpolation Filter Mode. This mode is used with a
PCM1792 in external digital filter mode.
Default value: 0
0: Normal mode
1: External Interpolation Filter Mode
Page 0 / Register 123
Dec
123
Hex
7B
b7
b6
G1MC2
0
b5
G1MC1
0
b4
G1MC0
0
b3
b2
G2MC2
0
b1
G2MC1
0
b0
G2MC0
0
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
GPIO1 output for External Interpolation Filter Mode
G1MC[2:0]
These bits select a signal to be output to GPIO1 in External Interpolation Filter mode.
Default value: 000
000: Logic low
001: MS
010: BCK (256FS)
011: WDCK (8FS)
100: DATAL
101: DATAR
110: Raw DIN (from DIN pin)
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G2MC[2:0]
SLASE12A –JULY 2014–REVISED OCTOBER 2014
111: Raw LRCK (from LRCK pin)
GPIO2 output for External Interpolation Filter Mode
These bits select a signal to be output to GPIO2 in External Interpolation Filter mode.
Default value: 000
000: Logic low
001: MS
010: BCK (256FS)
011: WDCK (8FS)
100: DATAL
101: DATAR
110: Raw DIN (from DIN pin)
111: Raw LRCK (from LRCK pin)
Page 0 / Register 124
Dec
124
Hex
7C
b7
b6
G3MC2
0
b5
G3MC1
0
b4
G3MC0
0
b3
b2
G4MC2
0
b1
G4MC1
0
b0
G4MC0
0
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
GPIO3 output for External Interpolation Filter Mode
G3MC[2:0]
These bits select a signal to be output to GPIO3 in External Interpolation Filter Mode.
Default value: 000
000: Logic low
001: MS
010: BCK (256FS)
011: WDCK (8FS)
100: DATAL
101: DATAR
110: Raw DIN (from DIN pin)
111: Raw LRCK (from LRCK pin)
G4MC[2:0]
GPIO4 output for External Interpolation Filter Mode
These bits select a signal to be output to GPIO4 in External Interpolation Filter Mode.
Default value: 000
000: Logic low
001: MS
010: BCK (256FS)
011: WDCK (8FS)
100: DATAL
101: DATAR
110: Raw DIN (from DIN pin)
111: Raw LRCK (from LRCK pin)
Page 0 / Register 125
Dec
125
Hex
7D
b7
b6
G5MC2
0
b5
G5MC1
0
b4
G5MC0
0
b3
b2
G6MC2
0
b1
G6MC1
0
b0
G6MC0
0
RSV
RSV
Reset Value
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RSV
Reserved
Reserved. Do not access.
G5MC[2:0]
GPIO5 output for External Interpolation Filter Mode
These bits select a signal to be output to GPIO5 in External Interpolation Filter mode.
Default value: 000
000: Logic low
001: MS
010: BCK (256FS)
011: WDCK (8FS)
100: DATAL
101: DATAR
110: Raw DIN (from DIN pin)
111: Raw LRCK (from LRCK pin)
G6MC[2:0]
GPIO6 output for External Interpolation Filter Mode
These bits select a signal to be output to GPIO6 in External Interpolation Filter mode.
Default value: 000
000: Logic low
001: MS
010: BCK (256FS)
011: WDCK (8FS)
100: DATAL
101: DATAR
110: Raw DIN (from DIN pin)
111: Raw LRCK (from LRCK pin)
12.3.1.3 Page 1 Registers
Page 1 / Register 1
Dec
1
Hex
01
b7
b6
b5
b4
b3
b2
b1
b0
OSEL
0
RSV
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
OSEL
Output Amplitude Type
This bit selects the output amplitude type. The clock autoset feature will not work with PLL enabled in VCOM
mode. In this case this feature has to be disabled via Page 0 / Register 37 and the clock dividers must be set
manually.
Default value: 0
0: VREF mode (Constant output amplitude against AVDD variation)
1: VCOM mode (Output amplitude is proportional to AVDD variation)
Page 1 / Register 2
Dec
Hex
02
b7
b6
b5
b4
LAGN
0
b3
b2
b1
b0
RAGN
0
2
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
LAGN
Analog Gain Control for Left Channel
This bit controls the left channel analog gain.
108
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Default value: 0
0: 0 dB
1:-6 dB
RAGN
Analog Gain Control for Right Channel
This bit controls the right channel analog gain.
Default value: 0
0: 0 dB
1: -6 dB
Page 1 / Register 5
Dec
5
Hex
05
b7
b6
b5
b4
b3
b2
b1
UEPD
0
b0
UIPD
0
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
UEPD
External UVP Control
This bit enables or disables detection of power supply drop via XSMUTE pin (External Under Voltage
Protection).
Default value: 0
0: Enabled
1: Disabled
UIPD
Internal UVP Control
This bit enables or disables internal detection of AVDD voltage drop (Internal Under Voltage Protection).
Default value: 0
0: Enabled
1: Disabled
Page 1 / Register 6
Dec
Hex
06
b7
b6
b5
b4
b3
b2
b1
b0
AMCT
0
6
RSV
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
AMCT
Analog Mute Control
This bit enables or disables analog mute following digital mute.
Default value: 0
0: Enabled
1: Disabled
Page 1 / Register 7
Dec
Hex
07
b7
b6
b5
b4
AGBL
0
b3
b2
b1
b0
AGBR
0
7
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
Analog +10% Gain for Left Channel
This bit enables or disables amplitude boost mode for left channel.
AGBL
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Default value: 0
0: Normal amplitude
1: +10% (+0.8 dB) boosted amplitude
AGBR
Analog +10% Gain for Right Channel
This bit enables or disables amplitude boost mode for right channel.
Default value: 0
0: Normal amplitude
1: +10% (+0.8 dB) boosted amplitude
Page 1 / Register 8
Dec
Hex
08
b7
b6
b5
b4
b3
b2
b1
b0
RCMF
0
8
RSV
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
RCMF
VCOM Reference Ramp Up
This bit controls the VCOM voltage ramp up speed.
Default value: 0
0: Normal ramp up, ~600ms with external capacitance = 1uF
1: Fast ramp up, ~3ms with external capacitance = 1uF
Page 1 / Register 9
Dec
Hex
09
b7
b6
b5
b4
b3
b2
b1
b0
VCPD
1
9
RSV
RSV
RSV
RSV
RSV
RSV
RSV
Reset Value
RSV
Reserved
Reserved. Do not access.
VCPD
Power down control for VCOM
This bit controls VCOM powerdown switch.
Default value: 1
0: VCOM is powered on
1: VCOM is powered down
12.3.1.4 Page 44 Registers
Page 44 / Register 1
Dec
1
Hex
01
b7
b6
b5
b4
b3
b2
AMDC
0
b1
b0
ACSW
0
RSV
RSV
RSV
RSV
ACRM
ACRS
Reset Value
RSV
Reserved
Reserved. Do not access.
Active CRAM Monitor (Read Only)
ACRM
This bit indicates which CRAM is being accessed by the DSP when adaptive mode is disabled. When adaptive
mode is enabled, this bit has no meaning.
0: CRAM A is being used by the DSP
1: CRAM B is being used by the DSP
Adaptive Mode Control
AMDC
110
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This bit controls the DSP adaptive mode. When in adaptive mode, only CRAM A is accessible via serial
interface when the DSP is disabled (DAC in standby state), while when the DSP is enabled (DAC is run state)
the CRAM A can only be accessed by the DSP and the CRAM B can only be accessed by the serial interface,
or vice versa depending on the value of CRAMSTAT. When not in adaptive mode, both CRAM A and B can be
accessed by the serial interface when the DSP is disabled, but when the DSP is enabled, no CRAM can be
accessed by serial interface. The DSP can access either CRAM, which can be monitored at SWPMON.
Default value: 0
0: Adaptive mode disabled
1: Adaptive mode enabled
ACRS
ACSW
Active CRAM Selection (Read Only)
This bit indicates which CRAM currently serves as the active one. The other CRAM serves as an update buffer,
and can accessed by serial interface (SPI/I2C)
0: CRAM A is active and being used by the DSP
1: CRAM B is active and being used by the DSP
Switch Active CRAM
This bit is used to request switching roles of the two buffers, i.e. switching the active buffer role between CRAM
A and CRAM B. This bit is cleared automatically when the switching process completed.
Default value: 0
0: No switching requested or switching completed
1: Switching is being requested
12.3.1.5 Page 253 Registers
Page 253 / Register 63
Dec
63
Hex
3F
b7
b6
b5
b4
b3
b2
b1
b0
PLLFLEX17 PLLFLEX16 PLLFLEX15 PLLFLEX14 PLLFLEX13 PLLFLEX12 PLLFLEX11 PLLFLEX10
Reset Value
0
0
0
0
0
0
0
0
PLLFLEX1[7:0]
Clock Flex Register #1
Clock Flex Register #1. Write 0x11 to this register to allow advanced clock tree functions. See Clocking
Overview section.
Default value: 00000000
Page 253 / Register 64
Dec
64
Hex
40
b7
b6
b5
b4
b3
b2
b1
b0
PLLFLEX27 PLLFLEX26 PLLFLEX25 PLLFLEX24 PLLFLEX23 PLLFLEX22 PLLFLEX21 PLLFLEX20
Reset Value
0
0
0
0
0
0
0
0
PLLFLEX2[7:0]
Clock Flex Register #2
Clock Flex Register #2. Write 0xFF to this register to allow advanced clock tree functions. See Clocking
Overview section.
Default value: 00000000
12.3.2 PLL Tables for Software Controlled Devices
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CP f (kHz)
Table 50. Recommended Clock Divider Settings for PLL as Master Clock (VREF Mode)
PLL VCO
(MHz)
DSP CLK
(MHz)
fS (kHz) RSCK
SCK (MHz)
P
PLL REF (MHz)
M = K*R
K = J.D
R
PLL fS
DSP fS NMAC
MOD fS
MOD f (kHz) NDAC
DOSR
% Error
NCP
8
8
8
8
8
8
8
8
8
8
8
128
192
1.024
1.536
2.048
3.072
4.096
6.144
8.192
9.216
12.288
16.384
24.576
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
1
1
1
3
3
3
3
9
9
9
9
1.024
1.536
2.048
1.024
1.365
2.048
2.731
1.024
1.365
1.82
96
64
48
96
72
48
36
96
72
54
36
48
32
48
48
36
48
36
48
36
54
36
2
2
1
2
2
1
1
2
2
1
1
12288
12288
12288
12288
12288
12288
12288
12288
12288
12288
12288
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
12
12
12
12
12
12
12
12
12
12
12
8.192
8.192
8.192
8.192
8.192
8.192
8.192
8.192
8.192
8.192
8.192
768
768
768
768
768
768
768
768
768
768
768
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
16
16
16
16
16
16
16
16
16
16
16
48
48
48
48
48
48
48
48
48
48
48
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
4
4
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
256
384
512
768
1024
1152
1536
2048
3072
2.731
11.025
11.025
11.025
11.025
11.025
11.025
11.025
11.025
11.025
11.025
11.025
128
192
1.4112
2.1168
2.8224
4.2336
5.6448
8.4672
11.2896
12.7008
16.9344
22.5792
33.8688
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
1
3
1
3
3
3
3
9
9
9
9
1.411
0.706
2.822
1.411
1.882
2.822
3.763
1.411
1.882
2.509
3.763
64
128
32
64
48
32
24
64
48
36
24
32
32
32
32
48
32
24
32
48
36
24
2
4
1
2
1
1
1
2
1
1
1
8192
8192
8192
8192
8192
8192
8192
8192
8192
8192
8192
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
8
8
8
8
8
8
8
8
8
8
8
11.2896
11.2896
11.2896
11.2896
11.2896
11.2896
11.2896
11.2896
11.2896
11.2896
11.2896
512
512
512
512
512
512
512
512
512
512
512
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
16
16
16
16
16
16
16
16
16
16
16
32
32
32
32
32
32
32
32
32
32
32
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
4
4
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
256
384
512
768
1024
1152
1536
2048
3072
16
16
16
16
16
16
16
16
16
16
16
16
64
1.024
2.048
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
1
1
1
1
3
3
3
3
3
9
9
9
1.024
2.048
3.072
4.096
2.048
2.731
4.096
5.461
6.144
2.731
3.641
5.461
96
48
32
24
48
36
24
18
16
36
27
18
48
48
32
24
48
36
24
18
16
36
27
18
2
1
1
1
1
1
1
1
1
1
1
1
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
6
6
6
6
6
6
6
6
6
6
6
6
16.384
16.384
16.384
16.384
16.384
16.384
16.384
16.384
16.384
16.384
16.384
16.384
384
384
384
384
384
384
384
384
384
384
384
384
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
16
16
16
16
16
16
16
16
16
16
16
16
24
24
24
24
24
24
24
24
24
24
24
24
0
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
4
4
4
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
128
192
3.072
256
4.096
384
6.144
512
8.192
768
12.288
16.384
18.432
24.576
32.768
49.152
1024
1152
1536
2048
3072
22.05
22.05
22.05
22.05
64
1.4112
2.8224
4.2336
5.6448
90.3168
90.3168
90.3168
90.3168
1
1
3
1
1.411
2.822
1.411
5.645
64
32
64
16
32
32
32
16
2
1
2
1
4096
4096
4096
4096
1024
1024
1024
1024
4
4
4
4
22.5792
22.5792
22.5792
22.5792
256
256
256
256
5644.8
5644.8
5644.8
5644.8
16
16
16
16
16
16
16
16
0
0
0
0
4
4
4
4
1411.2
1411.2
1411.2
1411.2
128
192
256
112
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SLASE12A –JULY 2014–REVISED OCTOBER 2014
Table 50. Recommended Clock Divider Settings for PLL as Master Clock (VREF Mode) (continued)
PLL VCO
(MHz)
DSP CLK
(MHz)
fS (kHz) RSCK
SCK (MHz)
P
PLL REF (MHz)
M = K*R
K = J.D
R
PLL fS
DSP fS NMAC
MOD fS
MOD f (kHz) NDAC
DOSR
% Error
NCP
CP f (kHz)
22.05
22.05
22.05
22.05
22.05
22.05
22.05
384
512
8.4672
11.2896
16.9344
22.5792
25.4016
33.8688
45.1584
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
3
3
3
3
9
9
9
2.822
3.763
5.645
7.526
2.822
3.763
5.018
32
24
16
12
32
24
18
32
24
16
12
32
24
18
1
1
1
1
1
1
1
4096
4096
4096
4096
4096
4096
4096
1024
1024
1024
1024
1024
1024
1024
4
4
4
4
4
4
4
22.5792
22.5792
22.5792
22.5792
22.5792
22.5792
22.5792
256
256
256
256
256
256
256
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
16
16
16
16
16
16
16
16
16
16
16
16
16
16
0
0
0
0
0
0
0
4
4
4
4
4
4
4
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
768
1024
1152
1536
2048
32
32
32
32
32
32
32
32
32
32
32
32
32
48
1.024
1.536
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
1
1
1
1
3
2
3
3
3
3
9
6
1.024
1.536
2.048
4.096
2.048
4.096
4.096
5.461
8.192
10.923
4.096
8.192
96
64
48
24
48
24
24
18
12
9
48
16
24
24
48
24
24
18
12
9
2
4
2
1
1
1
1
1
1
1
1
1
3072
3072
3072
3072
3072
3072
3072
3072
3072
3072
3072
3072
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
3
3
3
3
3
3
3
3
3
3
3
3
32.768
32.768
32.768
32.768
32.768
32.768
32.768
32.768
32.768
32.768
32.768
32.768
192
192
192
192
192
192
192
192
192
192
192
192
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
16
16
16
16
16
16
16
16
16
16
16
16
12
12
12
12
12
12
12
12
12
12
12
12
0
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
4
4
4
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
64
2.048
128
192
256
384
512
768
1024
1152
1536
4.096
6.144
8.192
12.288
16.384
24.576
32.768
36.864
49.152
24
12
24
12
44.1
44.1
44.1
44.1
44.1
44.1
44.1
44.1
44.1
32
64
1.4112
2.8224
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
1
1
1
3
2
3
3
3
3
1.411
2.822
5.645
2.822
5.645
5.645
7.526
11.29
15.053
64
32
16
32
16
16
12
8
32
16
16
32
16
16
12
8
2
2
1
1
1
1
1
1
1
2048
2048
2048
2048
2048
2048
2048
2048
2048
1024
1024
1024
1024
1024
1024
1024
1024
1024
2
2
2
2
2
2
2
2
2
45.1584
45.1584
45.1584
45.1584
45.1584
45.1584
45.1584
45.1584
45.1584
128
128
128
128
128
128
128
128
128
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
16
16
16
16
16
16
16
16
16
8
8
8
8
8
8
8
8
8
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
128
192
256
384
512
768
1024
5.6448
8.4672
11.2896
16.9344
22.5792
33.8688
45.1584
6
6
48
48
48
48
48
48
48
48
48
32
64
1.536
3.072
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
1
1
1
3
2
3
3
3
3
1.536
3.072
6.144
3.072
6.144
6.144
8.192
12.288
16.384
64
32
16
32
16
16
12
8
32
16
16
32
16
16
12
8
2
2
1
1
1
1
1
1
1
2048
2048
2048
2048
2048
2048
2048
2048
2048
1024
1024
1024
1024
1024
1024
1024
1024
1024
2
2
2
2
2
2
2
2
2
49.152
49.152
49.152
49.152
49.152
49.152
49.152
49.152
49.152
128
128
128
128
128
128
128
128
128
6144
6144
6144
6144
6144
6144
6144
6144
6144
16
16
16
16
16
16
16
16
16
8
8
8
8
8
8
8
8
8
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
1536
1536
1536
1536
1536
1536
1536
1536
1536
128
192
256
384
512
768
1024
6.144
9.216
12.288
18.432
24.576
36.864
49.152
6
6
96
32
3.072
98.304
1
3.072
32
16
2
1024
512
2
49.152
64
6144
16
4
0
4
1536
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SLASE12A –JULY 2014–REVISED OCTOBER 2014
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CP f (kHz)
Table 50. Recommended Clock Divider Settings for PLL as Master Clock (VREF Mode) (continued)
PLL VCO
(MHz)
DSP CLK
(MHz)
fS (kHz) RSCK
SCK (MHz)
P
PLL REF (MHz)
M = K*R
K = J.D
R
PLL fS
DSP fS NMAC
MOD fS
MOD f (kHz) NDAC
DOSR
% Error
NCP
96
96
96
96
96
96
96
48
4.608
6.144
98.304
98.304
98.304
98.304
98.304
98.304
98.304
3
1
2
3
4
6
8
1.536
6.144
6.144
6.144
6.144
6.144
6.144
64
16
16
16
16
16
16
32
8
2
2
1
1
1
1
1
1024
1024
1024
1024
1024
1024
1024
512
512
512
512
512
512
512
2
2
2
2
2
2
2
49.152
49.152
49.152
49.152
49.152
49.152
49.152
64
64
64
64
64
64
64
6144
6144
6144
6144
6144
6144
6144
16
16
16
16
16
16
16
4
4
4
4
4
4
4
0
0
0
0
0
0
0
4
4
4
4
4
4
4
1536
1536
1536
1536
1536
1536
1536
64
128
192
256
384
512
12.288
18.432
24.576
36.864
49.152
16
16
16
16
16
192
192
192
192
192
192
32
48
6.144
9.216
98.304
98.304
98.304
98.304
98.304
98.304
1
3
1
2
3
4
6.144
3.072
16
32
8
8
16
4
2
2
2
1
1
1
512
512
512
512
512
512
256
256
256
256
256
256
2
2
2
2
2
2
49.152
49.152
49.152
49.152
49.152
49.152
32
32
32
32
32
32
6144
6144
6144
6144
6144
6144
16
16
16
16
16
16
2
2
2
2
2
2
0
0
0
0
0
0
4
4
4
4
4
4
1536
1536
1536
1536
1536
1536
64
12.288
24.576
36.864
49.152
12.288
12.288
12.288
12.288
128
192
256
8
8
8
8
8
8
384
384
384
384
32
48
12.288
18.432
24.576
49.152
98.304
98.304
98.304
98.304
2
3
2
4
6.144
6.144
16
16
8
8
8
4
8
2
2
2
1
256
256
256
256
128
128
128
128
2
2
2
2
49.152
49.152
49.152
49.152
16
16
16
16
6144
6144
6144
6144
16
16
16
16
1
1
1
1
0
0
0
0
4
4
4
4
1536
1536
1536
1536
64
12.288
12.288
128
8
114
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fS (kHz)
SLASE12A –JULY 2014–REVISED OCTOBER 2014
Table 51. Recommended Clock Divider Settings for PLL as Master Clock (VCOM Mode)
SCK
(MHz)
PLL VCO
(MHz)
PLL REF
(MHz)
DSP CLK
(MHz)
MOD f
(kHz)
RSCK
P
M = K*R
K = J.D
R
PLL fS
DSP fS
NMAC
MOD fS
NDAC
DOSR
% Error
NCP
CP f (kHz)
8
8
8
8
8
8
8
8
8
8
8
128
192
1.024
1.536
2.048
3.072
4.096
6.144
8.192
9.216
12.288
16.384
24.576
73.728
73.728
73.728
73.728
73.728
73.728
73.728
73.728
73.728
73.728
73.728
1
1
1.024
1.536
2.048
3.072
2.048
2.048
2.048
1.536
2.048
2.048
2.048
72
48
36
24
36
36
36
48
36
36
36
36
24
36
12
36
36
36
48
36
36
36
2
2
1
2
1
1
1
1
1
1
1
9216
9216
9216
9216
9216
9216
9216
9216
9216
9216
9216
768
768
768
768
768
768
768
768
768
768
768
12
12
12
12
12
12
12
12
12
12
12
6.144
6.144
6.144
6.144
6.144
6.144
6.144
6.144
6.144
6.144
6.144
768
768
768
768
768
768
768
768
768
768
768
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
12
12
12
12
12
12
12
12
12
12
12
48
48
48
48
48
48
48
48
48
48
48
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
4
4
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
256
1
384
1
512
2
768
3
1024
1152
1536
2048
3072
4
6
6
8
12
11.025
11.025
11.025
11.025
11.025
11.025
11.025
11.025
11.025
11.025
11.025
128
192
1.4112
2.1168
2.8224
4.2336
5.6448
8.4672
11.2896
12.7008
16.9344
22.5792
33.8688
84.672
84.672
84.672
84.672
84.672
84.672
84.672
84.672
84.672
84.672
84.672
1
1
1
2
2
3
4
6
8
8
8
1.411
2.117
2.822
2.117
2.822
2.822
2.822
2.117
2.117
2.822
4.234
60
40
30
40
30
30
30
40
40
30
20
30
10
30
20
30
30
30
20
40
30
20
2
4
1
2
1
1
1
2
1
1
1
7680
7680
7680
7680
7680
7680
7680
7680
7680
7680
7680
960
960
960
960
960
960
960
960
960
960
960
8
8
8
8
8
8
8
8
8
8
8
10.584
10.584
10.584
10.584
10.584
10.584
10.584
10.584
10.584
10.584
10.584
512
512
512
512
512
512
512
512
512
512
512
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
15
15
15
15
15
15
15
15
15
15
15
32
32
32
32
32
32
32
32
32
32
32
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
4
4
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
256
384
512
768
1024
1152
1536
2048
3072
16
16
16
16
16
16
16
16
16
16
16
16
64
1.024
2.048
73.728
73.728
73.728
73.728
73.728
73.728
73.728
73.728
73.728
73.728
73.728
73.728
1
1
1
2
3
4
6
8
9
8
8
8
1.024
2.048
3.072
2.048
2.048
2.048
2.048
2.048
2.048
3.072
4.096
6.144
72
36
24
36
36
36
36
36
36
24
18
12
36
36
24
36
36
36
36
36
36
24
18
12
2
1
1
1
1
1
1
1
1
1
1
1
4608
4608
4608
4608
4608
4608
4608
4608
4608
4608
4608
4608
768
768
768
768
768
768
768
768
768
768
768
768
6
6
6
6
6
6
6
6
6
6
6
6
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
384
384
384
384
384
384
384
384
384
384
384
384
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
12
12
12
12
12
12
12
12
12
12
12
12
24
24
24
24
24
24
24
24
24
24
24
24
0
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
4
4
4
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
128
192
3.072
256
4.096
384
6.144
512
8.192
768
12.288
16.384
18.432
24.576
32.768
49.152
1024
1152
1536
2048
3072
22.05
22.05
22.05
22.05
64
1.4112
2.8224
4.2336
5.6448
84.672
84.672
84.672
84.672
1
1
3
2
1.411
2.822
1.411
2.822
60
30
60
30
30
30
30
30
2
1
2
1
3840
3840
3840
3840
960
960
960
960
4
4
4
4
21.168
21.168
21.168
21.168
256
256
256
256
5644.8
5644.8
5644.8
5644.8
15
15
15
15
16
16
16
16
0
0
0
0
4
4
4
4
1411.2
1411.2
1411.2
1411.2
128
192
256
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CP f (kHz)
Table 51. Recommended Clock Divider Settings for PLL as Master Clock (VCOM Mode) (continued)
SCK
(MHz)
PLL VCO
(MHz)
PLL REF
(MHz)
DSP CLK
(MHz)
MOD f
(kHz)
fS (kHz)
RSCK
P
M = K*R
K = J.D
R
PLL fS
DSP fS
NMAC
MOD fS
NDAC
DOSR
% Error
NCP
22.05
22.05
22.05
22.05
22.05
22.05
22.05
384
512
8.4672
11.2896
16.9344
22.5792
25.4016
33.8688
45.1584
84.672
84.672
84.672
84.672
84.672
84.672
84.672
3
2
3
4
9
8
8
2.822
5.645
5.645
5.645
2.822
4.234
5.645
30
15
15
15
30
20
15
30
15
15
15
30
20
15
1
1
1
1
1
1
1
3840
3840
3840
3840
3840
3840
3840
960
960
960
960
960
960
960
4
4
4
4
4
4
4
21.168
21.168
21.168
21.168
21.168
21.168
21.168
256
256
256
256
256
256
256
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
15
15
15
15
15
15
15
16
16
16
16
16
16
16
0
0
0
0
0
0
0
4
4
4
4
4
4
4
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
768
1024
1152
1536
2048
32
32
32
32
32
32
32
32
32
32
32
32
32
48
1.024
1.536
73.728
73.728
73.728
73.728
73.728
73.728
73.728
73.728
73.728
73.728
73.728
73.728
1
1
1.024
1.536
2.048
2.048
2.048
2.048
2.048
2.048
4.096
4.096
4.096
4.096
72
48
36
36
36
36
36
36
18
18
18
18
36
12
18
36
36
36
36
36
18
18
18
18
2
4
2
1
1
1
1
1
1
1
1
1
2304
2304
2304
2304
2304
2304
2304
2304
2304
2304
2304
2304
768
768
768
768
768
768
768
768
768
768
768
768
3
3
3
3
3
3
3
3
3
3
3
3
24.576
24.576
24.576
24.576
24.576
24.576
24.576
24.576
24.576
24.576
24.576
24.576
192
192
192
192
192
192
192
192
192
192
192
192
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
0
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
4
4
4
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
64
2.048
1
128
192
256
384
512
768
1024
1152
1536
4.096
2
6.144
3
8.192
4
12.288
16.384
24.576
32.768
36.864
49.152
6
8
6
8
9
12
44.1
44.1
44.1
44.1
44.1
44.1
44.1
44.1
44.1
44.1
32
48
1.4112
2.1168
84.672
84.672
84.672
84.672
84.672
84.672
84.672
84.672
84.672
84.672
1
1
1
1
2
2
3
4
6
8
1.411
2.117
2.822
5.645
4.234
5.645
5.645
5.645
5.645
5.645
60
40
30
15
20
15
15
15
15
15
30
10
15
15
20
15
15
15
15
15
2
4
2
1
1
1
1
1
1
1
1920
1920
1920
1920
1920
1920
1920
1920
1920
1920
960
960
960
960
960
960
960
960
960
960
2
2
2
2
2
2
2
2
2
2
42.336
42.336
42.336
42.336
42.336
42.336
42.336
42.336
42.336
42.336
128
128
128
128
128
128
128
128
128
128
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
15
15
15
15
15
15
15
15
15
15
8
8
8
8
8
8
8
8
8
8
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
4
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
64
2.8224
128
192
256
384
512
768
1024
5.6448
8.4672
11.2896
16.9344
22.5792
33.8688
45.1584
48
48
48
48
48
48
48
48
48
32
48
1.536
2.304
73.728
73.728
73.728
73.728
73.728
73.728
73.728
73.728
73.728
1
1
1
2
3
4
6
4
6
1.536
2.304
3.072
3.072
3.072
3.072
3.072
6.144
6.144
48
32
24
24
24
24
24
12
12
24
8
2
4
2
1
1
1
1
1
1
1536
1536
1536
1536
1536
1536
1536
1536
1536
768
768
768
768
768
768
768
768
768
2
2
2
2
2
2
2
2
2
36.864
36.864
36.864
36.864
36.864
36.864
36.864
36.864
36.864
128
128
128
128
128
128
128
128
128
6144
6144
6144
6144
6144
6144
6144
6144
6144
12
12
12
12
12
12
12
12
12
8
8
8
8
8
8
8
8
8
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
1536
1536
1536
1536
1536
1536
1536
1536
1536
64
3.072
12
24
24
24
24
12
12
128
192
256
384
512
768
6.144
9.216
12.288
18.432
24.576
36.864
116
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SLASE12A –JULY 2014–REVISED OCTOBER 2014
Table 51. Recommended Clock Divider Settings for PLL as Master Clock (VCOM Mode) (continued)
SCK
(MHz)
PLL VCO
(MHz)
PLL REF
(MHz)
DSP CLK
(MHz)
MOD f
(kHz)
fS (kHz)
RSCK
P
M = K*R
K = J.D
R
PLL fS
DSP fS
NMAC
MOD fS
NDAC
DOSR
% Error
NCP
CP f (kHz)
48
1024
49.152
73.728
8
6.144
12
12
1
1536
768
2
36.864
128
6144
12
8
0
4
1536
96
96
96
96
96
96
96
96
32
48
3.072
4.608
73.728
73.728
73.728
73.728
73.728
73.728
73.728
73.728
2
3
2
4
6
8
6
8
1.536
1.536
3.072
3.072
3.072
3.072
6.144
6.144
48
48
24
24
24
24
12
12
24
24
12
24
24
24
12
12
2
2
2
1
1
1
1
1
768
768
768
768
768
768
768
768
384
384
384
384
384
384
384
384
2
2
2
2
2
2
2
2
36.864
36.864
36.864
36.864
36.864
36.864
36.864
36.864
64
64
64
64
64
64
64
64
6144
6144
6144
6144
6144
6144
6144
6144
12
12
12
12
12
12
12
12
4
4
4
4
4
4
4
4
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
1536
1536
1536
1536
1536
1536
1536
1536
64
6.144
128
192
256
384
512
12.288
18.432
24.576
36.864
49.152
192
192
192
192
192
192
32
48
6.144
9.216
73.728
73.728
73.728
73.728
73.728
73.728
2
3
4
8
6
8
3.072
3.072
3.072
3.072
6.144
6.144
24
24
24
24
12
12
12
12
12
24
12
12
2
2
2
1
1
1
384
384
384
384
384
384
192
192
192
192
192
192
2
2
2
2
2
2
36.864
36.864
36.864
36.864
36.864
36.864
32
32
32
32
32
32
6144
6144
6144
6144
6144
6144
12
12
12
12
12
12
2
2
2
2
2
2
0
0
0
0
0
0
4
4
4
4
4
4
1536
1536
1536
1536
1536
1536
64
12.288
24.576
36.864
49.152
128
192
256
384
384
384
384
32
48
12.288
18.432
24.576
49.152
73.728
73.728
73.728
73.728
2
3
4
8
6.144
6.144
6.144
6.144
12
12
12
12
6
6
2
2
2
1
192
192
192
192
96
96
96
96
2
2
2
2
36.864
36.864
36.864
36.864
16
16
16
16
6144
6144
6144
6144
12
12
12
12
1
1
1
1
0
0
0
0
4
4
4
4
1536
1536
1536
1536
64
6
128
12
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CP f (kHz)
Table 52. Recommended Clock Divider Settings for SCK as Master Clock
fS (kHz)
RSCK
SCK (MHz)
DSP fS
NMAC
DSP CLK
(MHz)
MOD fS
MOD f (kHz)
NDAC
DOSR
NCP
8
8
8
8
8
8
8
8
8
256
384
2.048
3.072
4.096
6.144
8.192
9.216
12.288
16.384
24.576
256
384
1
1
1
1
1
1
1
1
1
2.048
3.072
4.096
6.144
8.192
9.216
12.288
16.384
24.576
256
384
512
768
512
576
768
512
768
2048
3072
4096
6144
4096
4608
6144
4096
6144
1
1
1
1
2
2
2
4
4
16
24
32
48
32
36
48
32
48
2
2
2
4
2
4
4
2
4
1024
1536
2048
1536
2048
1152
1536
2048
1536
512
512
768
768
1024
1152
1536
2048
3072
1024
1152
1536
2048
3072
11.025
11.025
11.025
11.025
11.025
11.025
256
384
2.8224
4.2336
256
384
1
1
1
1
1
1
2.822
4.234
256
384
384
512
512
512
2822.4
4233.6
4233.6
5644.8
5644.8
5644.8
1
1
3
3
4
6
16
24
24
32
32
32
2
4
4
4
4
4
1411.2
1058.4
1058.4
1411.2
1411.2
1411.2
1152
1536
2048
3072
12.7008
16.9344
22.5792
33.8688
1152
1536
2048
3072
12.701
16.934
22.579
33.869
16
16
16
16
16
16
16
16
256
384
4.096
6.144
256
384
1
1
1
1
1
1
1
1
4.096
6.144
256
384
256
384
288
384
256
384
4096
6144
4096
6144
4608
6144
4096
6144
1
1
2
2
4
4
8
8
16
24
16
24
18
24
16
24
2
4
2
4
4
4
2
4
2048
1536
2048
1536
1152
1536
2048
1536
512
8.192
512
8.192
768
12.288
18.432
24.576
32.768
49.152
768
12.288
18.432
24.576
32.768
49.152
1152
1536
2048
3072
1152
1536
2048
3072
22.05
22.05
22.05
22.05
22.05
22.05
22.05
22.05
256
384
5.6448
8.4672
256
384
1
1
1
1
1
1
1
1
5.645
8.467
256
192
256
256
256
192
256
256
5644.8
4233.6
5644.8
5644.8
5644.8
4233.6
5644.8
5644.8
1
2
2
3
4
6
6
8
16
12
16
16
16
12
16
16
4
4
4
4
4
4
4
4
1411.2
1058.4
1411.2
1411.2
1411.2
1058.4
1411.2
1411.2
512
11.2896
16.9344
22.5792
25.4016
33.8688
45.1584
512
11.29
768
768
16.934
22.579
25.402
33.869
45.158
1024
1152
1536
2048
1024
1152
1536
2048
32
32
32
32
32
32
32
256
384
8.192
12.288
16.384
24.576
32.768
36.864
49.152
256
384
1
1
1
1
1
1
1
8.192
12.288
16.384
24.576
32.768
36.864
49.152
128
128
128
128
128
128
128
4096
4096
4096
4096
4096
4096
4096
2
3
8
8
8
8
8
8
8
2
2
2
2
2
4
4
2048
2048
2048
2048
2048
1024
1024
512
512
4
768
768
6
1024
1152
1536
1024
1152
1536
8
9
12
44.1
44.1
44.1
44.1
44.1
256
384
512
768
1024
11.2896
16.9344
22.5792
33.8688
45.1584
256
384
512
768
1024
1
1
1
1
1
11.29
16.934
22.579
33.869
45.158
128
128
128
128
128
5644.8
5644.8
5644.8
5644.8
5644.8
2
3
4
6
8
8
8
8
8
8
4
4
4
4
4
1411.2
1411.2
1411.2
1411.2
1411.2
48
48
48
48
48
256
384
512
768
1024
12.288
18.432
24.576
36.864
49.152
256
384
512
768
1024
1
1
1
1
1
12.288
18.432
24.576
36.864
49.152
128
128
128
128
128
6144
6144
6144
6144
6144
2
3
4
6
8
8
8
8
8
8
4
4
4
4
4
1536
1536
1536
1536
1536
96
96
96
96
192
256
384
512
18.432
24.576
36.864
49.152
192
256
384
512
1
1
1
1
18.432
24.576
36.864
49.152
48
64
64
64
4608
6144
6144
6144
4
4
6
8
3
4
4
4
6
4
4
4
768
1536
1536
1536
118
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PCM5242
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fS (kHz)
SLASE12A –JULY 2014–REVISED OCTOBER 2014
Table 52. Recommended Clock Divider Settings for SCK as Master Clock (continued)
RSCK
SCK (MHz)
DSP fS
NMAC
DSP CLK
(MHz)
MOD fS
MOD f (kHz)
NDAC
DOSR
NCP
CP f (kHz)
192
192
192
128
192
256
24.576
36.864
49.152
128
192
256
1
1
1
24.576
36.864
49.152
32
32
32
6144
6144
6144
4
6
8
2
2
2
4
4
4
1536
1536
1536
384
384
64
24.576
49.152
64
1
1
24.576
49.152
16
16
6144
6144
4
8
1
1
4
4
1536
1536
128
128
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PCM5242
SLASE12A –JULY 2014–REVISED OCTOBER 2014
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13 Device and Documentation Support
13.1 Community Resources
E2E™ Audio Converters Forum TI
E2E Community
13.2 Trademarks
System Two Cascade, Audio Precision are trademarks of Audio Precision.
DirectPath is a trademark of Texas, Instruments, Inc..
All other trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, see the left-hand navigation.
120
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Product Folder Links: PCM5242
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PCM5242RHBR
PCM5242RHBT
ACTIVE
ACTIVE
VQFN
VQFN
RHB
RHB
32
32
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-25 to 85
-25 to 85
PCM5242
PCM5242
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCM5242RHBR
PCM5242RHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
330.0
180.0
12.4
12.4
5.3
5.3
5.3
5.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
PCM5242RHBR
PCM5242RHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
346.0
210.0
346.0
185.0
33.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
20.000
OPTIONAL METAL THICKNESS
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
SEE SIDE WALL
DETAIL
2X
SYMM
33
3.5
0.3
0.2
32X
24
0.1
C A B
C
1
0.05
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
32X
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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