PGA300ARHHR [TI]
适用于压力传感器的 PGA300 信号调节器和发送器 | RHH | 36 | -40 to 150;
| 型号： | PGA300ARHHR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于压力传感器的 PGA300 信号调节器和发送器 | RHH | 36 | -40 to 150 PC 传感器 压力传感器 调节器 |
| 文件： | 总68页 (文件大小：2038K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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PGA300
ZHCSF35A –OCTOBER 2014–REVISED JUNE 2016
PGA300 适用于压力传感器的信号调节器和发送器
1 特性
– 电源：
–
–
片上电源管理，支持 3.3V 至 30V 的宽电源
电压范围
1
•
模拟 特性
–
–
–
–
–
–
–
适用于阻性桥式传感器的模拟前端
传感器灵敏度可调节范围：1mV/V 至 135mV/V
片上温度传感器
集成反向保护电路
2 应用
可编程增益
•
•
•
压力传感器发送器和换能器
液位计、流量计
适用于信号通道的 16 位 Σ-Δ 模数转换器
适用于温度通道的 16 位 Σ-Δ 模数转换器
14 位输出数模转换器 (DAC)
阻性现场发送器
•
•
•
数字 特性
3 说明
–
–
–
–
–
整个温度范围内的 FSO 精度 < 0.1%
PGA300 器件提供了一个适用于压阻式和应力计压感
元件的接口。该器件具有可编程模拟前端 (AFE)、模数
转换器 (ADC) 和数字信号处理功能。这是一套完整的
片上系统 (SoC) 解决方案，可直接连接传感元件。此
外，PGA300 器件还集成了稳压器和振荡器，最大程
度地减少了外部组件数。该器件采用三阶温度和非线性
补偿实现高精度。凭借单线制串行接口 (OWI)，可以通
过电源引脚实现外部通信，从而简化系统校准过程。集
成 DAC 支持绝对电压、比例电压以及 4mA 至 20mA
的电流回路输出。
系统响应时间 < 220µs
三阶偏移、增益和非线性温度补偿
诊断功能
集成 EEPROM 用于存储器件操作、校准数据和
用户数据
外设 特性
–
单线接口，可通过电源引脚进行通信，无需额外
使用线路
–
–
–
–
4mA 至 20mA 电流回路接口
比例电压输出和绝对电压输出
电源管理控制
器件信息(1)
器件型号
PGA300
封装
VQFN (36)
封装尺寸（标称值）
模拟低压检测
6.00mm x 6.00mm
通用 特性
工业温度范围：–40°C 至 150°C
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
–
PGA300 简化框图
PGA300
BRG+
Ratiometric
Bridge Excitation
Power Management
OWI
Reference
EEPROM
Bridge
Sensor
INP+
INP–
16-Bit
ADC
PWR
(3.3 V – 30 V)
PGA
Resistive Sensing AFE
BRG–
Control
and Status
Registers
14-Bit
DAC
INT+
INT–
GAIN
16-Bit
ADC
OUT
PGA
Temperature Sensing AFE
Diagnostics
Third-Order TC and
Third-Order NL
Sensor
Internal
Oscillator
Internal
Temperature
Sensor
Optional
External
Compensation
Temperature
Sensor
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLDS204
PGA300
ZHCSF35A –OCTOBER 2014–REVISED JUNE 2016
www.ti.com.cn
目录
Converter ................................................................... 9
6.15 Electrical Characteristics – One-Wire Interface ...... 9
6.16 Electrical Characteristics – DAC Output ................. 9
6.17 Electrical Characteristics – DAC Gain .................... 9
6.18 Electrical Characteristics – Non-Volatile Memory. 10
6.19 Electrical Characteristics – Diagnostics................ 10
6.20 Operating Characteristics...................................... 12
6.21 Typical Characteristics.......................................... 13
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 39
7.5 Register Maps......................................................... 39
Application and Implementation ........................ 54
8.1 Application Information............................................ 54
Power Supply Recommendations...................... 60
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
7
6.5 Electrical Characteristics – Reverse Voltage
Protection................................................................... 6
6.6 Electrical Characteristics – Regulators ..................... 6
6.7 Electrical Characteristics – Internal Reference......... 6
6.8 Electrical Characteristics – Bridge Sensor Supply.... 6
8
9
6.9 Electrical Characteristics – Temperature Sensor
Supply ........................................................................ 7
6.10 Electrical Characteristics – Internal Temperature
Sensor........................................................................ 7
10 Layout................................................................... 60
10.1 Layout Guidelines ................................................. 60
10.2 Layout Example .................................................... 60
11 器件和文档支持 ..................................................... 62
11.1 商标....................................................................... 62
11.2 静电放电警告......................................................... 62
11.3 Glossary................................................................ 62
12 机械、封装和可订购信息....................................... 62
6.11 Electrical Characteristics – P Gain (Chopper
Stabilized) .................................................................. 7
6.12 Electrical Characteristics – P Analog-to-Digital
Converter ................................................................... 8
6.13 Electrical Characteristics – T Gain (Chopper
Stabilized) .................................................................. 8
6.14 Electrical Characteristics – T Analog-to-Digital
4 修订历史记录
Changes from Original (October 2014) to Revision A
Page
•
已将数据表状态由“产品预览”改为“量产数据” .......................................................................................................................... 1
2
Copyright © 2014–2016, Texas Instruments Incorporated
PGA300
www.ti.com.cn
ZHCSF35A –OCTOBER 2014–REVISED JUNE 2016
5 Pin Configuration and Functions
RHH Package
36-Pin VQFN With Thermal Pad
Top View
NU
DVDD_MEM
DVDD
1
2
3
4
5
6
7
8
9
27
26
25
24
23
22
21
20
19
NU
NU
NU
NU
NU
Thermal
Pad
PWR
AVSS
INT–
INT+
NU
DACCAP
NU
OUT
AVDD
NU
NU – Make no external connection
Copyright © 2014–2016, Texas Instruments Incorporated
3
PGA300
ZHCSF35A –OCTOBER 2014–REVISED JUNE 2016
www.ti.com.cn
Pin Functions
PIN
I/O
DESCRIPTION
NAME
AVDD
NO.
9
O
—
O
O
I
AVDD regulator output
AVSS
BRG+
BRG–
COMP
DACCAP
DVDD
DVDD_MEM
DVSS
FB+
23
15
14
13
6
Analog ground
Bridge drive, positive
Bridge drive, negative
Output amplifier compensation
DAC capacitor
O
O
O
—
I
3
DVDD regulator output
Power supply for EEPROM and OTP
Digital ground
2
32
12
11
10
18
17
21
22
Feedback, positive
FB–
I
Feedback, negative
GND
—
I
Ground
INP+
Resistive sensor positive input
Resistive sensor negative input
INP–
I
INT+
I
External temperature sensor positive input
External temperature sensor negative input
INT–
I
1, 4, 7, 19,
20,
24 to 31, 33
to 36
NU
—
Do not connect
OUT
8
5
O
I
DAC gain output
PWR
Input power supply
REFCAP
Thermal pad
16
—
O
—
ADC reference capacitor
Connect to analog ground
4
Copyright © 2014–2016, Texas Instruments Incorporated
PGA300
www.ti.com.cn
ZHCSF35A –OCTOBER 2014–REVISED JUNE 2016
6 Specifications
6.1 Absolute Maximum Ratings
(1)
see
MIN
–28
–0.3
MAX
33
UNIT
V
PWR
Supply voltage
Voltage at sensor input pins: INP+, INP–, INT+, INT–
2
V
Voltage at AVDD, AVSS, BRG+, BRG–, COMP, DACCAP, DVDD, DVDD_MEM,
DVSS, FB–, GATE, REFCAP
–0.3
3.6
V
Voltage at FB+ pin
Voltage at OUT pin
–2
VPWR + 0.3
33
V
V
-0.3
IPWR, short
on OUT pin
Supply current
25
mA
TJmax
Tstg
Maximum junction temperature
Storage temperature
155
150
°C
°C
–40
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
30
UNIT
VPWR
Power supply voltage
Slew rate
3.3
V
VDD = 0 to 30 V
0.5
V/µs
Power supply current - normal operation No load on BRG, no load on DAC
2.5
While EEPROM is being
Power supply current - EEPROM
programmed, no load on BRG, no
programming
IPWR
mA mA
9(1)
load on DAC
TA
Operating ambient temperature
–40
–40
150
140
°C
°C
Programming temperature
EEPROM
Start-up time (including analog and
digital)
VPWR ramp rate 0.5 V/µs
1
ms
nF
Capacitor on PWR pin
10
(1) Programming of the EEPROM results in an additional 6 mA of current on the PWR pin.
Copyright © 2014–2016, Texas Instruments Incorporated
5
PGA300
ZHCSF35A –OCTOBER 2014–REVISED JUNE 2016
www.ti.com.cn
6.4 Thermal Information
PGA300
RHH (VQFN)
36 PINS
30.6
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
16.4
5.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
5.4
RθJC(bot)
0.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics – Reverse Voltage Protection
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MAX
UNIT
V
Reverse voltage
–28
Voltage drop across reverse voltage
protection element
20
mV
6.6 Electrical Characteristics – Regulators
PARAMETER
AVDD voltage
DVDD voltage – operating
TEST CONDITIONS
MIN
TYP
3
UNIT
V
VAVDD
VDVDD
CAVDD = 100 nF
CDVDD = 100 nF
1.8
V
6.7 Electrical Characteristics – Internal Reference
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1.2
MAX
UNIT
V
High-voltage reference voltage(1)
Accurate reference voltage
Capacitor value on REFCAP pin
2.5
V
100
nF
(1) TEMP_DRIFT = [(Value at TEMP – Value at 25³C) / (Value at 25³C × ΔTEMP)] × 106
6.8 Electrical Characteristics – Bridge Sensor Supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BRG SUPPLY FOR RESISTIVE BRIDGE SENSORS
Bridge supply control bit = 0b00, no
load
2.5
2
V
V
V
VBRG+
VBRG–
–
Bridge supply control bit = 0b01, no
load
Bridge supply voltage
Bridge supply control bit = 0b10, no
load
1.25
IBRG
Current supply to the bridge
Capacitive load
1.5
2
mA
nF
CBRG
RBRG = 20 kΩ
6
Copyright © 2014–2016, Texas Instruments Incorporated
PGA300
www.ti.com.cn
ZHCSF35A –OCTOBER 2014–REVISED JUNE 2016
6.9 Electrical Characteristics – Temperature Sensor Supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ITEMP SUPPLY FOR TEMPERATURE SENSOR
Control bit = 0b000
Control bit = 0b001
25
50
µA
ITEMP
Current supply to temperature sensor Control bit = 0b010
Control bit = 0b011
100
500
OFF
Control bit = 0b1xx
CTEMP
Capacitive load
100
nF
Output impedance
15
MΩ
6.10 Electrical Characteristics – Internal Temperature Sensor
PARAMETER
TEST CONDITIONS
MIN
–40
TYP
MAX
150
UNIT
Temperature range
°C
6.11 Electrical Characteristics – P Gain (Chopper Stabilized)
PARAMETER
TEST CONDITIONS
00000, at dc
MIN
TYP
MAX
UNIT
5
5.48
5.97
6.56
7.02
8
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
9.09
10
10.53
11.11
12.5
13.33
14.29
16
17.39
18.18
19.05
20
Gain steps (5 bits)
V/V
22.22
25
30.77
36.36
40
44.44
50
57.14
66.67
80
100
133.33
200
400
Copyright © 2014–2016, Texas Instruments Incorporated
7
PGA300
ZHCSF35A –OCTOBER 2014–REVISED JUNE 2016
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Electrical Characteristics – P Gain (Chopper Stabilized) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Gain bandwidth product
10
MHz
f = 0.1 Hz to 2 kHz, gain = 400 V/V,
sampling rate = 128 µs, across
temperature
Input-referred noise density(1)
15
nV/√Hz
Input offset voltage
Input bias current
Frequency response
10
5
µV
nA
Gain = 400 V/V, <1 kHz
±0.1
%V/V
Depends
on
selected
gain,
bridge
Common-mode voltage range
V
supply and
sensor
(2)
span
Common-mode rejection ratio
Input impedance
fCM = 50 Hz at gain = 5 V/V
110
dB
10
MΩ
(1) Total input-referred noise including gain noise, ADC reference noise, ADC thermal noise, and ADC quantization noise
(2) Common Mode at P Gain Input and Output: There are two constraints:
(a) The single-ended voltage of the positive and negative pins at the P gain input must be between 0.3 V and 1.8 V
(b) The single-ended voltage of the positive and negative pins at the P gain output must be between 0.1 V and 2 V
6.12 Electrical Characteristics – P Analog-to-Digital Converter
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
V
Sigma-delta modulator frequency
ADC voltage input range
Number of bits
1
–2.5
2.5
16
bits
ADC 2s complement code for –2.5-
V differential input
8000hex
ADC 2s complement code for 0-V
differential input
0000hex
7FFFhex
ADC 2s complement code for 2.5-V
differential input
INL
Integral nonlinearity
±0.5
LSB
6.13 Electrical Characteristics – T Gain (Chopper Stabilized)
PARAMETER
TEST CONDITIONS
Gain control bits = 0b00 at dc
Gain control bits = 0b01
Gain control bits = 0b10
Gain control bits = 0b11
MIN
TYP
MAX
UNIT
1.33
2
Gain steps (2 bits)
V/V
5
20
350
Gain bandwidth product
Noise density(1)
kHz
f = 0.1 Hz to 100 Hz
at gain = 5 V/V, across temperature
110
nV/√Hz
Input offset voltage
Input bias current
Frequency response
95
5
µV
nA
Gain = 20 V/V, <100 Hz
0.335
%V/V
(1) Total input-referred noise including gain noise, ADC reference noise, ADC thermal noise, and ADC quantization noise
8
Copyright © 2014–2016, Texas Instruments Incorporated
PGA300
www.ti.com.cn
ZHCSF35A –OCTOBER 2014–REVISED JUNE 2016
Electrical Characteristics – T Gain (Chopper Stabilized) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Depends
on
selected
gain and
current
Common mode voltage range
(2)
supply
Common-mode rejection ratio
Input impedance
fCM = 50 Hz
110
dB
1
MΩ
(2) Common Mode at T Gain Input and Output: There are two constraints:
(a) The single-ended voltage of positive/negative pin at the T gain input should be between 5 m V and 1.8 V
(b) The single-ended voltage of positive/negative pin at the T gain output should be between 0.1 V and 2 V
6.14 Electrical Characteristics – T Analog-to-Digital Converter
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
V
Sigma-delta modulator frequency
ADC voltage input range
Number of bits
1
–2.5
2.5
16
bits
ADC 2s complement code for –2.5-V
differential input
2s complement
8000hex
LSB
LSB
ADC 2s complement code for 0-V
differential input
0000hex
7FFFhex
ADC 2s complement code for 2.5-V
differential input
LSB
LSB
INL
Integral nonlinearity
±0.5
6.15 Electrical Characteristics – One-Wire Interface
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
bits per
second
Communication Baud Rate(1)
600
9600
OWI_ENH
OWI_ENL
OWI_VIH
OWI_VIL
OWI_IOH
OWI_IOL
OWI activation high
5.95
V
V
OWI activation low
5.75
5.1
OWI transceiver Rx threshold for high
OWI transceiver Rx threshold for low
OWI transceiver Tx threshold for high
OWI transceiver Tx threshold for low
4.8
3.9
500
2
V
4.2
V
1379
5
µA
µA
(1) OWI over power line does not work if there is an LDO between the supply to the sensor and the PWR pin, or if the OWI high
and low voltages are greater than the regulated voltage.
6.16 Electrical Characteristics – DAC Output
PARAMETER
TEST CONDITIONS
Reference bit = 1
Reference bit = 0 (ratiometric)
MIN
TYP
1.25
MAX
UNIT
V
DAC reference voltage
DAC resolution
0.25 × VPWR
14
bits
6.17 Electrical Characteristics – DAC Gain
PARAMETER
TEST CONDITIONS
MIN
TYP
2
MAX
UNIT
2×
4×
4
Buffer gain (see Figure 16)
V/V
6.67×
10×
6.67
10
Copyright © 2014–2016, Texas Instruments Incorporated
9
PGA300
ZHCSF35A –OCTOBER 2014–REVISED JUNE 2016
www.ti.com.cn
Electrical Characteristics – DAC Gain (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
1001
1
MAX
UNIT
mA/mA
MHz
mV
Current loop gain
Gain-bandwidth product
Zero-code voltage (gain = 4×)
Full-code voltage (gain = 4×)
DAC code = 0000h, IDAC = 2.5 mA
DAC code is 1FFFh, IDAC = –2.5 mA
20
4.8
V
DAC code = 1FFFh , DAC code =
0000h
Output current
±2.5
mA
Short-circuit source current
Short-circuit sink current
DAC code = 1FFFh
DAC code = 0000h
Without compensation
With compensation
27
27
mA
mA
pF
100
100
Maximum capacitance
nF
6.18 Electrical Characteristics – Non-Volatile Memory
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Bytes
Cycles
ms
Size
128
Erase-write cycles
Programming time
Data retention
1000
8
EEPROM
1 8-byte page
10
Years
6.19 Electrical Characteristics – Diagnostics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
Oscillator circuit
supply overvoltage
threshold
OSC_PWR
_OV
3.3
V
Oscillator circuit
OSC_PWR supply
2.7
10
V
_UV
undervoltage
threshold
Resistive bridge
sensor supply
overvoltage
threshold
BRG_OV
%. VBRG
Resistive bridge
sensor supply
undervoltage
threshold
%Prog.
VBRG
BRG_UV
–10
AVDD overvoltage
threshold
AVDD_OV
AVDD_UV
DVDD_OV
DVDD_UV
3.3
2.7
2
V
V
V
V
AVDD
undervoltage
threshold
DVDD overvoltage
threshold
DVDD
undervoltage
threshold
1.53
Reference
overvoltage
threshold
REF_OV
REF_UV
2.75
2.25
V
V
Reference
undervoltage
threshold
10
Copyright © 2014–2016, Texas Instruments Incorporated
PGA300
www.ti.com.cn
ZHCSF35A –OCTOBER 2014–REVISED JUNE 2016
Electrical Characteristics – Diagnostics (continued)
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
PD2
PD1
P gain input
P_DIAG_P diagnostics
0
0
1
1
0
1
0
1
1
2
3
4
MΩ
U
pulldown resistor
value
INP+ and INP– each has threshold
comparator
THRS[2] THRS[1] THRS[0]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
72.5
70
VBRG = 2.5 V
P gain input
overvoltage
threshold value
65
INP_OV
% VBRG
90
VBRG = 2 V
87.5
82.5
100
95
VBRG = 1.25 V
INP+ and INP– each has threshold
comparator
THRS[2] THRS[1] THRS[0]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7.5
10.0
15.0
10.0
12.5
17.5
17.5
22.5
VBRG = 2.5 V
P gain input
undervoltage
threshold value
INP_UV
% VBRG
VBRG = 2.V
VBRG = 1.25 V
T gain input
overvoltage
INT_OV
INT+ and INT– each has threshold comparator
2.1
V
V
Output overvoltage
(single-ended)
threshold for P
gain
PGAIN_OV
2.25
Output
undervoltage
PGAIN_UV (single-ended)
threshold for P
gain
0.15
V
Output overvoltage
TGAIN_OV (single-ended)
threshold for T gain
2.25
0.15
V
V
Output
undervoltage
(single-ended)
TGAIN_UV
threshold for T gain
Open-wire leakage
HARNESS_ current 1. Open
2
µA
µA
FAULT1
PWR with pullup
on OUT
Open-wire leakage
HARNESS_ current 2. Open
20
FAULT2
GND with pulldown
on OUT
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6.20 Operating Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
Start-up time(1)
TEST CONDITIONS
No IIR filter,
MIN
TYP
180
MAX
UNIT
µs
Start-up time(2)
IIR filter = 1000 Hz
1158
128
µs
Output rate
µs
Response time(3)
Response time(4)
No IIR filter
211
µs
IIR filter = 1000 Hz
1050
0.2
µs
Absolute-voltage mode, overall accuracy 3 pressure - 1 temperature calibration,
%FSO
(PGA300 only, no sense element)(5)
overall accuracy calculated using points
different from points used for calibration
3 pressure - 3 temperature calibration,
input voltage not subject to temperature
variation, overall accuracy calculated
using points different from points used
for calibration
0.1
%FSO
%FSO
4 pressure - 4 temperature calibration,
input voltage not subject to temperature
variation, overall accuracy calculated
using points different from points used
for calibration
0.08
Ratiometric-voltage mode, overall
accuracy (PGA300, no sense
element)(5)
3 pressure - 1 temperature calibration,
overall accuracy calculated using points
different from points used for calibration
0.5
%FSO
%FSO
3 pressure - 3 temperature calibration,
input voltage not subject to temperature
variation, overall accuracy calculated
using points different from points used
for calibration
0.25
4 pressure - 4 temperature calibration,
input voltage not subject to temperature
variation, overall accuracy calculated
using points different from points used
for calibration
0.2
%FSO
Current mode, overall accuracy
(PGA300, no sense element)(5)
3 pressure - 1 temperature calibration,
overall accuracy calculated using points
different from points used for calibration
0.2
0.1
%FSO
%FSO
3 pressure - 3 temperature calibration,
input voltage not subject to temperature
variation, overall accuracy calculated
using points different from points used
for calibration
4 pressure - 4 temperature calibration,
input voltage not subject to temperature
variation, overall accuracy calculated
using points different from points used
for calibration
0.09
%FSO
(1) Time from power up to reach 90% of valid output
(2) Time from power up to reach valid output, including settling time
(3) Time to reach 90% of valid output
(4) Time to reach valid output, including settling time
(5) Sense element held at constant temperature while the PGA300 device was calibrated at –25ºC, 25ºC, 85ºC and 125ºC. Accuracy was
then measured at –40ºC, 50ºC and 150 ºC.
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6.21 Typical Characteristics
2800000
2600000
2400000
2200000
2000000
1800000
1600000
1400000
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (°C)
D003
Figure 1. Temperature Sensor Code vs Temperature
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7 Detailed Description
7.1 Overview
The PGA300 device can be used in a variety of applications. The most common ones are for pressure and
temperature measurement. Depending on the application, the device itself can be configured in different modes.
The following sections provide details regarding these configurations.
The PGA300 device is a high-accuracy, low-drift, low-noise, low-power, and easily programmable signal-
conditioner device for resistive bridge pressure and temperature sensing applications. The PGA300 device
implements a third-order temperature coefficient (TC) and nonlinearity (NL) algorithm to linearize the analog
output. The PGA300 device accommodates various sensing element types, such as piezoresistive, ceramic film,
and steel membrane. It supports the sensing element spans from 1 mV/V to 135 mV/V. The typical applications
supported are pressure sensor transmitter, transducer, liquid-level meter, flow meter, strain gauge, weight scale,
thermocouple, thermistor, 2-wire resistance thermometer (RTD), and resistive field transmitters. The device can
also be used in accelerometer and humidity sensor signal-conditioning applications.
The PGA300 device provides bridge excitation voltages of 2.5 V, 2 V, and 1.25 V, all ratiometric to the ADC
reference level. The PGA300 device has the unique one-wire interface (OWI) that supports communication and
configuration through the power-supply line during the calibration process. This feature minimizes the number of
wires needed for an application.
The PGA300 device contains two separated analog front-end (AFE) chains for resistive-bridge inputs and
temperature-sensing inputs. Each AFE chain has its own gain amplifier and a 16-bit ADC at a 7.8-kHz output
rate. The resistive-bridge input AFE chain consists of a programmable gain with 32 steps from 5 V/V to 400 V/V.
For the temperature-sensing AFE input chain, the PGA300 device provides a current source that can supply up
to 500 µA for optional external temperature sensing. This current source can also be used as constant-current
bridge excitation. The programmable gain in the temperature sensing chain has four steps from 1.33 V/V to 20
V/V. In addition, the PGA300 device integrates an internal temperature sensor which can be configured as the
input of the temperature-sensing AFE chain.
A 128-byte EEPROM is integrated in the PGA300 device to store the calibration coefficients and the PGA300
configuration settings as needed. The PGA300 device has a 14-bit DAC followed by a buffer gain stage of 2 V/V
to 10 V/V. The device supports industrial-standard ratiometric-voltage output, absolute-voltage output, and 4-mA
to 20-mA current loop.
The diagnostic function monitors the operating condition of the PGA300 device. The device can operate with a
3.3-V to 30-V power supply directly, without using an external LDO. The PGA300 device has a wide ambient-
temperature operating range from –40°C to 150°C. The package form is 6-mm × 6-mm 36-pin VQFN. Within this
small package size, the PGA300 device has integrated all the functions needed for resistive-bridge sensing
applications to minimize PCB area and simplify the overall application design.
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7.2 Functional Block Diagram
PWR
vdd
DVDD_MEM
AVSS
DVSS
Sensor Voltage Supply
Bridge Drive
Linear Regulators
AVDD Regulator
GND
AVDD
BRG+
BRG–
DVDD
DVDD Regulator
REF
REFCAP
Accurate Reference
(2.5 V, 10 ppm/°C)
P ADC
INP+
INP–
P Sigma-
Delta
Modulator
vP
P Gain
(5 Bits)
P Decimation
Filter
Channel Select
INT+
INT–
T ADC
T Sigma-
Delta
Modulator
vT
T Gain
(2 Bits)
T Decimation
Filter
vtint
Internal
Temperature
vdd
OWI Driver
tx
EEPROM
(Calibration Coefficients, Serial No.)
OWI
rx
Digital Compensation
req
DACCAP
FB+
Third-Order TC
and
vP
vT
Third-Order NL
Sensor
Compensation
vdd
IIR
Second-
Order Filter
DAC
+
–
OUT
DAC Gain
(2 Bits)
COMP
FB–
Diagnostics
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7.3 Feature Description
This section describes individual functional blocks of the PGA300 device.
7.3.1 Reverse-Voltage Protection Block
The PGA300 device includes a reverse-voltage protection block. This block protects the device from reverse-
battery conditions on the external power supply.
7.3.2 Linear Regulators
The PGA300 device has two main linear regulators: an AVDD regulator and a DVDD regulator. The AVDD
regulator provides the 3-V voltage source for internal analog circuitry, whereas the DVDD regulator provides the
1.8-V regulated voltage for the digital circuitry. The user must connect bypass capacitors of 100 nF each on the
AVDD and DVDD pins of the device.
7.3.3 Internal Reference
The PGA300 device has two internal references. These references are described in the following subsections.
7.3.3.1 High-Voltage Reference
The high-voltage reference is an inaccurate reference used in the diagnostic thresholds.
7.3.3.2 Accurate Reference
The accurate reference is used to generate reference voltage for the P ADC, T ADC and DAC. TI recommends
placing a 100-nF capacitor on the REFCAP pin to limit the bandwidth of reference noise.
The accurate reference buffer can be disabled by setting the ADC_EN_VREF bit in the ALPWR register to 0.
This allows the user to connect an external single-ended reference voltage to the REFCAP pin and thus provide
the reference voltage to the ADCs and the DAC. Note that the default power-up state of ADC_EN_VREF is such
that the reference buffer is disabled.
NOTE
The accurate reference is valid 50 µs after digital core starts running at power up.
7.3.4 BRG+ to BRG– Supply for the Resistive Bridge
The sensor voltage-supply block of the PGA300 device supplies power to the resistive-bridge sensor. The sensor
supply in the PGA300 device is configurable to a 2.5-V, 2-V, or 1.25-V nominal output supply using the
BRG_CTRL bits in BRG_CTRL register to accommodate bridge sense elements with different resistor values.
This nominal supply is ratiometric to the accurate reference as shown in Figure 2.
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Feature Description (continued)
100 nF
100 nF
100 nF
REFCAP
DVDD
AVDD
INT+
DVDD
Regulator
1.8 V
ITEMP
Buf
PWR
2.5 V
2.5 V
3 V
AVDD
Regulator
Ref
Buf
2.5 V
Reference
Reverse
Protection
MUX
2.5 V
BRG+
R1
R1
2 V
Buf
VBRG
Absolute Ratiometric
1.25 V
R
R
2.5 V
ADC
INP+
INP–
PGA
1.25 V
OUT
40 kΩ
DAC
Gain
DAC
DACCAP
3.3 nF
Figure 2. Bridge Supply and P ADC Reference Are Ratiometric
The sensor drive includes a switch. This switch can be used to turn off power to the sense element.
7.3.5 ITEMP Supply for the Temperature Sensor
The ITEMP block in PGA300 device supplies programmable current to an external temperature sensor such as
an RTD temperature probe or NTC or PTC thermistor. The temperature-sensor current source is ratiometric to
the accurate reference.
The value of the current can be programmed using the ITEMP_CTRL bits in the TEMP_CTRL register.
7.3.6 Internal Temperature Sensor
PGA300 device includes an internal temperature sensor whose voltage output is digitized by the T ADC and
made available to the microprocessor. This digitized value is used to implement temperature compensation
algorithms in software. Note that the voltage generated by the internal temperature sensor is proportional to the
junction temperature.
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Feature Description (continued)
Figure 3 shows the internal temperature sensor AFE.
VREF = 2.5 V
T
T
VPTAT
Gain
ADC
Figure 3. Temperature Sensor AFE
7.3.7 P Gain
P gain is designed with precision, low-drift, low-flicker-noise, chopper-stabilized amplifiers. P gain is implemented
as an instrument amplifier as shown in Figure 4.
The gain of this stage is adjustable using 5 bits in the P_GAIN_SELECT register to accommodate sense
elements with a wide range of signal spans.
PGA300
PGAIN_OPEN
INP+
+
-
To P ADC
-
INP–
+
Copyright © 2016, Texas Instruments Incorporated
Figure 4. P Gain
7.3.8 P Analog-to-Digital Converter
The P analog-to-digital converter digitizes the voltage output of the P-gain amplifier.
7.3.8.1 P Sigma-Delta Modulator for P ADC
The sigma-delta modulator for P ADC is a 1-MHz, second-order, 3-bit quantizing sigma-delta modulator.
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Feature Description (continued)
7.3.8.2 P Decimation Filter for P ADC
The pressure signal path output conversion time is 128 µs or an output rate of 7.8125 ksamples/s.
The output of the decimation filter in the pressure signal path is a 16-bit signed value. Some example decimation
output codes for given differential voltages at the input of the sigma-delta modulator are shown in Table 1.
Table 1. Input Voltage to Output Counts for the P ADC
SIGMA-DELTA MODULATOR
16-BIT NOISE-FREE
DIFFERENTIAL INPUT VOLTAGE
DECIMATOR OUTPUT
(V)
–2.5
–1.25
0
–32 768 (0x8000)
–16 384 (0xC000)
0 (0x0000)
1.25
2.5
16 383 (0x3FFF)
32 767 (0x7FFF)
7.3.9 T Gain
The device has the ability to perform temperature compensation via an internal or external temperature sensor.
The user can select the source of the temperature measurement with the TEMP_MUX_CTRL bits in
TEMP_CTRL register. Note that the device connects to an external temperature sensor via the INT+ and INT–
pins.
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The T gain block is constructed with a low-flicker-noise, low-offset, chopper-stabilized amplifier. The gain is
configurable with 2 bits in the T_GAIN_SELECT register. Figure 5 shows the T-gain amplifier topology.
PGA300
VREF = 2.5V
INT+
+
–
To T ADC
TSEM_N
–
INT–
TSEM_N
+
Copyright © 2016, Texas Instruments Incorporated
Figure 5. Temperature Sensor AFE
The T-gain amplifier can be configured for single-ended or differential operation using the TSEM_N bit in the
AMUX_CTRL register. Note that when the T-gain amplifier is set up for single-ended operation, the differential
voltage converted by the T ADC is with respect to ground. Table 2 shows the configuration that the user must
select for the different temperature sources.
Table 2. T-Gain Configuration
TEMPERATURE SOURCE
T GAIN CONFIGURATION
Single-ended
Internal temperature sensor
External temperature sensor with one terminal of the sensor connected to ground
External temperature sensor with neither terminal of the sensor connected to ground
Single-ended
Differential
The T-gain amplifier must be set up for either the single-ended or differential configuration, depending on the
source of signal to the T gain.
NOTE
When T GAIN is configured to measure the internal temperature-sensor output,
T GAIN must be configured to operate in single-ended mode and with a gain of 5
V/V.
7.3.10 T Analog-to-Digital Converter
The T analog-to-digital converter is for digitizing the T-gain amplifier output. The digitized value is available in the
TADC_DATA2 and TADC_DATA3 registers.
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7.3.10.1 T Sigma-Delta Modulator for T ADC
The sigma-delta modulator for T ADC is a 1-MHz, second-order, 3-bit quantizing sigma-delta modulator.
7.3.10.2 T Decimation Filters for T ADC
The temperature signal path contains a decimation filter with an internal output rate of 128 µs.
The output of the decimation filter in the temperature signal path is 16-bit signed value. Some example
decimation output codes for given differential voltages at the input of the sigma-delta modulator are shown in
Table 3.
Table 3. Input Voltage to Output Counts for T ADC
SIGMA-DELTA MODULATOR
16-BIT NOISE-FREE
DIFFERENTIAL INPUT VOLTAGE
DECIMATOR OUTPUT
–2.5 V
–1.25 V
0 V
–32 768 (0x8000)
–16 384 (0xC000)
0 (0x0000)
1.25 V
2.5 V
16 383 (0x3FFF)
32 767 (0x7FFF)
The nominal relationship between the device junction temperature and 16-bit T ADC code for T GAIN = 5 V/V is
shown in Equation 1
T ADC code = 25.9´ TEMP + 6680
where
TEMP is temperature in °C.
(1)
7.3.11 P GAIN and T GAIN Calibration
The P_GAIN value should be set based on the maximum bridge output voltage. The maximum bridge voltage is
the maximum sum of bridge offset and bridge span across the entire operating temperature range.
The T GAIN value should be set based on the temperature sense element. The specific values to be used are:
•
•
For the internal temperature sensor, set T_GAIN to 5 V/V gain
For an external temperature sensor such as a PTC thermistor, set T_GAIN to 20 V/V gain
7.3.12 One-Wire Interface (OWI)
The device includes an OWI digital communication interface. The function of OWI is to enable writes to and
reads from all memory locations inside the PGA300 device that are available for OWI access.
7.3.12.1 Overview of OWI
The OWI digital communication is a master-slave communication link in which the PGA300 device operates as a
slave device only. The master device controls when data transmission begins and ends. The slave device does
not transmit data back to the master until it is commanded to do so by the master.
The PWR pin of PGA300 device is used as OWI interface, so that when the PGA300 device is embedded inside
of a system module, only two pins are needed (PWR and GND) for communication. The OWI master
communicates with the PGA300 device by modulating the voltage on the PWR pin, whereas the PGA300 device
communicates with the master by modulating the current on the PWR pin. The OWI master activates OWI
communication by generating an activation pulse on the PWR pin.
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Figure 6 shows a functional equivalent circuit for the structure of the OWI circuitry.
C and S
Registers
Address and
Data Lines
PWR
Enable
OWI
Controller
XCVR SW
OWI
Transceiver
OWI_ACT
Digital
Compensation
Tx
Rx
OWI_REQ
OWI_REQ_INT
OWI_REQ
ESFR
XCVR SW
C and S
Registers
Address and
Data Lines
5.75 V
OWI_REQ
OWI_REQ Deglitch
Filter
OWI
Activation
Comparator
Figure 6. OWI System Components
7.3.12.2 Activating and Deactivating the OWI Interface
7.3.12.2.1 Activating OWI Communication
The OWI master initiates OWI communication by generating an OWI activation-pulse sequence on the PWR
pin. When the PGA300 device receives a valid OWI activation-pulse sequence, it prepares itself for OWI
communication. Notice that after the valid OWI activation-pulse sequence is received, the logic checks on the
EEPROM lock status. If the EEPROM is locked, the sequence 0x5555 must be sent within 100 ms after the end
of the activation-pulse sequence.
PWR Voltage
PWR=5.95 V
>1 ms
PWR=5.75 V
PWR=4.8 V
PWR=4.2 V
OWI
COMMUNICATION
<100 ms
100 ms<time<200 ms
>100 ms
Figure 7. OWI Activation Using Overvoltage Drive
7.3.12.2.2 Deactivating OWI Communication
In order to deactivate OWI communication and restart the compensation engine inside the PGA300 device (if it
was in reset), the following two steps must be performed by the OWI master:
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•
•
The OWI_XCR_EN bit in the DIG_IF_CTRL register must be set to 0. This turns off the OWI transceiver.
The compensation engine reset should be de-asserted by writing 0 to the COMPENSATION_RESET bit in
the COMPENSATION_CONTROL register.
7.3.12.3 OWI Protocol
7.3.12.3.1 OWI Frame Structure
7.3.12.3.1.1 Standard Field Structure
Data is transmitted on the one-wire interface in byte-sized packets. The first bit of the OWI field is the start bit.
The next 8 bits of the field are data bits to be processed by the OWI control logic. The final bit in the OWI field is
the stop bit. A group of fields make up a transmission frame. A transmission frame is composed of the fields
necessary to complete one transmission operation on the one-wire interface. The standard field structure for a
one-wire field is shown in Figure 8
Standard Field
Figure 8. Standard OWI Field
7.3.12.3.1.2 Frame Structure
A complete one-wire data transmission operation is done in a frame with the structure is shown in Figure 9.
Command
Field
1st Data
Field
Nth Data
Field
Sync Field
cmd[0:7]
data-1[0:7]
data-N[0:7]
Inter-Field
Wait Time
(One Bit-Time)
Figure 9. OWI Transmission Frame, N = 1 to 8
Each transmission frame must have a synchronization field and a command field followed by zero to a maximum
of eight data fields. The sync field and command fields are always transmitted by the master device. The data
fields may be transmitted either by the master or the slave, depending on the command given in the command
field. It is the command field which determines direction of travel of the data fields (master-to-slave or slave-to-
master). The number of data fields transmitted is also determined by the command in the command field. The
inter-field wait time is optional and may be necessary for the slave or the master to process data that has been
received.
NOTE
If the OWI remains idle in either the logic-0 or logic-1 state for more than 15 ms, then the
PGA300 communication resets and requires a sync field as the next data transmission
from the master.
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7.3.12.3.1.3 Sync Field
The sync field is the first field in every frame that is transmitted by the master. The sync field is used by the slave
device to compute the bit width transmitted by the master. This bit width is used to receive accurately all
subsequent fields transmitted by the master. The format of the sync field is shown in Figure 10.
Sync Field
Measured Time
Figure 10. OWI Sync Field
NOTE
Consecutive sync-field bits are measured and compared to determine if a sync field is
being transmitted to the PGA300 device is valid. If the difference in bit widths of any two
consecutive SYNC field bits is greater than ±25%, then the PGA300 device ignores the
rest of the OWI frame; that is, the PGA300 device does not respond to the OWI message.
7.3.12.3.1.4 Command Field
The command field is the second field in every frame sent by the master. The command field contains
instructions about what to do with and where to send the data that is transmitted to the slave. The command field
can also instruct the slave to send data back to the master during a read operation. The number of data fields to
be transmitted is also determined by the command in the command field. The format of the command field is
shown in Figure 11.
Command Field
cmd[0:7]
Figure 11. OWI Command Field
7.3.12.3.1.5 Data Fields
After the master has transmitted the command field in the transmission frame, zero or more data fields are
transmitted to the slave (write operation) or to the master (read operation). The data fields can be raw EEPROM
data or address locations in which to store data. The format of the data is determined by the command in the
command field. The typical format of a data field is shown in Figure 12.
Data Field
data[0:7]
Figure 12. OWI Data Field
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7.3.12.3.2 OWI Commands
The following is the list of five OWI commands supported by PGA300:
1. OWI write
2. OWI read initialization
3. OWI read response
4. OWI burst write of EEPROM cache
5. OWI burst read from EEPROM cache
7.3.12.3.2.1 OWI Write Command
FIELD
DESCRIPTION
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LOCATION
Command field
Data field 1
Basic write command
Destination address
Data byte to be written
0
P2
A6
D6
P1
A5
D5
P0
A4
D4
0
0
0
1
A7
D7
A3
D3
A2
D2
A1
D1
A0
D0
Data field 2
The P2, P1, and P0 bits in the command field determine the memory page that is being accessed by the OWI.
The memory page decode is shown in Table 4.
Table 4. OWI Memory Page Decode
P2
0
P1
0
P0
0
MEMORY PAGE
Reserved
Reserved
0
0
1
Control and status registers, DI_PAGE_ADDRESS
= 0x02
0
1
0
0
1
1
1
1
0
0
1
1
0
1
0
Reserved
Reserved
EEPROM cache
Reserved
Control and status registers, DI_PAGE_ADDRESS
= 0x07
1
1
1
7.3.12.3.2.2 OWI Read Initialization Command
FIELD
DESCRIPTION
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LOCATION
Command field
Data field 1
Read initialization
command
0
P2
A6
P1
A5
P0
A4
0
0
1
0
Fetch address
A7
A3
A2
A1
A0
The P2, P1, and P0 bits in the command field determine the memory page that is being accessed by the OWI.
The memory page decode is shown in Table 4.
7.3.12.3.2.3 OWI Read-Response Command
FIELD
LOCATION
DESCRIPTION
BIT 7
0
BIT 6
1
BIT 5
1
BIT 4
1
BIT 3
0
BIT 2
0
BIT 1
1
BIT 0
1
Command field
Read-response command
Data retrieved (OWI drives
data out)
Data field 1
D7
D6
D5
D4
D3
D2
D1
D0
The P2, P1, and P0 bits in the command field determine the memory page that is being accessed by the OWI.
The memory page decode is shown in Table 4.
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7.3.12.3.2.4 OWI Burst-Write Command (EEPROM Cache Access)
FIELD
DESCRIPTION
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LOCATION
Command field
Data field 1
EE_CACHE write-command
cache bytes (0–7)
1
1
0
1
0
0
0
0
First data byte to be written
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Second data byte to be
written
Data field 2
Data field 3
Data field 4
Data field 5
Data field 6
Third data byte to be written
Fourth data byte to be written
Fifth data byte to be written
Sixth data byte to be written
D7
D7
D7
D7
D6
D6
D6
D6
D5
D5
D5
D5
D4
D4
D4
D4
D3
D3
D3
D3
D2
D2
D2
D2
D1
D1
D1
D1
D0
D0
D0
D0
Seventh data byte to be
written
Data field 7
Data field 8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Eighth data byte to be written
7.3.12.3.2.5 OWI Burst Read Command (EEPROM Cache Access)
FIELD
LOCATION
DESCRIPTION
BIT 7
1
BIT 6
1
BIT 5
0
BIT 4
1
BIT 3
0
BIT 2
0
BIT 1
1
BIT 0
1
Burst-read response (8
bytes)
Command field
First data byte retrieved
EEPROM cache byte 0
Data field 1
Data field 2
Data field 3
Data field 4
Data field 5
Data field 6
D7
D7
D7
D7
D7
D7
D6
D6
D6
D6
D6
D6
D5
D5
D5
D5
D5
D5
D4
D4
D4
D4
D4
D4
D3
D3
D3
D3
D3
D3
D2
D2
D2
D2
D2
D2
D1
D1
D1
D1
D1
D1
D0
D0
D0
D0
D0
D0
Second data byte retrieved
EEPROM cache byte 1
Third data byte retrieved
EEPROM cache byte 2
Fourth data byte retrieved
EEPROM cache byte 3
Fifth data byte retrieved
EEPROM cache byte 4
Sixth data byte retrieved
EEPROM cache byte 5
Seventh data byte
retrieved
EEPROM cache byte 6
Data field 7
Data field 8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Eighth data byte retrieved
EEPROM cache byte 7
7.3.12.3.3 OWI Operations
7.3.12.3.3.1 Write Operation
The write operation on the one-wire interface is fairly straightforward. The command field specifies the write
operation, where the subsequent data bytes are to be stored in the slave, and how many data fields are going to
be sent. Additional command instructions can be sent in the first few data fields if necessary. The write operation
is illustrated in Figure 13.
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Command
Field
1st Data
Field
Nth Data
Field
Sync Field
(To Slave)
Write Cmd
(To Slave)
Write Data
(To Slave)
Write Data
(To Slave)
Inter-Field
Wait Time
Figure 13. Write Operation, N = 1 to 8
7.3.12.3.3.2 Read Operation
The read operation requires two consecutive transmission frames to move data from the slave to the master. The
first frame is the read-initialization frame. It tells the slave to retrieve data from a particular location within the
slave device and prepare to send it over the OWI. The data location may be specified in the command field or
may require additional data fields for complete data-location specification. The data is not sent until the master
commands it to be sent in the subsequent frame called the read-response frame. During the read-response
frame, the data direction changes from master → slave to slave → master immediately after the read response
command field is sent. Enough time elapses between the command field and data field to allow the signal drivers
to change direction. This wait time is 20 µs, and the timer for this wait time is located on the slave device. After
this wait time is complete, the slave transmits the requested data. The master device is expected to have
switched its signal drivers and is ready to receive data. The read frames are shown in Figure 14.
Command
Field
1st Data
Field
Nth Data
Field
Sync Field
READ_INIT
(To Slave)
Opt Data
Opt Data
(To Slave)
(To Slave)
(To Slave)
Inter-Field
Wait Time
Figure 14. Read-Initialization Frame, N = 1 to 8
1st Data
Field
Command
Field
Nth Data
Field
Sync Field
(To Slave)
RD_RESP
Read Data
(To Master)
Read Data
(To Slave)
(To Master)
Data Changes Direction Between
Command Field and First Data Field
Inter-Field
Wait Time
Figure 15. Read-Response Frame, N = 1 to 8
7.3.12.3.3.3 EEPROM Burst Write
The EEPROM burst write is used to write 8 bytes of data to the EEPROM cache using one OWI frame to allow
fast programming of EEPROM. Note that the EEPROM page must be selected before transferring the contents of
the EEPROM memory cells to the EEPROM cache.
7.3.12.3.3.4 EEPROM Burst Read
The EEPROM burst read is used to read 8 bytes of data from the EEPROM cache using one OWI frame to allow
for fast reading of the EEPROM cache contents. The read process is used to verify the writes to the EEPROM
cache.
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7.3.12.4 OWI Communication-Error Status
The PGA300 device detects errors in OWI communication. The OWI_ERROR_STATUS_LO and
OWI_ERROR_STATUS_HI registers contain OWI communication error bits. The communication errors detected
include
•
•
•
•
Out-of-range communication baud rate
Invalid SYNC field
Invalid STOP bits in command and data
Invalid OWI command
7.3.13 DAC Output
The device includes a 14-bit digital-to-analog converter that produces an absolute output voltage with respect to
the accurate reference voltage or a ratiometric output voltage with respect to the PWR supply.
When the microprocessor undergoes a reset, the DAC registers are driven to the 0x000 code.
7.3.13.1 Ratiometric vs Absolute
The DAC output can be configured to be either in ratiometric-to-PWR mode or independent-of-PWR (or absolute)
mode using the DAC_RATIOMETRIC bit in DAC_CONFIG.
NOTE
In ratiometric mode, changes in the VPWR voltage result in a proportional change in the
output voltage because the current reference for the DAC is derived from VPWR
.
7.3.14 DAC Gain
The DAC gain buffer is a configurable buffer stage for the DAC output. The DAC gain amplifier can be configured
to operate in voltage amplification mode for voltage output or current amplification mode for 4-mA to 20-mA
applications. In voltage output mode, the DAC gain can be configured for a specific gain value by setting the
DAC_GAIN bits in the DAC_CONFIG register to a specific value as shown in Figure 16. The DAC gain can be
configured to one of four possible gain configurations using the 2-bit DAC_GAIN field.
The final stage of DAC gain is connected to PWR and ground, thus providing the ability to drive the VOUT voltage
close to the VPWR voltage.
The DAC gain buffer also implements a COMP pin in order to allow implementing compensation when driving
large capacitive loads.
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PWR
40 kΩ
VDAC
+
OUT
S1
-
40 kΩ
COMP
FB–
Open
2 V/V
S5
75 kΩ
S0
37.5 kΩ
15 kΩ
4 V/V
6.67 V/V
10 V/V
7.5 kΩ
15 kΩ
40 Ω
FB+
DACCAP
Figure 16. PGA300 Output Buffer
7.3.15 Memory
7.3.15.1 EEPROM Memory
Figure 17 shows the EEPROM structure. The contents of the EEPROM must be transferred to the EEPROM
cache before writes; that is, the EEPROM can be programmed 8 bytes at a time. EEPROM reads occur without
the EEPROM cache.
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Read DATA_OUT[31:0]
Digital
Compensation
Cache
ADDRESS[3:0]
EEPROM
Program
DATA_OUT[63:0]
EEPROM
Memory
Cells
EEPROM
Cache
(8 Bytes, 1 ´ 64 Bits)
(128 Bytes, 16 ´ 64 Bits)
Cache Write
DATA_IN[7:0]
Digital Interface
OWI
Read DATA_OUT[7:0]
Figure 17. Structure of the EEPROM Interface
7.3.15.1.1 EEPROM Cache
The EEPROM cache serves as temporary storage of data being transferred to selected EEPROM locations
during the programming process.
7.3.15.1.2 EEPROM Programming Procedure
For programming the EEPROM, the EEPROM is organized in 16 pages of 8 bytes each. The EEPROM memory
cells are programmed by writing to the 8-byte EEPROM cache. The contents of the cache are transferred to
EEPROM memory cells by selecting the EEPROM memory page.
1. Select the EEPROM page by writing the upper 4 bits of the 7-bit EEPROM address to the
EEPROM_PAGE_ADDRESS register.
2. Load the 8-byte EEPROM cache by writing to the EEPROM_CACHE register. Note that all 8 bytes must be
loaded into the EEPROM_CACHE register.
3. Set the ERASE_AND_PROGRAM bit in the EEPROM_CTRL register. Setting this bit automatically erases
the selected EEPROM memory page and programs it with the contents of the EEPROM_CACHE register.
Alternatively, the user can erase by writing 1 to the ERASE bit in the EEPROM_CTRL register, followed by
writing 1 to the PROGAM bit in the EEPROM_CTRL register once the erase is complete. The status of the
erase and program operations can be monitored through the EEPROM_STATUS register.
7.3.15.1.3 EEPROM Programming Current
The EEPROM programming process results in an additional 6-mA current on the PWR pin for the duration of
programming.
7.3.15.1.4 CRC
The last byte of the EEPROM memory is reserved for the CRC. This CRC value covers all data in the EEPROM
memory. Every time the last byte is programmed, the CRC value is automatically calculated and validated. The
validation process checks the calculated CRC value with the last byte programmed in the EEPROM memory cell.
If the calculated CRC matches the value programmed in the last byte, the CRC_GOOD bit is set in the
EEPROM_CRC_STATUS register.
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The CRC check can also be initiated at any time by setting the CALCULATE_CRC bit in the EEPROM_CRC
register. The status of the CRC calculation is available in the CRC_CHECK_IN_PROG bit in the
EEPROM_CRC_STATUS register, whereas the result of the CRC validation is available in the CRC_GOOD bit in
the EEPROM_CRC_STATUS register.
The CRC calculation pseudo code is as follows:
currentCRC8 = 0xFF; // Current value of CRC8
for NextData
D = NextData;
C = currentCRC8;
begin
nextCRC8_BIT0 = D_BIT7 ^ D_BIT6 ^ D_BIT0 ^ C_BIT0 ^ C_BIT6 ^ C_BIT7;
nextCRC8_BIT1 = D_BIT6 ^ D_BIT1 ^ D_BIT0 ^ C_BIT0 ^ C_BIT1 ^ C_BIT6;
nextCRC8_BIT2 = D_BIT6 ^ D_BIT2 ^ D_BIT1 ^ D_BIT0 ^ C_BIT0 ^ C_BIT1 ^ C_BIT2 ^ C_BIT6;
nextCRC8_BIT3 = D_BIT7 ^ D_BIT3 ^ D_BIT2 ^ D_BIT1 ^ C_BIT1 ^ C_BIT2 ^ C_BIT3 ^ C_BIT7;
nextCRC8_BIT4 = D_BIT4 ^ D_BIT3 ^ D_BIT2 ^ C_BIT2 ^ C_BIT3 ^ C_BIT4;
nextCRC8_BIT5 = D_BIT5 ^ D_BIT4 ^ D_BIT3 ^ C_BIT3 ^ C_BIT4 ^ C_BIT5;
nextCRC8_BIT6 = D_BIT6 ^ D_BIT5 ^ D_BIT4 ^ C_BIT4 ^ C_BIT5 ^ C_BIT6;
nextCRC8_BIT7 = D_BIT7 ^ D_BIT6 ^ D_BIT5 ^ C_BIT5 ^ C_BIT6 ^ C_BIT7;
end
currentCRC8 = nextCRC8_D8;
endfor
NOTE
The EEPROM CRC calculation is complete 340 µs after the digital core starts running at
power up.
7.3.15.2 Control and Status Registers Memory
The digital compensator uses the Control and Status registers to interact with the analog blocks of the device.
7.3.16 Diagnostics
The PGA300 device implements the diagnostics described in the following table:
DIAGNOSTICS DESCRIPTION
Digital-compensation-logic execution-timing error
Digital-compensation-logic checksum error
EEPROM is corrupted or EEPROM CRC = 0
ACTION
DAC is disabled and compensation logic is set to reset
DAC is disabled and compensation logic is set to reset
DAC code is driven to 0 code
DAC output is driven to the value determined by the FAULT register in
EEPROM
Power-supply and signal-chain errors
All the foregoing diagnostics can be enabled by setting the DIAG_ENABLE register in EEPROM to a non-zero
value. To disable diagnostics, set the DIAG_ENABLE register in EEPROM to 0.
7.3.16.1 Power Supply Diagnostics
The PGA300 device includes circuits to monitor the reference and power supply for faults. Specifically, the
following signals are monitored are:
•
AVDD voltage
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•
•
•
•
DVDD voltage
Bridge supply voltage
Internal oscillator supply voltage
Reference output voltage
Electrical Characteristics – Diagnostics lists the voltage thresholds for each of the power rails.
7.3.16.2 Signal Chain Faults
The PGA300 device includes circuits to monitor the P and T signal chains for faults. This section describes the
faults monitored by the PGA300 device.
7.3.16.2.1 P Gain and T Gain Input Faults
The PGA300 device includes circuits to monitor for sensor connectivity faults. Specifically, the device monitors
the bridge sensor pins for opens (including loss of connection from the sensor), short to ground, and short to
sensor supply. The monitoring is accomplished by comparing the voltage at INP+ and INP– pins with the
overvoltage and undervoltage thresholds described in Electrical Characteristics – Diagnostics.
The device also includes an overvoltage monitor at the INT+ and INT– pins through the use of 1-MΩ pullup
resistors.
Figure 18 shows the block diagram of the P gain and T gain input faults.
32
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PGA300
OV
OV
UV
VINP_OV
VINP_UV
UV
PGAIN_OPEN
INP+
INP–
P Gain
(5 Bits)
To P ADC
OV
OV
VINT_OV
AVDD
INT+
INT–
T Gain
(5 Bits)
To T ADC
Copyright © 2016, Texas Instruments Incorporated
Figure 18. Block Diagram of P Gain and T Gain Diagnostics
The bridge-sensor connectivity faults are detected through the use of an internal pulldown resistor. The value of
the pulldown resistor and the threshold can be configured using the AFEDIAG_CFG EEPROM register. Table
Table 5 describes the possible configurations.
Table 5. Definition of AFEDIAG_CFG EEPROM Register
BITS
DESCRIPTION
0: PD1
1: PD2
See Electrical Specifications Electrical Characteristics – Diagnostics
2: THRS[0]
3: THRS[1]
4: THRS[2]
See Electrical Specifications Electrical Characteristics – Diagnostics
1: Disables pulldown resistors used for open and short diagnostics on the INP+ and INP– pins
0: Enables pulldown resistors used for open and short diagnostics on the INP+ and INP– pins
5: DIS_R_P
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Table 5. Definition of AFEDIAG_CFG EEPROM Register (continued)
1: Disables pullup resistors used for open and short diagnostics on the INT+ and INT– pins
0: Enables pullup resistors used for open and short diagnostics on the INT+ and INT– pins
6: DIS_R_T
7:
—
7.3.16.2.2 P Gain and T Gain Output Diagnostics
The PGA300 device includes modules that verify that the output signal of each gain is within a certain range.
This ensures that gain stages in the signal chain are working correctly.
PGA300
OV
PGAIN_OV
OV
UV
PGAIN_UV
UV
INP+
P Gain
To P ADC
(5 Bits)
INP–
OV
TGAIN_OV
OV
UV
TGAIN_UV
UV
INT+
T Gain
To T ADC
(2 Bits)
INT–
Copyright © 2016, Texas Instruments Incorporated
Figure 19. Block Diagram of P Gain and T Gain Output Diagnostics
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7.3.16.2.3 Masking Signal Chain Faults
The signal chain diagnostics can be selectively enabled and disabled using the bits in the AFEDIAG_MASK
register in EEPROM. Table Table 6 describes the mask bits. Setting a bit to 1 enables detection of the
corresponding fault and setting the bit to 0 disables the detection of corresponding fault.
Table 6. Signal Chain Fault Masking Bits
BIT
0
DESCRIPTION
INP+ or INP– overvoltage
INP+ or INP– unvervoltage
INT+ or INT– overvoltage
N/A
1
2
3
4
P GAIN output overvoltage
P GAIN output undervoltage
T GAIN output overvoltage
T GAIN output undervoltage
5
6
7
7.3.16.2.4 Fault Detection Timing
The PGA300 fault-monitoring circuits monitor faults either at power up or periodically. Table 7 describes the fault-
detection timing.
Table 7. Fault Detection Timing
MINIMUM TIME AFTER
FAULT OCCURS
MAXIMUM TIME AFTER
FAULT OCCURS
FAULT
POWER UP OR RUN TIME
Digital-compensation execution-timing error
Digital-compensation checksum error
Run time
Run time
500 ms
500 ms
—
—
Power up only (EEPROM is
accessed only at power up)
EEPROM is corrupted or EEPROM CRC = 0
Power supply and signal chain errors
N/A
N/A
Run time
8 ms
16 ms
7.3.17 Digital Compensation and Filter
The PGA300 device implements a third-order TC and NL correction of the pressure and temperature inputs. The
corrected output is then filtered using a second-order IIR filter and then written to the DAC as shown in
Figure 20.
Digital Compensation
Digital
Offset
INP+
16
Bits
16
Bits
P Gain,
P ADC
Digital
Gain
+
INP–
DAC
Filtered
14 Bits
3rd-Order
TC and NL
Sensor
OUT
DAC
14 Bits
DAC
14 Bits
IIR 2nd-
Order Filter
DAC,
DAC Gain
Clamping
Compensation
INT+
INT–
16
Bits
T Gain,
T ADC
16
Bits
Digital
Gain
+
Digital
Offset
Figure 20. Digital Transfer Block Diagram
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7.3.17.1 Digital Gain and Offset
The digital compensation implements digital gain and offset for both pressure and temperature. The equations
are:
P = a0(P ADC + b0)
T = a1(T ADC + b1)
where
a0 and a1 are the digital gain
b0 and b1 are the digital offset
P is the pressure
T is the temperature
P ADC is the pressure digital output
T ADC is the temperature digital output
For high-offset sensors or sensor bridges with a low or high common mode, it may be useful to amplify and offset
the P ADC value in the digital domain. The PGA300 device allows the ability to cancel the offset and amplify the
signal further before being used in the compensation equation. The determination of the digital gain and offset
values is implemented automatically by the PGA300 GUI.
7.3.17.2 TC and NL Correction
The digital compensation equation is as follows:
DAC = (h0 + h1 × T + h2 × T2 + h3 × T3) + (g0 + g1 × T + g2 × T2 + g3 × T3) × P + (n0 + n1 × T + n2 × T2 + n3 × T3) × P2 +
(m0 + m1 × T + m2 × T2 + m3 × T3) × P3
(2)
where
DAC = Digitally compensated value at the input of the DAC
hx, gx, nx and mx are TC and NL compensation coefficients programmed in EEPROM
P is pressure
T is temperature
7.3.17.2.1 TC and NL Coefficients
The PGA300 device implements third-order TC and NL compensation of the bridge offset, bridge span, and
bridge nonlinearity. The equation has 16 coefficients, and hence requires at least 16 different measurement
points to compute a unique set of 16 coefficients. The TC-compensated DAC output equation is as follows:
DAC = (h0 + h1T + h2T2 + h3T3) + (g0 + g1T + g2T2 + g3T3) × P + (n0 + n1T + n2T2 + n3T3) × P2 + (m0 + m1T + m2T2 +
m3T3) × P3
(3)
The 16 different P ADC and T ADC measurements can be made, for example, at four temperatures and at four
different pressures. Note that
•
•
P GAIN and T GAIN values must be set to a fixed value for all measurements.
At each measurement point, the P ADC value and the T ADC value must be recorded in order to compute the
16 coefficients.
•
Sometimes, it may be expensive to measure P ADC and T ADC at different temperatures and pressures. In
this case, there are three approaches:
–
–
Use a model of the bridge to estimate P ADC and T ADC measurements instead of actually measuring.
Use batch modeling, in which a family of sense elements is characterized across temperature, and the TC
coefficients of the compensation equation are determined prior to calibration. On a production line,
measurements are made at a limited number of temperature and pressure set points, and coefficients are
adjusted accordingly. Discuss with TI application engineers for details.
–
Reduce the number of coefficients by reducing the order of TC compensation. Discuss the procedure to
use fewer coefficients with TI application engineers.
7.3.17.2.1.1 No TC and NL Coefficients
The equation for P ADC-to-DAC conversion is as follows:
DAC = H0EE + G0EE × P ADC
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Table 8. Coefficient Values for No TC and NL Compensation
COEFFICIENT
VALUE (HEX)
(1)
h0
h1
h2
h3
g0
g1
g2
g3
n0
n1
n2
n3
m0
m1
m2
m3
H0EE
0x0000
0x0000
0x0000
(1)
G0EE
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
(1) H0EE and G0EE are the values stored in EEPROM, which are 214 times the actual H0 and G0 coefficients.
Consider an example of scaling the positive half of the 16-bit P ADC to a 14-bit DAC value. In this case, H0 = 0
and G0 = 0.5. Therefore, H0EE = 0, and G0EE = 213.
7.3.17.2.2 TC Compensation Using the Internal Temperature Sensor
Temperature compensation can be performed using the internal temperature sensor with T GAIN = 5 V/V gain.
The internal temperature ADC values at the different temperatures are:
Table 9. T ADC Value for the Internal Temperature Sensor
TEMPERATURE
T ADC VALUE (HEX VALUE)
–40°C
0°C
0x16C9
0x1ACF
0x29E5
150°C
For T ADC at intermediate temperatures, use linear interpolation.
7.3.17.3 Clamping
The output of the digital compensation is clamped. The low and high clamp values are programmable using the
LOW_CLAMP and HIGH_CLAMP registers in the EEPROM. In addition, a normal operating output can be
configured using the NORMAL_LOW and NORMAL_HIGH registers in the EEPROM. Figure 21 shows an
example of the clamping feature for a 0-V to 5-V output operational mode. In a similar way, the output of the
compensation can be configured when the 4-mA to 20-mA operational mode is used. In such case, however, the
LOW_CLAMP value must be larger than the maximum current needed for normal operation of the device.
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5 V
Diagnostics
High Clamp
HIGH_CLAMP, 4.75 V
NORMAL_HIGH, 4.5 V
Normal Pressure
NORMAL_LOW, 0.5 V
LOW_CLAMP, 0.25 V
0 V
Low Clamp
Diagnostics
Figure 21. Example of Clamping the Digital Compensation Output
7.3.17.4 Filter
The IIR filter is as follows:
w(n) = (a0 × DAC(n) + a1 × w(n – 1) + a2w(n – 2))
DACF(n) = (b0 × w(n) + b1 × w(n – 1) + b2w(n – 2)
where a0, a1, a2, b0, b1, and b2 are the IIR filter coefficients, DAC(n) is the DAC output prior to the IIR filter, and
DACF(n) is the output of the PGA300 device after the second-order IIR filter.
7.3.18 Filter Coefficients
7.3.18.1 No Filtering
If filtering must be disabled, set a0 = 0x0000.
7.3.18.2 Filter Coefficients for P ADC Sampling Rate = 128 µs
Table 10. Filter Cutoff Frequency and Filter Coefficients
CUTOFF
FREQUENCY
(Hz)
a0 (Hex)
a1 (Hex)
a2 (Hex)
b0 (Hex)
b1 (Hex)
b2 (Hex)
0B01
600
4000
4000
4000
4000
4000
4000
4000
AAA1
2060
0B01
1602
700
B169
B818
BEAE
C52D
CB95
D1EA
1CEE
19E0
172D
14CE
12BC
10F2
0E57
11F8
15DB
19FB
1E52
22DC
1CAF
23F0
2BB7
33F6
3CA3
45B8
0E57
11F8
15DB
19FB
1E52
22DC
800
900
1000
1100
1200
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Table 10. Filter Cutoff Frequency and Filter Coefficients (continued)
CUTOFF
FREQUENCY
(Hz)
a0 (Hex)
a1 (Hex)
a2 (Hex)
b0 (Hex)
b1 (Hex)
b2 (Hex)
2798
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
4000
4000
4000
4000
4000
4000
4000
4000
4000
4000
4000
4000
4000
D82D
0F6A
2798
4F2F
DE61
E487
EAA3
F0B6
F6C3
FCCC
02D4
08DD
0EE9
14FC
1B17
213C
0E21
0D14
0C3F
0BA1
0B37
0B02
0B01
0B33
0B99
0C33
0D05
0E0F
2C82
319B
36E2
3C56
41FA
47CE
4DD4
540F
5A82
612F
681B
6F4B
5905
6336
6DC4
78AD
83F4
8F9C
9BA9
A81F
B504
C25E
D037
DE96
2C82
319B
36E2
3C56
41FA
47CE
4DD4
540F
5A82
612F
681B
6F4B
7.4 Device Functional Modes
There are two main functional modes for the PGA300 device: current (4-mA to 20-mA loop) and voltage modes.
Depending on which mode is being used, the external components and connections are slightly different.
7.4.1 Voltage Mode
When configured in this mode, the FB– pin must be connected to the OUT pin. If the OUT pin is driving a large
capacitive load, a compensation capacitor can be connected to the COMP pin and an isolation resistor can be
placed between the OUT and FB– pins. The FB+ pin is not used in voltage mode.
7.4.2 Current Mode
When configured in this mode, the OUT pin is driving the base of a bipolar junction transistor (BJT) as shown in
图 40. The COMP pin is connected to the emitter of the BJT and the FB+ pin is connected to the return terminal
of the supply. The FB– pin is not used in current mode.
7.5 Register Maps
7.5.1 Register Settings
Before the PGA300 device can be used in any application, the device must be configured by setting various
control registers to the desired values. Table 11 lists all the registers that must be configured and their respective
default configurations. Note that the registers are configured by writing to the appropriate EEPROM addresses
listed in the Control and Status Registers section.
Table 11. Default Register Settings
REGISTER
DAC_CONFIG
VALUE (HEX)
0x00
DESCRIPTION
DAC is set for absolute voltage output.
OP_STAGE_CTRL
BRG_CTRL
0x08
Output is configured for 4-mA to 20-mA mode.
Bridge excitation is set to 2.5 V.
0x00
P_GAIN_SELECT
T_GAIN_SELECT
TEMP_CTRL
0x00
P_GAIN is set to 5 V/V gain.
0x00
T_GAIN is set for 1.33 V/V gain.
0x40
ITEMP drive is disabled and T signal chain is set for VINT+ – VINT–
.
TEMP_SE
0x00
T GAIN is in single-ended configuration.
NORMAL_LOW_LSB
NORMAL_LOW_MSB
NORMAL_HIGH_LSB
0x67
DAC normal low output set to 0x0667. Must be updated during calibration
DAC normal low output set to 0x0667. Must be updated during calibration
DAC normal high output set to 0x399A. Must be updated during calibration
0x06
0x9A
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Register Maps (continued)
Table 11. Default Register Settings (continued)
REGISTER
NORMAL_HIGH_MSB
LOW_CLAMP_LSB
LOW_CLAMP_MSB
HIGH_CLAMP_LSB
HIGH_CLAMP_MSB
DIAG_ENABLE
VALUE (HEX)
0x39
DESCRIPTION
DAC normal high output set to 0x399A. Must be updated during calibration
DAC clamp low output set to 0x0334. Must be updated during calibration
DAC clamp low output set to 0x0334. Must be updated during calibration
DAC clamp high output set to 0x3CCF. Must be updated during calibration
DAC clamp high output set to 0x3CCF. Must be updated during calibration
Diagnostics are disabled.
0x34
0x03
0xCF
0x3C
0x00
EEPROM_LOCK
0x00
EEPROM is unlocked.
Diagnostics pulldown (1 MΩ) and pullup (1 MΩ) resistors enabled, VINP_UV threshold
= 7.5% and VINP_OV threshold = 92.5%
AFEDIAG_CFG
0x07
0x33
AFEDIAG_MASK
VINP_OV and PGAIN_UV detection enabled
SERIAL_NUMBER_BYTE0-1-2-3 0x00
EEPROM_CRC 0xB8
Serial number specified by customer
Must be updated every time EEPROM is changed if diagnostics are enabled
40
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7.5.2 Control and Status Registers
Table 12. Control and Status Registers
DI Page
Address
DI Offset
Address
EEPROM
Address
Register Name
R/W
D7
D6
D5
D4
D3
D2
D1
D0
H0_LSB
H0_MSB
G0_LSB
G0_MSB
N0_LSB
N0_MSB
M0_LSB
M0_MSB
H1_LSB
H1_MSB
G1_LSB
G1_MSB
N1_LSB
N1_MSB
M1_MSB
M1_LSB
H2_LSB
H2_MSB
G2_LSB
G2_MSB
N2_LSB
N2_MSB
M2_LSB
M2_MSB
H3_LSB
H3_MSB
G3_LSB
G3_MSB
N3_LSB
N3_MSB
M3_LSB
N/A
N/A
0x40000000
0x40000001
0x40000002
0x40000003
0x40000004
0x40000005
0x4000003C
0x4000003D
0x40000006
0x40000007
0x40000008
0x40000009
0x4000000A
0x4000000B
0x4000003E
0x4000003F
0x4000000C
0x4000000D
0x4000000E
0x4000000F
0x40000010
0x40000011
0x40000040
0x40000041
0x40000036
0x40000037
0x40000038
0x40000039
0x4000003A
0x4000003B
0x40000042
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
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Table 12. Control and Status Registers (continued)
DI Page
Address
DI Offset
Address
EEPROM
Address
Register Name
R/W
D7
D6
D5
D4
D3
D2
D1
D0
M3_MSB
N/A
N/A
0x40000043
0x40000012
0x40000013
0x40000014
0x40000015
0x40000016
0x40000017
0x40000018
0x40000019
0x4000001A
0x4000001B
0x4000001C
0x4000001D
N/A
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
A0_LSB
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0x2
0x2
0x2
0x2
0x2
0x2
N/A
A0_MSB
N/A
A1_LSB
N/A
A1_MSB
N/A
A2_LSB
N/A
A2_MSB
N/A
B0_LSB
N/A
B0_MSB
N/A
B1_LSB
N/A
B1_MSB
N/A
B2_LSB
N/A
B2_MSB
N/A
PADC_DATA1
PADC_DATA2
TADC_DATA1
TADC_DATA2
DAC_REG0_1
DAC_REG0_2
0x20
0x21
0x24
0x25
0x30
0x31
N/A
R
N/A
R
N/A
R
N/A
RW
RW
N/A
DAC_
DAC_CONFIG
0x2
0x39
0x40000020
RW
RATIOMETR
IC
OP_STAGE_CTR
L
DACCAP_E
N
DAC_GAIN[2 DAC_GAIN[1 DAC_GAIN[0
0x2
0x2
0x2
0x2
0x3B
0x46
0x47
0x48
0x40000021
0x40000022
0x40000023
0x40000024
RW
RW
RW
RW
4_20MA_EN
P_GAIN[3]
]
]
]
VBRDG_
CTRL[1]
VBRDG_
CTRL[0]
BRDG_CTRL
P_GAIN_
SELECT
P_INV
T_INV
P_GAIN[4]
P_GAIN[2]
P_GAIN[1]
T_GAIN[1]
P_GAIN[0]
T_GAIN[0]
T_GAIN_
SELECT
TEMP_MUX TEMP_MUX TEMP_MUX TEMP_MUX
ITEMP_
CTRL[2]
ITEMP_
CTRL[1]
ITEMP_
CTRL[0]
TEMP_CTRL
0x2
0x4C
0x40000025
RW
_
_
_
_
CTRL[3]
CTRL[2]
CTRL[1]
CTRL[0]
TEMP_SE
N/A
N/A
N/A
N/A
0x40000028
0x4000002A
RW
RW
TEMP_SE
NORMAL_LOW_L
SB
42
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Register Name
ZHCSF35A –OCTOBER 2014–REVISED JUNE 2016
Table 12. Control and Status Registers (continued)
DI Page
Address
DI Offset
Address
EEPROM
Address
R/W
RW
RW
RW
RW
RW
RW
D7
D6
D5
D4
D3
D2
D1
D0
NORMAL_LOW_
MSB
N/A
N/A
0x4000002B
0x4000002C
0x4000002D
0x4000002E
0x4000002F
0x40000030
NORMAL_HIGH_L
SB
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
NORMAL_HIGH_
MSB
LOW_CLAMP_LS
B
LOW_CLAMP_MS
B
HIGH_CLAMP_LS
B
HIGH_CLAMP_M
SB
N/A
N/A
N/A
0x40000031
0x40000032
0x40000033
RW
RW
RW
PADC_GAIN_LSB N/A
PADC_GAIN_MS
B
N/A
PADC_OFFSET_
N/A
N/A
N/A
0x40000034
0x40000035
RW
RW
BYTE0
PADC_OFFSET_
N/A
BYTE1
DIAG_ENABLE
EEPROM_LOCK
AFEDIAG_CFG
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0x40000044
0x40000045
0x40000046
0x40000047
0x4000004A
0x4000004B
0x4000004C
0x4000004D
RW
RW
RW
RW
RW
RW
RW
RW
-
DIS_R_T
DIS_R_P
THRS[2]
THRS[1]
THRS[0]
PD2
INP_UV
PD1
INP_OV
AFEDIAG_MASK N/A
TGAIN_UV TGAIN_OV
PGAIN_UV
PGAIN_OV
-
INT_OV
FAULT_LSB
FAULT_MSB
N/A
N/A
TADC_GAIN_LSB N/A
TADC_GAIN_MSB N/A
TADC_OFFSET_B
YTE0
N/A
N/A
N/A
N/A
N/A
0x4000004E
0x4000004F
0x40000050
0x40000051
RW
RW
RW
RW
TADC_OFFSET_B
YTE1
N/A
SERIAL_NUMBER
N/A
_BYTE0
SERIAL_NUMBER
N/A
_BYTE1
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Table 12. Control and Status Registers (continued)
DI Page
Address
DI Offset
Address
EEPROM
Address
Register Name
R/W
RW
RW
R
D7
D6
D5
D4
D3
D2
D1
D0
SERIAL_NUMBER
_BYTE2
N/A
N/A
0x40000052
0x40000053
0x4000007F
SERIAL_NUMBER
_BYTE3
N/A
0x5
N/A
EEPROM_CRC
_VALUE
0x8D
COMPENSATION
COMPENSA
_
0x0
0x0C
N/A
RW
TION_RESE IF_SEL
T
CONTROL
EEPROM ARRAY 0x5
EEPROM_CACHE 0x5
0x00-0x7F N/A
0x80-0x87 N/A
RW
RW
EEPROM_PAGE_
0x5
0x88
0x89
0x8A
N/A
N/A
N/A
RW
RW
RW
ADDR[2]
ADDR[1]
ERASE
ADDR[0]
ADDRESS
FIXED_
ERASE_
ERASE_AN
D
PROG_TIME _PROGRAM
EEPROM_CTRL
EEPROM_CRC
0x5
0x5
PROGRAM
CALCULATE
_CRC
PROGRAM_
IN
_PROGRES
S
ERASE_IN
_PROGRES _PROGRES
S
READ_IN
EEPROM_STATU
S
0x5
0x5
0x8B
0x8C
N/A
N/A
R
R
S
CRC_CHEC
K
EEPROM_CRC
_STATUS
CRC_GOOD
_IN_PROG
44
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ZHCSF35A –OCTOBER 2014–REVISED JUNE 2016
7.5.2.1 DAC_CONFIG
DI PAGE ADDRESS: 0x2, DI PAGE OFFSET: 0x39
Figure 22. DAC_CONFIG Register (EEPROM Address = 0x40000020)
DAC_CONFIG
7
6
5
4
3
2
1
0
DAC_
RATIOMET
RIC
BIT DEFINITION
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
RW ACCESS
RW
0
RESET VALUE
Table 13. DAC_CONFIG Register (EEPROM Address = 0x40000020) Bit Descriptions
Register
Bits
0: DAC_RATIOMETRIC
1–7: UNUSED
Description
1: DAC is in ratiometric mode
0: DAC is in absolute mode
DAC_CONFIG
7.5.2.2 OP_STAGE_CTRL
DI PAGE ADDRESS: 0x2, DI PAGE OFFSET: 0x3B
Figure 23. OP_STAGE_CTRL Register (EEPROM Address = 0x40000021)
OP_STAGE_CTRL
7
6
5
4
3
2
1
0
PULLUP_E DACCAP_E 4_20MA_E DAC_GAIN[ DAC_GAIN[ DAC_GAIN[
BIT DEFINITION
UNUSED
UNUSED
N
RW
0
N
RW
0
N
RW
0
2]
RW
1
1]
RW
0
0]
RW
1
RW ACCESS
RESET VALUE
Table 14. OP_STAGE_CTRL Register (EEPROM Address = 0x40000021) Bit Descriptions
Register
Bits
Description
DAC_GAIN[0]
0: DAC_GAIN[0]
1: DAC_GAIN[1]
2: DAC_GAIN[2]
DAC_GAIN[2]
DAC_GAIN[1]
Description
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Voltage mode disabled
Gain = 10V/V
Gain = 4V/V
Reserved
Gain = 2V/V
Reserved
Gain = 6.67V/V
Reserved
OP_STAGE_CTRL
1: Enable 4 to 20mA Current Loop (Close switch S5 in DAC Gain)
0: Disable 4 to 20mA Current Loop (Open switch S5 in DAC Gain)
3: 4_20MA_EN
4: DACCAP_EN
1: Enable DACCAP capacitor (Close switch S4 in DAC Gain)
0: Disable DACCAP capacitor (Open switch S4 in DAC Gain)
1: Enable Pull up at the input of DAC Gain (Close switch S8 in DAC Gain)
0: Disable Pull up at the input of DAC Gain (Open switch S8 in DAC Gain)
5: PULLUP_EN
6–7: UNUSED
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7.5.2.3 BRDG_CTRL
DI PAGE ADDRESS: 0x2, DI PAGE OFFSET: 0x46
Figure 24. BRDG_CTRL Register (EEPROM Address = 0x40000022)
BRDG_CTRL
7
6
5
4
3
2
1
0
VBRDG_
CTRL[1]
VBRDG_
CTRL[0]
BIT DEFINITION
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
RW ACCESS
RW
0
RW
0
RESET VALUE
Table 15. BRDG_CTRL Register (EEPROM Address = 0x40000022) Bit Descriptions
Register
Bits
0: UNUSED
Description
VBRDG_CTRL[1]
VBRDG_CTRL[0]
Bridge Supply Voltage
0
0
1
1
0
1
0
1
2.5V
1: VBRDG_CTRL[0]
2: VBRDG_CTRL[1]
BRDG_CTRL
2.0V
1.25V
1.25V
3–7: UNUSED
7.5.2.4 P_GAIN_SELECT
DI PAGE ADDRESS: 0x2, DI PAGE OFFSET: 0x47
Figure 25. P_GAIN_SELECT Register (EEPROM Address = 0x40000023)
P_GAIN_SELECT
BIT DEFINITION
RW ACCESS
7
P_INV
RW
0
6
5
4
P_GAIN[4]
RW
3
P_GAIN[3]
RW
2
P_GAIN[2]
RW
1
P_GAIN[1]
RW
0
P_GAIN[0]
RW
UNUSED
UNUSED
RESET VALUE
0
0
0
0
0
Table 16. P_GAIN_SELECT Register (EEPROM Address = 0x40000023) Bit Descriptions
Register
Bits
Description
0: P_GAIN[0]
1: P_GAIN[1]
2: P_GAIN[2]
3: P_GAIN[3]
4: P_GAIN[4]
See Electrical Parameters for Gain Selections
P_GAIN_SELECT
5–6: UNUSED
1: Inverts the output of the PGAIN Output
0: No Inversion
7: P_INV
7.5.2.5 T_GAIN_SELECT
DI PAGE ADDRESS: 0x2, DI PAGE OFFSET: 0x48
Figure 26. T_GAIN_SELECT Register (EEPROM Address = 0x40000024)
T_GAIN_SELECT
BIT DEFINITION
RW ACCESS
7
T_INV
RW
0
6
5
4
3
2
1
T_GAIN[1]
RW
0
T_GAIN[0]
RW
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
RESET VALUE
0
0
46
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ZHCSF35A –OCTOBER 2014–REVISED JUNE 2016
Table 17. T_GAIN_SELECT Register (EEPROM Address = 0x40000024) Bit Descriptions
Register
Bits
Description
0: T_GAIN[0]
1: T_GAIN[1]
See Electrical Parameters for Gain Selections
T_GAIN_SELECT
2–6: UNUSED
1: Inverts the output of the T GAIN Output
0: No Inversion
7: T_INV
7.5.2.6 TEMP_CTRL
DI PAGE ADDRESS: 0x2, DI PAGE OFFSET: 0x4C
Figure 27. TEMP_CTRL Register (EEPROM Address = 0x40000025)
TEMP_CTRL
7
6
5
4
3
2
1
0
TEMP_MU TEMP_MU TEMP_MU TEMP_MU
ITEMP_
CTRL[2]
ITEMP_
CTRL[1]
ITEMP_
CTRL[0]
BIT DEFINITION
UNUSED
X_
X_
X_
X_
CTRL[3]
CTRL[2]
CTRL[1]
CTRL[0]
RW ACCESS
RW
1
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RESET VALUE
Table 18. TEMP_CTRL Register (EEPROM Address = 0x40000025)
Register
Bits
Description
0:
TEMP_MUX_ TEMP_MUX_ TEMP_MUX_ TEMP_MUX_
Description
TEMP_MUX_CTRL[0]
CTRL[3]
CTRL[2]
CTRL[1]
CTRL[0]
1:
0
0
0
0
0
1
0
1
INT+ and INT–
TEMP_MUX_CTRL[1]
2:
VTEMP_INT-GND (Internal
Temperature Sensor)
TEMP_MUX_CTRL[2]
3:
TEMP_MUX_CTRL[3]
TEMP_CTRL
ITEMP_
CTRL[2]
ITEMP_
CTRL[1]
ITEMP_
CTRL[0]
4: ITEMP_CTRL[0]
Description
5: ITEMP_CTRL[1]
6: ITEMP_CTRL[2]
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
25µA
50µA
100µA
500µA
OFF
7: UNUSED
7.5.2.7 TEMP_SE
Figure 28. TEMP_SE Register (EEPROM Address = 0x40000028)
TEMP_SE
BIT DEFINITION
RW ACCESS
RESET VALUE
7
6
5
4
3
2
1
0
TEMP_SE
RW
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
0
Table 19. TEMP_SE Register (EEPROM Address = 0x40000028) Bit Descriptions
Register
TEMP_SE
Bits
Description
1: Output of Temperature Mux is differential
0: Output of Temperature Mux is single-ended
0: TEMP_SE
1–7: UNUSED
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7.5.2.8 DIAG_ENABLE
Figure 29. DIAG_ENABLE Register (EEPROM Address = 0x40000044)
DIAG_ENABLE
7
6
5
4
3
2
1
0
DIAG_ENA
BLE
BIT DEFINITION
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
RW ACCESS
RW
0
RESET VALUE
Table 20. DIAG_ENABLE Register (EEPROM Address = 0x40000044) Bit Descriptions
Register
Bits
Description
Read:
0: DIAG_ENABLE
1–7: UNUSED
1: Enables Diagnostics
0: Disables Diagnostics
DIAG_ENABLE
7.5.2.9 AFEDIAG_CFG
Figure 30. AFEDIAG_CFG Register (EEPROM Address = 0x40000046)
AFEDIAG_CFG
BIT DEFINITION
RW ACCESS
7
6
DIS_R_T
RW
5
DIS_R_P
RW
4
THRS[2]
RW
3
THRS[1]
RW
2
THRS[0]
RW
1
PD2
RW
0
0
PD1
RW
0
UNUSED
RESET VALUE
0
0
0
0
0
48
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Register
ZHCSF35A –OCTOBER 2014–REVISED JUNE 2016
Table 21. AFEDIAG_CFG Register (EEPROM Address = 0x40000046) Bit Descriptions
Bits
Description
Pull Down
Resistor Value
PD2
PD1
0: PD1
0
1
0
1
0
0
1
1
4MΩ
3MΩ
2MΩ
1MΩ
1: PD2
VINP_UV
Threshold
VINP_OV
Threshold
THRS[2]
THRS[1]
THRS[0]
95% of
Programmed
VBRDG
5% of Programmed
VBRDG
2: THRS[0]
3: THRS[1]
4: THRS[2]
0
0
0
7.5% of
Programmed
VBRDG
92.5% if
Programmed
VBRDG
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
10% of
Programmed
VBRDG
90% of
Programmed
VBRDG
12.5% of
Programmed
VBRDG
87.5% of
Programmed
VBRDG
AFEDIAG_CFG
15% of
Programmed
VBRDG
85% of
Programmed
VBRDG
20% of
Programmed
VBRDG
80% of
Programmed
VBRDG
25% of
Programmed
VBRDG
75% of
Programmed
VBRDG
30% of
Programmed
VBRDG
70% of
Programmed
VBRDG
1: Disables pulldown resistors used for open/short diagnostics on the INP+ and INP– pins
0: Enables pulldown resistors used for open/short diagnostics on the INP+ and INP– pins
5: DIS_R_P
1: Disables pullup resistors used for open/short diagnostics on the INT+ and INT– pins
0: Enables pullup resistors used for open/short diagnostics on the INT+ and INT– pins
6: DIS_R_T
7: UNUSED
7.5.2.10 AFEDIAG_MASK
Figure 31. AFEDIAG_MASK Register (EEPROM Address = 0x40000047)
AFEDIAG
7
6
5
4
3
2
INT_OV
RW
1
INP_UV
RW
0
INP_OV
RW
BIT DEFINITION
RW ACCESS
RESET VALUE
TGAIN_UV TGAIN_OV PGAIN_UV PGAIN_OV
UNUSED
RW
0
RW
0
RW
0
RW
0
0
0
0
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Table 22. AFEDIAG_MASK Register (EEPROM Address = 0x40000047) Bit Descriptions
Register
Bits
Description
1: Enable overvoltage detection at input pins of P Gain
0: Disable overvoltage detection at input pins of P Gain
0: INP_OV
1: INP_UV
1: Enable undervoltage detection at input pins of P Gain
0: Disable undervoltage detection at input pins of P Gain
1: Enable overvoltage detection at input pins of T Gain
0: Disable overvoltage detection at input pins of T Gain
2: INT_OV
3: UNUSED
4: PGAIN_OV
AFEDIAG
1: Enable overvoltage detection at output pins of P Gain
0: Disable overvoltage detection at output pins of P Gain
1: Enable undervoltage detection at output pins of P Gain
0: Disable undervoltage detection at output pins of P Gain
5: PGAIN_UV
6: TGAIN_OV
7: TGAIN_UV
1: Enable overvoltage detection at output pins of T Gain
0: Disable overvoltage detection at output pins of T Gain
1: Enable undervoltage detection at output pins of T Gain
0: Disable undervoltage detection at output pins of T Gain
7.5.2.11 COMPENSATION_CONTROL
DI PAGE ADDRESS: 0x0, DI PAGE OFFSET: 0x0C
Figure 32. COMPENSATION_CONTROL Register (EEPROM Address = N/A)
COMPENSATION_CONT
ROL
7
6
5
4
3
2
1
0
COMPENS
ATION_RE
SET
BIT DEFINITION
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
IF_SEL
RW ACCESS
RW
0
RW
0
RESET VALUE
Table 23. COMPENSATION_CONTROL Register (EEPROM Address = N/A) Bit Descriptions
Register
Bits
Description
1: Digital Interface accesses the PGA300 resources
0: Calculation Engine accesses the PGA300 resources
0: IF_SEL
COMPENSATION_CONTROL
1: Compensation Engine is in Reset
0: Compensation Engine is Running
1: COMPENSATION_RESET
2–7: UNUSED
7.5.2.12 EEPROM_LOCK
Figure 33. EEPROM_LOCK Register (EEPROM Address = 0x40000045)
EEPROM_LOCK
7
6
5
4
3
2
1
0
EEPROM_L
OCK
BIT DEFINITION
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
RW ACCESS
RW
0
RESET VALUE
Table 24. EEPROM_LOCK Register (EEPROM Address = 0x40000045) Bit Descriptions
Register
Bits
0: EEPROM_LOCK
1–7: UNUSED
Description
1: EEPROM is locked - EEPROM is not accessible
0: EEPROM is unlocked - EEPROM is accessible
EEPROM_LOCK
50
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7.5.2.13 EEPROM_PAGE_ADDRESS
DI PAGE ADDRESS: 0x5, DI PAGE OFFSET: 0x88
Figure 34. EEPROM_PAGE_ADDRESS Register (EEPROM Address = N/A)
EEPROM_PAGE_ADDRES
S
7
6
5
4
3
2
1
0
BIT DEFINITION
RW ACCESS
UNUSED UNUSED
UNUSED
UNUSED
ADDR[3]
ADDR[2]
ADDR[1]
ADDR[0]
RW
0
RW
0
RW
0
RW
0
RESET VALUE
Table 25. EEPROM_PAGE_ADDRESS Register (EEPROM Address = N/A) Bit Descriptions
Register
Bits
0–3: ADDR[0-3]
4–7: UNUSED
Description
EEPROM page address used in the EEPROM Programming Procedure
EEPROM_PAGE_ADDRESS
7.5.2.14 EEPROM_CTRL
DI PAGE ADDRESS: 0x5, DI PAGE OFFSET: 0x89
Figure 35. EEPROM_CTRL Register (EEPROM Address = N/A)
EEPROM_CTRL
7
6
5
4
3
2
1
0
FIXED_
ERASE_
ERASE_AN
D
BIT DEFINITION
UNUSED
UNUSED
UNUSED
UNUSED
ERASE
PROGRAM
PROG_TIM _PROGRA
E
RW
0
M
RW
0
RW ACCESS
RW
0
RW
0
RESET VALUE
Table 26. EEPROM_CTRL Register (EEPROM Address = N/A) Bit Descriptions
Register
Bits
Description
1: Program contents of EEPROM cache into EEPROM memory pointed to by
0: PROGRAM
1: ERASE
EEPROM_PAGE_ADDRESS
0: No action
1: Erase contents of EEPROM memory pointed to by EEPROM_PAGE_ADDRESS
0: No action
EEPROM_
CTRL
1: Erase contents of EEPROM memory pointed to by EEPROM_PAGE_ADDRESS and
program of contents of EEPROM cache
0: No action
2: ERASE_AND_PROGRAM
1: Use Fixed 8ms as the Erase/Program time
0: Use Variable time <8ms as the Erase/Program time. The EEPROM programming logic
will determine the duration to program the EEPROM memory.
3:
FIXED_ERASE_PROG_TIME
4–7: UNUSED
7.5.2.15 EEPROM_CRC
DI PAGE ADDRESS: 0x5, DI PAGE OFFSET: 0x8A
Figure 36. EEPROM_CRC Register (EEPROM Address = N/A)
EEPROM_CRC
7
6
5
4
3
2
1
0
CALCULAT
E
BIT DEFINITION
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
_CRC
RW ACCESS
RW
0
RESET VALUE
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Table 27. EEPROM_CRC Register (EEPROM Address = N/A) Bit Descriptions
Register
Bits
Description
1: Calculate EEPROM CRC
0: No action
0: CALCULATE_CRC
1–7: UNUSED
EEPROM_CRC
7.5.2.16 EEPROM_STATUS
DI PAGE ADDRESS: 0x5, DI PAGE OFFSET: 0x8B
Figure 37. EEPROM_STATUS Register (EEPROM Address = N/A)
EEPROM_STATUS
7
6
5
4
3
2
1
0
PROGRAM
_IN
_PROGRE
SS
ERASE_IN
_PROGRE _PROGRE
READ_IN
BIT DEFINITION
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
SS
SS
RW ACCESS
R
0
R
0
R
0
RESET VALUE
Table 28. EEPROM_STATUS Register (EEPROM Address = N/A) Bit Descriptions
Register
Bits
Description
1: EEPROM Read in progress
0: EEPROM Read not in progress
0: READ_IN_PROGRESS
1: EEPROM Erase in progress
0: EEPROM Erase not in progress
1: ERASE_IN_PROGRESS
EEPROM_STATUS
1: EEPROM Program in progress
0: EEPROM Program not in progress
2: PROGRAM_IN_PROGRESS
3–7: UNUSED
7.5.2.17 EEPROM_CRC_STATUS
DI PAGE ADDRESS: 0x5, DI PAGE OFFSET: 0x8C
Figure 38. EEPROM_CRC_STATUS Register (EEPROM Address = N/A)
EEPROM_CRC_STATUS
7
6
5
4
3
2
1
0
CRC_CHE
CK
_IN_PROG
CRC_GOO
D
BIT DEFINITION
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
RW ACCESS
R
0
R
0
RESET VALUE
Table 29. EEPROM_CRC_STATUS Register (EEPROM Address = N/A) Bit Descriptions
Register
Bits
Description
1: EEPROM CRC check in progress
0: EEPROM CRC check not in progress
0: CRC_CHECK_IN_PROGRESS
EEPROM_CRC_
STATUS
1: EEPROM Programmed CRC matches calculated CRC
0: EEPROM Programmed CRC does not match calculated CRC
1: CRC_GOOD
2–7: UNUSED
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7.5.2.18 EEPROM_CRC_VALUE
DI PAGE ADDRESS: 0x5, DI PAGE OFFSET: 0x8D
Figure 39. EEPROM_CRC_VALUE Register (EEPROM Address = 0x4000007F)
EEPROM_CRC_VALUE
BIT DEFINITION
RW ACCESS
7
6
5
4
3
2
1
0
R
1
R
1
R
1
R
1
R
1
R
1
R
1
R
1
RESET VALUE
Table 30. EEPROM_CRC_VALUE Register (EEPROM Address = 0x4000007F) Bit Descriptions
Register
Bits
Description
CRC value as calculated by the digital logic
EEPROM_CRC_VALUE
0–7
EEPROM CRC value should be located in the last byte of the EEPROM
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The PGA 300 can be used in a variety of applications to measure pressure and temperature. Depending on the
application, the device can be configured in different modes as illustrated in the following sections.
8.1.1 4-mA to 20-mA Output With Internal Sense Resistor
Sensor
Controller
PWR
PWR
40 kΩ
VDAC
+
OUT
S1
–
40 kΩ
COMP
+
DAC
100 nF
Reference
Is Absolute
1.25 V
–
Open
FB–
S2
S0
2 V/V
4 V/V
150 kΩ
6.67 V/V
10 V/V
40 Ω
FB+
DACCAP
Iloop
GND
AVDD
REFCAP
DVDD
100 nF
100 nF
100 nF
图 40. 4-mA to 20-mA Output With Internal Sense Resistor Diagram
8.1.1.1 Design Requirements
There are only a few requirements to take into account when using the PGA300 device in a design:
•
•
Do not exceed the maximum slew rate of 0.5 V/µs at the PWR pin.
Place a 100-nF capacitor from the AVDD pin to ground, as close as possible to the AVDD pin.
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Application Information (接下页)
•
•
Place a 100-nF capacitor from the DVDD pin to ground, as close as possible to the DVDD pin.
Place a capacitor between 10 nF and 1000 nF from the REFCAP pin to ground, as close as possible to the
REFCAP pin.
•
•
Place a 150-Ω resistor between the COMP pin and the emitter of the BJT for current-loop stability purposes.
Place a 10-Ω resistor between the FB+ pin and the negative terminal of the controller for current
measurement.
8.1.1.2 Detailed Design Procedure
8.1.1.2.1 Calibration Tips
8.1.1.2.1.1 Programming the EEPROM for 4-mA to 20-mA Output
The EEPROM in the PGA300 is configured by default to operate in current mode using the OP_STG_CTRL
register. If not, the following sequence must be followed to change it to current mode:
1. Send an OWI activation pulse to stop the digital compensation from running.
2. Set OP_STAGE_CTRL to 0x80 for current mode and DAC_CONFIG EEPROM to 0x00 or 0x01 for No_Gain.
3. Let the digital compensation run again to read the new EEPROM values.
8.1.1.3 Application Curve
Voltage measured between the GND pin in the PGA300 device and the negative terminal of the
controller. This includes the internal 40-Ω resistor and an external 10-Ω resistor, VPWR = 15 V.
The DAC codes used were 0x880 and 0x2760 for 4 mA and 20 mA, respectively.
图 41. Loop Current Step From 4 mA to 20 mA
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Application Information (接下页)
8.1.2 0- to 10-V Absolute Output With Internal Drive
Sensor
Controller
PWR
OUT
PWR
40 kΩ
VDAC
+
S1
+
–
–
40 kΩ
COMP
DAC
Reference
Is Absolute
1.25 V
Open
FB–
S2
2 V/V
4 V/V
S0
150 kΩ
6.67 V/V
10 V/V
40 Ω
GND
FB+
DACCAP
AVDD
100 nF
100 nF
100 nF
100 nF
REFCAP
DVDD
图 42. 0- to 10-V Absolute Output With Internal Drive Diagram
8.1.2.1 Design Requirements
There are only a few requirements to take into account when using the PGA300 in a design:
•
•
•
•
Do not exceed the maximum slew rate of 0.5 V/µs at the VDD pin.
Place a 100-nF capacitor from the AVDD pin to ground, as close as possible to the AVDD pin.
Place a 100-nF capacitor from the DVDD pin to ground, as close as possible to the DVDD pin.
Place a capacitor between 10 nF and 1000 nF from the REFCAP pin to ground, as close as possible to the
REFCAP pin.
•
Implement compensation, using the COMP pin and an isolation resistor, when driving large capacitive loads
with the OUT pin.
56
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Application Information (接下页)
8.1.2.2 Detailed Design Procedure
8.1.2.2.1 Programmer Tips
8.1.2.2.1.1 Resetting the Microprocessor and Enable Digital Interface
The following bits must be configured to reset the M0 microprocessor and to enable digital interface:
1. Set the IF_SEL bit in the MICRO_INTERFACE_CONTROL register to 1.
2. Set the MICRO_RESET bit in the MICRO_INTERFACE_CONTROL register to 1.
8.1.2.2.1.2 Turning On the Accurate Reference Buffer (REFCAP Voltage)
The following bits must be configured to turn ON the accurate reference buffer:
1. Set the SD bit in the ALPWR register to 0.
2. Set the ADC_EN_VREF bit in the ALPWR register to 1.
By turning on the accurate reference buffer, the reference voltage can be measured on REFCAP pin. Further, the
capacitor on the REFCAP pin is connected to the reference buffer.
8.1.2.2.1.3 Turning On DAC and DAC GAIN
The following bits must be configured to turn on DAC and DAC GAIN:
•
•
•
•
•
Set the SD bit in the ALPWR register to 0.
Set the ADC_EN_VREF bit in the ALPWR register to 1.
Set the DAC_ENABLE bit in the DAC_CTRL_STATUS register to 1.
Set the 4_20_MA_EN bit in the OP_STAGE_CTRL register for voltage output or current output mode.
Set the DACCAP_EN bit in the OP_STAGE_CTRL register to connect or disconnect the external capacitor at
the DAC output.
•
•
Set the DAC_RATIOMETRIC bit in the DAC_CONFIG register for ratiometric or absolute-voltage output
mode.
Set the TEST_MUX_DAC_EN bit in the AMUX_CTRL register to 1.
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Application Information (接下页)
8.1.3 0- to 5-V Ratiometric Output With Internal Drive
Sensor
Controller
PWR
OUT
PWR
40 kΩ
VDAC
+
S1
+
–
–
40 kΩ
COMP
DAC
Reference Is
Open
Ratiometric
to PWR / 4
FB–
S2
2 V/V
4 V/V
S0
150 kΩ
6.67 V/V
10 V/V
40 Ω
GND
FB+
DACCAP
AVDD
100 nF
100 nF
100 nF
100 nF
REFCAP
DVDD
图 43. 0- to 5-V Ratiometric Output With Internal Drive Diagram
8.1.3.1 Design Requirements
There are only a few requirements to take into account when using the PGA300 in a design:
•
•
•
•
Do not exceed the maximum slew rate of 0.5 V/µs at the PWR pin.
Place a 100-nF capacitor from the AVDD pin to ground, as close as possible to the AVDD pin.
Place a 100-nF capacitor from the DVDD pin to ground, as close as possible to the DVDD pin.
Place a capacitor between 10 nF and 1000 nF from the REFCAP pin to ground, as close as possible to the
REFCAP pin.
•
Implement compensation, using the COMP pin and an isolation resistor, when driving large capacitive loads
with the OUT pin.
58
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Application Information (接下页)
8.1.3.2 Detailed Design Procedure
8.1.3.2.1 Programmer Tips
8.1.3.2.1.1 Resetting the Microprocessor and Enable Digital Interface
The following bits must be configured to reset the M0 microprocessor and to enable digital interface:
1. Set the IF_SEL bit in the MICRO_INTERFACE_CONTROL register to 1.
2. Set the MICRO_RESET bit in the MICRO_INTERFACE_CONTROL register to 1.
8.1.3.2.1.2 Turning On the Accurate Reference Buffer (REFCAP Voltage)
The following bits must be configured to turn ON the accurate reference buffer:
1. Set the SD bit in the ALPWR register to 0.
2. Set the ADC_EN_VREF bit in the ALPWR register to 1.
By turning on the accurate reference buffer, the reference voltage can be measured on REFCAP pin. Further, the
capacitor on the REFCAP pin is connected to the reference buffer.
8.1.3.2.1.3 Turning On DAC and DAC GAIN
The following bits must be configured to turn on DAC and DAC GAIN:
•
•
•
•
•
Set the SD bit in ALPWR register to 0.
Set the ADC_EN_VREF bit in the ALPWR register to 1.
Set the DAC_ENABLE bit in the DAC_CTRL_STATUS register to 1.
Set the 4_20_MA_EN bit in the OP_STAGE_CTRL register for the voltage-output or current-output mode.
Set the DACCAP_EN bit in the OP_STAGE_CTRL register to connect or disconnect the external capacitor at
the DAC output.
•
•
Set the DAC_RATIOMETRIC bit in the DAC_CONFIG register for ratiometric or absolute-voltage output
mode.
Set the TEST_MUX_DAC_EN bit in the AMUX_CTRL register to 1.
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9 Power Supply Recommendations
The PGA300 device has a single pin, PWR, for the input power supply. The maximum slew rate for the PWR pin
is 0.5 V/µs as specified in the Recommended Operating Conditions. Faster slew rates might generate a POR. A
decoupling capacitor for PWR should be placed as close as possible to the pin.
10 Layout
10.1 Layout Guidelines
Standard layout good practices should be used when designing a board to test the PGA300 device. Depending
on the number of layers in the board, one or more GND planes should be inserted as internal layers. However,
given the limited number of external components needed for an application using the PGA300 device and the
number of NC pins in the device, it is very possible to design a simple two-layer board. In addition, the PWR
decoupling capacitor should be placed as close as possible to the pin. In a similar way, the 100 nF
recommended capacitors for the AVDD and DVDD regulators as well as the 10- to 1000-nF recommended
capacitor for REFCAP should be placed as close as possible to their respective pins.
Depending on the application, the signal traces for FB–, FB+, COMP, and OUT should be routed such that they
do not cross one another in order to minimize coupling.
10.2 Layout Example
图 44 shows the main guidelines previously discussed being implemented in a six-layer, socketed EVM of the
PGA300 device. Two main GND planes (layer 2 and 5) were used to provide a nearby GND plane to each of the
signal layers and the power plane (layer 3) in the EVM. This EVM supports voltage and current modes for the
device, and as a result, GND separation is needed, depending on the application. As a result, layer 2 is a solid
GND plane for the majority of the circuitry in the EVM (IRETURN). Because most of the circuitry is referred to
this GND plane, layers 3 and 4 also contain copper pours connected to IRETURN. This GND plane is the return
path for the supply used in the 4-mA to 20-mA loop. Layer 5 is a split plane for the ground references for the
digital communication signals used for this EVM (USBGND) and the ground pins in the device (GND, AVSS and
DVSS), referred to as ASICGND. The EVM provides jumpers to connect, or disconnect, these three planes one
from another, depending on the desired configuration.
图 44 shows the recommended capacitors for the proper operation of the PGA300 device. These capacitors are
placed as close as possible to their respective pins of the socket used for this particular EVM. The signal traces
for FB–, FB+, COMP, and OUT can also be observed to be routed all in the same layer to avoid crossing each
other and minimize coupling.
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Layout Example (接下页)
DVDD Capacitor
PWR Capacitor
AVDD Capacitor
2.3 In
REFCAP
FB+ Trace
FB– Trace
COMP Trace
OUT Trace
5 In
图 44. Layout Diagram
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11 器件和文档支持
11.1 商标
11.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件提供的最新数据。本数据随时可能发生变更并且
不对本文档进行修订，恕不另行通知。要获得这份数据表的浏览器版本，请查阅左侧的导航窗格。
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PGA300ARHHR
PGA300ARHHT
ACTIVE
VQFN
VQFN
RHH
36
36
2500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 150
-40 to 150
PGA300A
RHH
ACTIVE
RHH
NIPDAU
PGA300A
RHH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Aug-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PGA300ARHHR
PGA300ARHHT
VQFN
VQFN
RHH
RHH
36
36
2500
250
330.0
180.0
16.4
16.4
6.3
6.3
6.3
6.3
1.1
1.1
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Aug-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
PGA300ARHHR
PGA300ARHHT
VQFN
VQFN
RHH
RHH
36
36
2500
250
367.0
210.0
367.0
185.0
38.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHH 36
6 x 6, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225440/A
www.ti.com
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