PTPS7B4255QDYBRQ1 [TI]
具有 5mV 跟踪容差的汽车级、70mA、40V 电压跟踪低压降 (LDO) 稳压器 | DYB | 5 | -40 to 125;
| 型号： | PTPS7B4255QDYBRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 5mV 跟踪容差的汽车级、70mA、40V 电压跟踪低压降 (LDO) 稳压器 | DYB | 5 | -40 to 125 稳压器 |
| 文件： | 总23页 (文件大小：1566K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS7B4255-Q1
ZHCSOZ7 –JUNE 2022
TPS7B4255-Q1
具有5mV 跟踪容差的汽车类70mA、40V 电压跟踪LDO
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准：
TPS7B4255-Q1 是一款低压差 (LDO) 电压跟踪稳压
器，具有高跟踪精度以及出色的负载和线路瞬态响应。
该器件采用两种 5 引脚 SOT-23 封装（DBV 和
DYB）。TPS7B4255-Q1 旨在为动力总成系统等汽车
应用中的非板载传感器供电。该器件提供反极性、电池
和接地输出短路以及电流限制和热关断等集成保护功
能，可防止非板载电源系统中的高电缆故障风险。该器
件可保持 45V（绝对最大值）输入电压，从而维持负
载突降瞬态条件。
– 温度等级1：–40°C 至+125°C，TA
– 结温：–40°C 至+150°C，TJ
• 宽输入电压范围（-40V 至+40V）：
– 绝对最大输入范围：-40 V 至+45 V
• 宽输出电压范围：2V 至40V
• 非常严格的输出跟踪容差：5 mV（最大值）
• 低压降：70 mA 时为500 mV（最大值）
• 反极性保护
• 反向电流保护（电池短路）
• 组合基准和使能输入
• 轻负载时低静态电流：35μA
• 极宽的ESR 范围：
在 ADJ/EN 引脚上施加的基准电压可有效地对负载高
达 70mA 时的电压进行高精度缓冲。高跟踪精度为非
板载模块提供精确的电源，并在测量比例式传感器时实
现更高的精度。
– 与ESR（1mΩ 至3Ω）陶瓷输出电容器（1µF
至200µF）搭配使用时可保持稳定
• 过温保护
• 对接地和电源的输出短路保护
• 封装：5 引脚SOT-23 DBV 和DYB
通过将调节/使能输入引脚 (ADJ/EN) 置于低电平，
TPS7B4255-Q1 器件可切换至待机模式，从而更大限
度地降低静态电流。
封装信息(1)
封装尺寸（标称值）
器件型号
封装
2 应用
2.90mm × 1.60mm
2.93 mm x 1.50 mm
SOT-23 (5)、DBV
SOT-23 (5)、DYB
TPS7B4255-Q1
• 动力总成压力传感器
• 动力总成温度传感器
• 动力总成排气传感器
• 动力总成油液浓度传感器
• 车身控制模块(BCM)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
IN
OUT
IN
DC/DC converter
or LDO
TPS7B4255-Q1
ADJ/EN
OUT
5V
Sensor
1
MCU
ADC
Control Unit Board
典型应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBVS392
TPS7B4255-Q1
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Table of Contents
7.4 Device Functional Modes............................................8
8 Application and Implementation....................................9
8.1 Application Information............................................... 9
8.2 Typical Application.................................................... 10
8.3 Power Supply Recommendations.............................11
8.4 Layout....................................................................... 12
9 Device and Documentation Support............................14
9.1 接收文档更新通知..................................................... 14
9.2 支持资源....................................................................14
9.3 Trademarks...............................................................14
9.4 Electrostatic Discharge Caution................................14
9.5 术语表....................................................................... 14
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
Thermal Information..........................................................4
6.4 Electrical Characteristics.............................................5
TIming Characteristics...................................................... 5
7 Detailed Description........................................................6
7.1 Overview.....................................................................6
7.2 Functional Block Diagram...........................................6
7.3 Feature Description.....................................................6
Information.................................................................... 14
10.1 Mechanical Data..................................................... 15
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
June 2022
*
Initial release.
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5 Pin Configuration and Functions
ADJ/EN
GND
IN
1
2
3
5
GND
OUT
4
Not to scale
图5-1. DBV Package, 5-Pin SOT-23 (Top View)
ADJ/EN
1
2
3
5
4
GND
OUT
GND
IN
图5-2. DYB Package, 5-Pin SOT-23 (Top View)
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
ADJ/EN PIN. Connect the reference to this pin. This pin connects to the reference voltage. A low
signal below VIL disables the device and a high signal above VIH enables the device. Connect
the voltage reference directly or with a voltage divider for lower output voltages. To compensate
for line influences, place a capacitor close to this pin.
ADJ/EN
1
I
GND
GND
2
5
G
G
Ground pin. This pin is internally connected to pin 5 on the DYB package.
Ground pin. On the DYB package, this pin is internally connected to pin 2. On the DBV package
this pin is not internally connected, but connecting this pin to GND is recommended.
Input power-supply voltage pin. This pin is the device supply. For best transient response and to
minimize input impedance, use the recommended value or larger ceramic capacitor from IN to
GND as listed in the Recommended Operating Conditions table. Place the input capacitor as
close to the input of the device as possible to compensate for line influences.
IN
3
4
I
Regulated output voltage pin. A capacitor is required from OUT to GND for stability. For best
transient response, use the nominal recommended value or larger ceramic capacitor from OUT
to GND; see the Recommended Operating Conditions table. Place the output capacitor as close
to output of the device as possible.
OUT
O
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
-40
MAX UNIT
VIN
Unregulated input voltage
Regulated output voltage
Adjustable Input
45
45
V
V
VOUT
ADJ
TJ
–5
-0.3
–40
–65
45
V
Operating junction temperature range
Storage temperature
150
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
V(ESD)
Electrostatic discharge
All pins
V
Charged-device model (CDM), per AEC
Q100-011
Corner pins
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordancewith the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
40
UNIT
VIN
Unregulated input voltage
Regulated output voltage
Output current
3
V
V
VOUT
IOUT
COUT
ESR
CIN
2
0
40
70
mA
µF
Output capacitor(2)
1
200
3
Output capacitor ESR requirements
Input capacitor(1)
0.001
0
Ω
1
µF
TJ
Operating junction temperature
150
°C
–40
(1) For robust EMI performance the minimum input capacitance is 500 nF.
(2) Effective output capacitance of 500 nF minimum required for stability.
Thermal Information
TPS7B4255-Q1
THERMAL METRIC(1)
DBV (SOT-23)
5 PINS
176.3
75.6
DYB (SCT595)
UNIT
5 PINS
127.8
59.9
16.6
4.4
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
44.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
17.9
ΨJT
44.1
16.4
N/A
ΨJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.4 Electrical Characteristics
specified at TJ = –40°C to +150°C, VIN = 13.5 V, IOUT = 100 µA, COUT = 1 µF, 1 mΩ< COUT ESR < 2 Ω, CIN = 1 µF, and
VADJ = 5 V (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
Regulated output
Line regulation
Load regulation
TEST CONDITIONS
MIN
TYP
MAX
5
UNIT
mV
VOUT
VIN = VOUT + 600 mV to 40 V, IOUT = 100 µA to 70 mA
VIN = VOUT + 600 mV to 40 V, IOUT = 100 µA
–5
0.5
0.5
31
mV
ΔVOUT(ΔVIN)
ΔVOUT(ΔIOUT)
VIN = VOUT + 600 mV, IOUT = 100 µA to 70 mA (1)
VIN = 3 V to 40 V, VADJ = 2 V, IOUT = 0 mA, TJ = 25ºC
VIN = 3 V to 40 V, VADJ = 2 V, IOUT = 0 mA, -40ºC < TJ < 85ºC
VIN = 3 V to 40 V, VADJ = 2 V, IOUT = 0 mA
mV
TBD
IQ
Quiescent current
36
42
µA
VIN = 3 V to 40 V, VADJ = 2 V, IOUT = 70 mA, TJ = 25ºC
VIN = 3 V to 40 V, VADJ = 2 V, IOUT = 70 mA
600
800
500
355
3
IGND
Ground current
Dropout voltage
(2)
IOUT = 70 mA, VADJ ≥3.3 V, VIN = VADJ
VDO
mV
µA
(2)
IOUT = 50 mA, VADJ ≥4 V, VIN = VADJ
ISHUTDOWN
IADJ/EN
Shutdown supply current (IGND
)
VADJ/EN = 0 V
ADJ/EN pin current
VADJ/EN = VIN = 13.5 V
VIN rising, IOUT = 1 mA
VIN falling, IOUT = 1 mA
0.3
2.81
2.5
VUVLO(RISING)
VUVLO(FALLING)
VUVLO(HYST)
VIL
Rising input supply UVLO
Falling input supply UVLO
VUVLO(IN) hysteresis
2.6
2.3
2.7
2.4
V
300
mV
Adjust and enable logic input low level
0.7
V
Adjust and enable logic input high
level
VIH
2
ICL
Output current limit
VIN = VOUT + 1 V, VOUT short to 90% x VADJ
75
100
80
120
mA
dB
PSRR
Power-supply ripple rejection
VIN - VOUT = 1 V, Frequency = 100 Hz, IOUT = 70 mA
VOUT = 3.3 V, IOUT = 1 mA, a 5 µVRMS reference is used for
this measurement
Vn
Output noise voltage
150
µVRMS
IR
Reverse current at VIN
VIN = 0 V, VOUT = 20 V, VADJ = 5 V
VIN = -20 V, VOUT = 20 V, VADJ = 5 V
VIN = -20 V, VOUT = 0 V, VADJ = 5 V
-5
-5
5
5
IRN1
IRN2
TJ
Reverse current at negative VIN
Reverse current at negative VIN
Junction temperature
µA
-5
5
150
°C
°C
°C
–40
TSD(SHUTDOWN) Junction shutdown temperature
TSD(HYST) Hysteresis of thermal shutdown
175
20
(1) Power dissipation is limited to 2 W for device production testing purposes. The power dissipation can be higher during normal
operation. Please see the thermal dissipation section for more information on how much power the device can dissipate while
maintaining a junction temperature below 150℃.
(2) Measured when the output voltage VOUT has dropped 10 mV from the typical value.
TIming Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Timing Characteristics
tstartup Startup time
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Time from EN high to VOUT = 95% × VADJ, VADJ = 5 V
275
µs
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7 Detailed Description
7.1 Overview
The TPS7B4255-Q1 is an integrated, low-dropout (LDO) voltage tracker with ultra-low tracking tolerance.
Because of the high risk of cable shorts when powering sensors off-board, multiple protection features are built
into the LDO including short to battery, short to GND, and reverse current protection.
7.2 Functional Block Diagram
OUT
IN
V
V
reg
bat
2.2 µF
Logic
Control
Internal
Supply
Thermal
Shutdown
ADJ/EN
V
ref
GND
7.3 Feature Description
7.3.1 Regulated Output (VOUT
)
Because this device is a tracking LDO, the output voltage is determined by the voltage provided to the ADJ pin.
When the voltage at the ADJ pin exceeds the required voltage to enable the LDO, the output begins to rise to
the voltage on the ADJ pin. The output rises linearly as determined by the load, the output capacitor, and the
current limit. When the voltage reaches the level on the ADJ pin, the output voltage remains within a couple of
millivolts from the voltage set on the ADJ pin.
7.3.2 Undervoltage Lockout
The device has an internally fixed undervoltage lockout threshold. Undervoltage lockout activates when the input
voltage on VIN drops below the undervoltage lockout (UVLO) level. This activation ensures the regulator is not
latched into an unknown state during a low input supply voltage. If the input voltage has a negative transient that
drops below the UVLO threshold and recovers, the regulator shuts down and powers up in the standard power-
up sequence when the input voltage is above the required level.
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7.3.3 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 175°C, which
allows the device to cool. When the junction temperature cools to approximately 150°C, the output circuitry
enables. Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit
may cycle off and on. This cycling limits the dissipation of the regulator, thus protecting the regulator from
damage as a result of overheating.
The internal protection circuitry of the TPS7B4255-Q1 is designed to protect against overload conditions. The
circuitry is not intended to replace proper heat sinking. Continuously running the TPS7B4255-Q1 into thermal
shutdown degrades device reliability.
7.3.4 VOUT Short to Battery
When the output is shorted to the battery (as shown in 图 7-1), the TPS7B4255-Q1 survives and no damage
occurs to the device. A short to the battery can also occur when the device is powered by an isolated supply, as
shown in 图 7-2, at a lower voltage. In this case, the TPS7B4255-Q1 supply input voltage is set at 7 V when a
short to battery (14 V typical) occurs on VOUT, which typically runs at 5 V. The continuous reverse current that
flows out through VIN is less than 5 μA.
Automotive Battery,
14 V (typically)
Switch
Switch
V
bat
Automotive Battery,
14 V (typically)
TPS7B4255-Q1
IN
OUT
V
V
reg
bat
TPS7B4255-Q1
OUT
IN
V
1 µF
reg
2.2 µF
7-V V
I
1 µF
2.2 µF
5-V V
ref
5-V V
ref
ADJ/EN
GND
ADJ/EN
GND
图7-1. Output Voltage Short to Battery
图7-2. Output Voltage Higher Than the Input
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7.3.5 Tracking Regulator With an Enable Circuit
By pulling the reference voltage below 0.7 V, the device disables and enters a sleep state where the device
draws 3 μA (max) from the power supply. In a real application, the reference voltage is generally sourced from
another LDO voltage rail. A scenario where the device must be disabled without a shutdown of the reference
voltage can occur; the device can be configured as shown in 图 7-3 in this case. The TPS7B84-Q1 is a 150-mA
LDO with ultra-low quiescent current that is used as a reference voltage to the TPS7B4255-Q1 and also as a
power supply to the ADC. In a configuration as shown in 图7-3, the operational status of the device is controlled
by a microcontroller (MCU) input or output.
OUT
GND
IN
IN
OUT
V
ADC
bat
Sensor
22 µF
10 µF
47k
TPS7B84-Q1
10 µF
2.2 µF
TPS7B4255-Q1
EN
GND
ADJ/EN
100k
47k
MCU I/O
图7-3. Tracking an LDO With an Enable Circuit
7.4 Device Functional Modes
7.4.1 Operation With VIN < 4 V
The device operates with input voltages above 3 V to ensure proper operation. The device turns on when VIN is
greater than VUVLO(RISING) and VADJ is greater than VIH, and operates correctly as long as the input voltage stays
above 3 V. For voltages below 3 V and above VUVLO(FALLING), the LDO continues to operate but certain circuits
may not have the proper headroom to operate within specification. When the input voltage drops below
VUVLO(FALLING) the device shuts off again.
7.4.2 Operation With ADJ/EN Control
The ADJ pin operates as both the reference and EN pin to the LDO. When the input voltage is greater than
VUVLO(RISING) and VADJ is greater than VIH, the LDO is enabled and functional. When in this mode, the LDO
tracks the voltage at the ADJ pin because this pin functions as the reference to the control loop in the error
amplifier. When VIN is greater than VUVLO(RISING) and VADJ is lower than VIL, the LDO is disabled and is in a
lower power mode.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
Based on the end-application, different values of external components can be used. An application can require a
larger output capacitor during fast load steps to prevent a reset from occurring. Use a low ESR ceramic capacitor
with a dielectric of type X5R or X7R for better load transient response.
8.1.1 Input and Output Capacitor Selection
The TPS7B4255-Q1 requires an output capacitor of 1 µF or larger (500 nF or larger capacitance) for stability and
an equivalent series resistance (ESR) between 0.001 Ωand 3 Ω. For best transient performance, use X5R- and
X7R-type ceramic capacitors because these capacitors have minimal variation in value and ESR over
temperature. When choosing a capacitor for a specific application, be mindful of the DC bias characteristics for
the capacitor. Higher output voltages cause a significant derating of the capacitor. For best performance, the
maximum recommended output capacitance is 220 µF.
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. Some input supplies have a high impedance, thus placing the input capacitor on the input
supply helps reduce the input impedance. This capacitor counteracts reactive input sources and improves
transient response, input ripple, and PSRR. If the input supply has a high impedance over a large range of
frequencies, several input capacitors can be used in parallel to lower the impedance over frequency. Use a
higher-value capacitor if large, fast rise-time load transients are anticipated, or if the device is located several
inches from the input power source.
8.1.2 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. The following equation calculates the RDS(ON) of the device.
V
DO
R
=
(1)
DS(ON)
I
RATED
8.1.3 Reverse Current
The TPS7B4255-Q1 incorporates reverse current protection that prevents damage from a reverse polarity (that
is, when VOUT is higher than VIN). During a reverse polarity event where the VIN and VOUT absolute maximum
ratings are not violated and VOUT –VIN is less than 40 V, less than 5 μA flows out of VIN.
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8.2 Typical Application
图8-1 shows a typical application circuit for the TPS7B4255-Q1.
TPS7B4255-Q1
OUT
2.2 µF
IN
Vreg
Vbat
1 µF
ADJ/EN
Vref
GND
0.1 µF
图8-1. Typical Application Schematic
8.2.1 Design Requirements
Use the parameters listed in 表8-1 for this design example.
表8-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUES
Input voltage
3 V to 40 V
2 V to 20 V
2 V to 20 V
70 mA
ADJ reference voltage
Output voltage
Output current rating
Output capacitor range
Output capacitor ESR range
1 µF to 200 µF
1 mΩ to 3 Ω
8.2.2 Detailed Design Procedure
8.2.2.1 External Capacitors
An input capacitor, CIN, is recommended to help filter line influences. Connect the capacitors close to the device
pins.
The output capacitor for the TPS7B4255-Q1 is required for stability. Without the output capacitor, the regulator
oscillates. The actual size and type of the output capacitor can vary based on the application load and
temperature range. The effective series resistance (ESR) of the capacitor is also a factor in the device stability.
The worst case is determined at the minimum ambient temperature and maximum load expected. To ensure
stability of the TPS7B4255-Q1, the device requires an output capacitor between 1 µF and 200 µF with an ESR
range between 0.001 Ω and 3 Ω, which covers most types of capacitor ESR variation under the recommend
operating conditions. As a result, the output capacitor selection is flexible.
The capacitor must also be rated for all ambient temperatures expected in the system. To maintain regulator
stability down to –40°C, use a capacitor rated at that temperature.
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8.2.3 Application Curves
VI = 12 V, VADJ = 5 V, COUT = 1 μF, RLOAD = 4.7 kΩ
VI = 12 V, VADJ = 5 V, COUT = 1 μF, RLOAD = 4.7 kΩ
图8-2. Power Up
图8-3. Power Down
8.3 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 3 V to 40 V. If the input supply is
located more than a few inches from the TPS7B4255-Q1, add an electrolytic capacitor with a value of 10 µF and
a ceramic bypass capacitor at the input.
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8.4 Layout
8.4.1 Layout Guidelines
For best overall performance, place all circuit components on the same side of the circuit board and as near as
practical to the respective LDO pin connections. Place ground return connections to the input and output
capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side,
copper surface. The use of vias and long traces to the input and output capacitors is strongly discouraged and
negatively affects system performance. TI also recommends a ground reference plane either embedded in the
PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves to
assure accuracy of the output voltage, shield noise, and behaves similarly to a thermal plane to spread (or sink)
heat from the LDO device when connected to the thermal pad. In most applications, this ground plane is
necessary to meet thermal requirements.
8.4.1.1 Package Mounting
Solder-pad footprint recommendations for the TPS7B4255-Q1 are available at the end of this document and at
www.ti.com.
8.4.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
To improve AC performance (such as PSRR, output noise, and transient response), design the board with
separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device.
In addition, the ground connection for the output capacitor must connect directly to the GND pin of the device.
Equivalent series inductance (ESL) and ESR must be minimized in order to maximize performance and ensure
stability. Every capacitor must be placed as close as possible to the device and on the same side of the printed
circuit board (PCB) as the regulator.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use
of vias and long traces is strongly discouraged because of the negative impact on system performance. Vias and
long traces can also cause instability.
If possible, and to ensure the maximum performance denoted in this product data sheet, use the same layout
pattern used for the TPS7B4255-Q1 evaluation board, available at www.ti.com.
8.4.1.3 Power Dissipation and Thermal Considerations
方程式2 calculates the device power dissipation.
PD = IOUT × (VIN –VOUT) + IQ × VIN
(2)
where:
• PD = Continuous power dissipation
• IOUT = Output current
• VIN = Input voltage
• VOUT = Output voltage
• IQ = Quiescent current
Because IQ is much less than IOUT, the term IQ × VIN in 方程式2 can be ignored.
Calculate the junction temperature (TJ) with 方程式 3 for a device under operation at a given ambient air
temperature (TA).
TJ = TA + (RθJA × PD)
(3)
where:
• RθJA = Junction-to-junction-ambient air thermal impedance
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方程式4 calculates a rise in junction temperature because of power dissipation.
ΔT = TJ –TA = (RθJA × PD)
(4)
The maximum ambient air temperature (TAM) at which the device can operate can be calculated with 方程式 5
for a given maximum junction temperature (TJM).
TAM = TJM –(RθJA × PD)
(5)
8.4.2 Layout Examples
1
ADJ
GND
IN
GND
OUT
5
2
3
4
图8-4. DYB Package Layout Example
ADJ/EN
GND
1
5
GND
2
3
4
IN
OUT
图8-5. DBV Package Layout Example
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9 Device and Documentation Support
9.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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10.1 Mechanical Data
PACKAGE OUTLINE
DYB0005A
SOT - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SOT
1.29
1.15
2.85
2.55
1.1 MAX
0.2
C A B
1.6
1.4
0.1 C
B
A
PIN 1
INDEX AREA
1
5
2X 0.95
3.026
2.826
1.9
1.45
3
4
0.69
0.55
0.2
C A B
0.1
0.0
0.39
0.25
TYP
3X
0.2
C A B
0 -8 TYP
C
0.25
GAGE PLANE
SEATING PLANE
0.23
0.15
TYP
0.6
0.3
TYP
4226199/A 09/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. No JEDEC reference as of August 2020.
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EXAMPLE BOARD LAYOUT
DYB0005A
SOT - 1.1 max height
SOT
SYMM
5}X (1.1)
3X (0.6)
(0.8)
1
5
(1.4)
SYMM
3X (0.95)
(0.55)
3
4
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4226199/A 09/2020
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DYB0005A
SOT - 1.1 max height
SOT
SYMM
5X (1.1)
3X (0.6)
(0.8)
1
5
(1.4)
SYMM
(0.55)
3X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4226199/A 09/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTPS7B4255QDBVRQ1
PTPS7B4255QDYBRQ1
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DYB
5
5
3000
3000
TBD
TBD
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
Samples
Samples
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jul-2022
Addendum-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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