PUCC14241QDWNQ1 [TI]
Automotive, 2.0-W, 24-Vin, 25-Vout high-density > 5-kVRMS isolated DC/DC module
| DWN | 36 | -40 to 125;
| 型号： | PUCC14241QDWNQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Automotive, 2.0-W, 24-Vin, 25-Vout high-density > 5-kVRMS isolated DC/DC module | DWN | 36 | -40 to 125 |
| 文件： | 总46页 (文件大小：2567K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC14241-Q1
ZHCSRY5 – APRIL 2023
UCC14241-Q1 汽车类 2W、24V VIN、25V VOUT、高密度、
> 5kVRMS、隔离式直流/直流模块
1 特性
3 说明
•
采用隔离变压器的完全集成高密度隔离式直流/直流
UCC14241-Q1 是一款符合汽车标准的高隔离电压直
流/直流电源模块，旨在为 IGBT 或 SiC 栅极驱动器供
电。UCC14241-Q1 集成了具有专有架构的变压器和直
流/直流控制器，可实现高效率和超低的发射。高精度
输出电压可提供更好的通道增强，从而实现更高的系统
效率，不会对功率器件栅极造成过应力。
模块
•
•
•
隔离式直流/直流模块，用于驱动：IGBT、SiC FET
输入电压范围：21V 至 27V，绝对最大值为 32V
在 TA ≤ 85°C 时输出功率为 2.0W，在 TA = 105°C
时输出功率 > 1.5W
•
•
可调节的 (VDD – VEE) 输出电压（通过外部电阻
器）：在整个温度范围内为 15V 至 25V，调节精度
为 ±1.3%
可调节的 (COM – VEE) 输出电压（通过外部电
阻器）：在整个温度范围内为 2.5V 至 (VDD –
VEE)，调节精度为 ±1.3%
通过展频调制和集成变压器设计降低电磁发射
使能、电源正常、UVLO、OVLO、软启动、短路、
功率限制、欠压、过压和过热保护
CMTI > 150kV/µs
符合面向汽车应用的 AEC-Q100 标准
– 温度等级 1：–40°C ≤ TJ ≤ 150°C
– 温度等级 1: -40 °C ≤ TA ≤ 125°C
功能安全型
UCC14241-Q1 可以高效提供高达 2.0W（典型值）的
隔离输出功率。该模块需要非常少的外部元件，并且具
有片上器件保护功能，可提供额外的特性，例如输入欠
压锁定、过压锁定、输出电压电源正常比较器、过热关
断、软启动超时、可调隔离式正负输出电压、使能引脚
和开漏输出电源正常引脚。
•
•
封装信息
可订购器件型号(1)
封装
封装尺寸（标称值）
•
•
DWN（SSOP，
36）
PUCC14241QDWNRQ1
12.83 mm x 7.5 mm
DWN（SSOP，
36）
UCC14241QDWNRQ1
12.83 mm x 7.5 mm
•
•
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
– 有助于进行功能安全系统设计的文档
计划的安全相关认证：
录。
PG
PG
VDD
VDD
COUT2
– 符合 DIN EN IEC 60747-17 (VDE 0884-17) 标
准的 7071VPK 增强型隔离
R1
R2
ENA
ENA
VIN
RLIM
RLIM
FBVDD
FBVEE
COM
Source/
emitter
COUT1
VIN
R3
R4
– 符合 UL1577 标准且长达 1 分钟的 5000VRMS
隔离
COUT3
CIN
GNDP
VEE
VEE
– 符合 CQC GB4943.1 标准的增强型绝缘
36 引脚宽体 SSOP 封装
•
简化版应用
2 应用
•
混合动力、电动和动力总成系统 (EV/HEV)
– 逆变器和电机控制
– 车载充电器 (OBC) 和无线充电器
– 直流/直流转换器
•
电网基础设施
– 电动汽车充电站电源模块
– 直流充电（桩）站
– 串式逆变器
•
•
电机驱动器
– 交流逆变器和变频驱动器、机器人伺服驱动器
工业运输
典型上电序列
– 非公路用车电力驱动
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSF09
UCC14241-Q1
ZHCSRY5 – APRIL 2023
www.ti.com.cn
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 绝对最大额定值...........................................................6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................7
7.4 Thermal Information....................................................7
7.5 Power Ratings.............................................................7
7.6 Insulation Specifications............................................. 8
7.7 Safety-Related Certifications...................................... 9
7.8 Electrical Characteristics.............................................9
7.9 安全限值....................................................................12
7.10 Typical Characteristics............................................12
8 Detailed Description......................................................16
8.1 Overview...................................................................16
8.2 Functional Block Diagram.........................................17
8.3 Feature Description...................................................18
8.4 Device Functional Modes..........................................27
9 Application and Implementation..................................28
9.1 Application Information............................................. 28
9.2 Typical Application.................................................... 28
9.3 System Examples..................................................... 35
9.4 Power Supply Recommendations.............................36
9.5 Layout....................................................................... 36
10 Device and Documentation Support..........................39
10.1 Documentation Support.......................................... 39
10.2 接收文档更新通知................................................... 39
10.3 支持资源..................................................................39
10.4 Trademarks.............................................................39
10.5 静电放电警告.......................................................... 39
10.6 术语表..................................................................... 39
11 Mechanical, Packaging, and Orderable
Information.................................................................... 40
12 Tape and Reel Information..........................................41
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
April 2023
*
Advance Information release
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English Data Sheet: SLUSF09
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5 Device Comparison
表 5-1. Device Comparison Table
Output (VDD-VEE)
DEVICE NAME
VVIN Range
Typical power
Isolation rating
Adjustable Range
18 V to 25 V
15 V to 25 V
18 V to 25 V
18 V to 25 V
18 V to 25 V
12 V to 15 V
15 V to 18 V
10 V to 12 V
10 V to 18 V
UCC14240-Q1
UCC14241-Q1
21 V to 27 V
21 V to 27 V
8 V to 18 V
2 W
2 W
Basic
Reinforced
1 W
UCC14141-Q1
UCC14341-Q1
Reinforced
Reinforced
10.8 V to 13.2 V
13.5 V to 16.5 V
12 V to 15 V
15 V to 18 V
10 V to 18 V
14 V to 18 V
1.5 W
1.5 W
1.5 W
1.5 W
1 W
UCC14131-Q1
Reinforced
1 W
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6 Pin Configuration and Functions
GNDP
GNDP
PG
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VEE
2
VEEA
FBVDD
FBVEE
RLIM
VEE
3
ENA
4
GNDP
VIN
5
6
VIN
7
VEE
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
8
VDD
VDD
VEE
9
10
11
12
13
14
15
16
17
18
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
图 6-1. DWN Package, 36-Pin SSOP (Top View)
表 6-1. Pin Functions
PIN
TYPE (1)
DESCRIPTION
NAME
GNDP
NO.
1, 2, 5, 8, 9, 10,
11, 12, 13, 14,
15, 16, 17, 18
Primary-side ground connection for VIN. PIN 1,2, and 5 are analog ground. PIN 8, 9, 10, 11, 12,
13, 14, 15, 16, 17, and 18 are power ground. Place several vias to copper pours for thermal relief.
See Layout Guidelines.
G
Active low power-good open-drain output pin. PG remains low when (VVIN_UVLOP ≤ VVIN
≤
PG
3
4
O
I
VVIN_OVLO); (VVDD_UVP ≤ VFBVDD ≤ VVDD_OVP); (VVEE_UVP ≤ VFBVEE ≤ VVEE_OVP); TJ_Primary
TSHUTPPRIMARY_RISE; and TJ_secondary ≤ TSHUTSECONDARY_RISE
≤
Enable pin. Forcing ENA LOW disables the device. Pull HIGH to enable normal device
functionality. 5.5-V recommended maximum.
ENA
VIN
Primary input voltage. PIN 6 is for analog input, and PIN 7 is for power input. For PIN 7, connect
one 10-µF ceramic capacitor from power VIN PIN 7 to power GNDP PIN 8. Connect a 0.1-µF
high-frequency bypass ceramic capacitor close to PIN 7 and PIN 8.
6, 7
P
19, 20, 21, 22,
23, 24, 25,26,
27, 30,31, 36
Secondary-side reference connection for VDD and COM. The VEE pins are used for the high
current return paths.
VEE
G
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表 6-1. Pin Functions (continued)
PIN
TYPE (1)
DESCRIPTION
NAME
NO.
Secondary-side isolated output voltage from transformer. Connect a 2.2-µF and a parallel 0.1-µF
ceramic capacitor from VDD to VEE. The 0.1-µF ceramic capacitor is the high frequency bypass
and must be next to the IC pins. A 4.7-µF or 10-µF ceramic capacitor can be used instead of 2.2
µF to further reduce the output ripple voltage
VDD
28, 29
P
Secondary-side second isolated output voltage resistor to limit the source current from VDD to
COM node, and the sink current from COM to VEE. Connect a resistor from RLIM to COM to
regulate the (COM – VEE) voltage. See RLIM Resistor Selection for more detail.
RLIM
32
33
P
I
Feedback (COM – VEE) output voltage sense pin used to adjust the output (COM – VEE) voltage.
Connect a resistor divider from COM to VEE so that the midpoint is connected to FBVEE, and
the equivalent FBVEE voltage when regulating is 2.5 V. Add a 330-pF ceramic capacitor for high
frequency decoupling in parallel with the low-side feedback resistor. The 330-pF ceramic capacitor
for high frequency bypass must be next to the FBVEE and VEEA IC pins on top layer or back layer
connected with vias.
FBVEE
Feedback (VDD – VEE) output voltage sense pin and to adjust the output (VDD – VEE) voltage.
Connect a resistor divider from VDD to VEE so that the midpoint is connected to FBVDD, and
the equivalent FBVDD voltage when regulating is 2.5 V. Add a 330-pF ceramic capacitor for high
frequency decoupling in parallel with the low-side feedback resistor. The 330-pF ceramic capacitor
for high frequency bypass must be next to the FBVDD and VEEA IC pins on top layer or back
layer connected with vias.
FBVDD
VEEA
34
35
I
Secondary-side analog sense reference connection for the noise sensitive analog feedback inputs,
FBVDD and FBVEE. Connect the low-side feedback resistors and high frequency decoupling filter
capacitor close to the VEEA pin and respective feedback pin FBVDD or FBVEE. Connect to
secondary-side gate drive lowest voltage reference, VEE. Use a single point connection and place
the high frequency decoupling ceramic capacitor close to the VEEA pin. See Layout Guidelines.
G
(1) P = power, G = ground, I = input, O = output
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7 Specifications
7.1 绝对最大额定值
在自然通风条件下的工作温度范围内测得（除非另有说明）(1)
参数
引脚
最小值
-0.3
典型值
最大值
32
单位
V
VIN 至 GNDP
ENA、PG 至 GNDP
–0.3
-0.3
7
V
VDD、VEE、RLIM、FBVDD、FBVEE 至 VEE
总 (VDD-VEE) 输出功率 (TA = 25°C)
32
V
POUT_VDD_MAX
IRLIM_MAX_RMS_SOURCE
IRLIM_MAX_RMS_SINK
2.5
W
从 VDD 至 RLIM 的 RLIM 引脚最大均方根拉电流。
（在 24,500 小时的使用寿命内平均运行时间为 16%）
0.125
0.125
A)
A
从 RLIM 至 VEE 的 RLIM 引脚最大均方根灌电流。
（在 24,500 小时的使用寿命内平均运行时间为 16%）
TJ
工作结温范围
贮存温度
-40
150
150
°C
°C
Tstg
–65
(1) 应力超出绝对最大额定值 下所列的值可能会对器件造成永久损坏。这些列出的值仅仅是应力等级，这并不表示器件在这些条件下以及在
建议运行条件 以外的任何其他条件下能够正常运行。长时间处于绝对最大额定条件下可能会影响器件的可靠性。
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC
Q100-002((1))
±2000
V
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per AEC
Q100-011 Section 7.2
±500
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PIN
MIN
21
0
TYP
MAX
UNIT
VVIN
VENA
VPG
Primary-side input voltage to GNDP
Enable to GNDP
24
27
5.5
V
V
V
V
V
Powergood to GNDP
VDD to VEE
0
5.5
VVDD
VVEE
VFBVDD
15
2.5
25
COM to VEE
VDD-VEE
,
FBVDD, FBVEE to VEE
0
2.5
5.5
V
VFBVEE
TA
Ambient temperature
Junction temperature
–40
–40
125
150
°C
°C
((1))
TJ
(1) See the (VDD-VEE) and (COM-VEE) Load Recommended Operating Area section for maximum rated values across temperature and
VVIN conditions for different (VDD-VEE) and (COM-VEE) output voltage settings.
7.4 Thermal Information
DWN (SOIC)
THERMAL METRIC(1)
UNIT
36 PINS
52.3
28.5
25.9
16.6
25.6
–
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
VVIN = 24 V, CIN = 10µF, COUT = 2.2 uF, TJ = 150 °C, VENA = 5 V
PARAMETER
TEST CONDITIONS
TYP VALUE
UNIT
(VDD – VEE) = 25 V, PVDD-VEE = 2 W; (COM –
VEE) = 5 V, No Load from (VDD - COM) or (COM
- VEE)
PD
Power dissipation
1.65
W
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UNIT
ZHCSRY5 – APRIL 2023
7.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
VALUE
General
CLR
CPG
External clearance (1)
External creepage (1)
Shortest terminal-to-terminal distance through air
> 8
> 8
mm
mm
Shortest terminal-to-terminal distance across the
package surface
Minimum internal gap (internal clearance –
transformer power isolation)
> 120
µm
DTI
CTI
Distance through the insulation
Minimum internal gap (internal clearance –
capacitive signal isolation)
> 15.4
µm
V
Comparative tracking index
Material group
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
> 600
I
Rated mains voltage ≤ 300 VRMS
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I-IV
I-IV
I-III
Overvoltage category
DIN EN IEC 60747-17 (VDE 0884-17) (Planned Certification Targets) (2)
VIORM
Maximum repetitive peak isolation voltage
AC voltage (bipolar)
1414
1000
1414
7071
VPK
VRMS
VDC
AC voltage (sine wave) Time dependent dielectric
breakdown (TDDB) test
VIOWM
Maximum working isolation voltage
DC voltage
VTEST = VIOTM, t = 60s (qualification); VTEST = 1.2
× VIOTM, t = 1s (100% production)
VIOTM
VIMP
Maximum transient isolation voltage
Maximum impulse voltage ((3))
VPK
Tested in air, 1.2/50-μs waveform per IEC
62368-1
6250
VPK
VPK
Tested in oil (qualification test), 1.2/50 µs
waveform per IEC 62368-1
VIOSM
Maximum surge isolation voltage (3)
10000
Method a: After I/O safety test subgroup 2/3, Vini
= VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 1696
VPK, tm = 10 s
≤ 5
≤ 5
≤ 5
pC
pC
pC
Method a: After environmental tests subgroup 1,
qpd
Apparent charge (4)
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM
2262 VPK, tm = 10 s
=
Method b1: At routine test (100% production) and
preconditioning (type test) Vini = 1.2 × VIOTM, tini
1 s; Vpd(m) = 1.875 × VIORM = 2651 VPK, tm = 1 s
=
CIO
RIO
Barrier capacitance, input to output (5)
Isolation resistance, input to output (5)
VIO = 0.4 sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
< 3.5
> 1012
> 1011
> 109
2
pF
Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS = 150°C
Ω
Ω
Pollution degree
Climatic category
40/125/21
UL 1577 (Planned Certification Target)
VTEST = VISO = 5000 VRMS, t = 60 s (qualification);
VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100%
production)
VISO Withstand isolation voltage
5000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become
equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed-circuit board are used to help increase these
specifications.
(2) This coupler is suitable for safe electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall
be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
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(5) All pins on each side of the barrier tied together creating a two-terminal device
7.7 Safety-Related Certifications
VDE
UL
CQC
Plan to certify according to DIN EN IEC 60747-17
(VDE 0884-17)
Plan to certify under UL 1577 Component
Recognition Program
Plan to certify according to GB4943.1
Reinforced insulation Maximum transient isolation
voltage, 7071 VPK; Maximum repetitive peak
isolation voltage, 1414 VPK; Maximum surge
isolation voltage, 10000 VPK
Reinforced insulation, Altitude ≤ 5000 m, Tropical
Climate, 700 VRMS maximum working voltage
Single protection, 5000 VRMS
File number: (planned)
Certificate number: (planned)
Certificate number: (planned)
7.8 Electrical Characteristics
Over operating temperature range (TJ = –40 °C to 150 °C), VVIN = 21 V to 27 V, CIN = 10 µF, COUT = 2.2 µF, RLIM = 1 kΩ,
VENA = 5 V, unless otherwise noted. All typical values at TA = 25 °C and VVIN = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT SUPPLY (Primary-side. All voltages with respect to GNDP)
VVIN
Input voltage range
Primary-side input voltage to GNDP
VENA=0 V; VVIN=21 V - 27 V
21
24
27
V
IVINQ_OFF
VIN quiescent current, disabled
700
µA
VENA=5 V; VVIN=21 V - 27 V; (VDD-
VEE) =25-V regulating; IVDD-VEE = 0
mA. Single Output.
VIN operating current, enabled, No
Load
IVIN_ON_NO_LOAD
35
mA
mA
VENA=5 V; VVIN=21 V - 27 V; (VDD-
VEE) = 25-V regulating; IVDD-VEE = 60
mA. Single Output.
VIN operating current, enabled, Full
Load
IVIN_ON_FULL_LOAD
250
UVLOP COMPARATOR (Primary-side. All voltages with respect to GNDP)
VVIN_ANALOG_UVLO VIN analog undervoltage lockout rising Analog Comparator Always Active
7.8
7
8.2
7.4
8.5
7.7
V
V
threshold
First
P_RISING
VVIN_
VIN analog undervoltage lockout
falling threshold
Analog Comparator Always Active
First
ANALOG_UVLOP_FALL
ING
VIN undervoltage lockout rising
threshold
VVIN_UVLOP_RISING
19
20
18
21
V
V
VVIN_UVLOP_FALLIN VIN undervoltage lockout falling
17.1
18.9
threshold
G
OVLO COMPARATOR (Primary-side. All voltages with respect to GNDP)
VIN overvoltage lockout rising
VVIN_OVLO_RISING
threshold
29.45
27.55
31
29
32.55
30.45
V
V
VIN overvoltage lockout falling
VVIN_OVLO_FALLING
threshold
TSHUTP THERMAL SHUTDOWN COMPARATOR (Primary-side. All voltages with respect to GNDP)
TSHUTPPRIMARY_ Primary-side over-temperature
First time at power-up TJ needs to be
< 130 °C to turnon
140
15
150
20
160
25
°C
°C
shutdown rising threshold
RISE
TSHUTPPRIMARY_ Primary-side over-temperature
shutdown hysteresis
HYST
ENA INPUT PIN (Primary-side. All voltages with respect to GNDP)
Input voltage rising threshold, logic
HIGH
VEN_IR
Rising edge
1.25
0.84
1.95
V
Input voltage falling threshold, logic
LOW
VEN_IF
IEN
Falling edge
VENA = 5.0 V
1.44
10
V
Enable Pin Input Current
5
µA
PG OPEN-DRAIN OUTPUT PIN (Primary-side. All voltages with respect to GNDP)
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Over operating temperature range (TJ = –40 °C to 150 °C), VVIN = 21 V to 27 V, CIN = 10 µF, COUT = 2.2 µF, RLIM = 1 kΩ,
VENA = 5 V, unless otherwise noted. All typical values at TA = 25 °C and VVIN = 24 V.
PARAMETER
TEST CONDITIONS
Sink Current = 5 mA, power good
VPG = 5.5 V, power not good
MIN
TYP
MAX UNIT
VPG_OUT_LO
IPG_OUT_HI
PG output-low saturation voltage
PG Leakage current
0.5
5
V
µA
Primary-side Control (All voltages with respect to GNDP)
VVIN = 24 V; VENA = 5 V; (VDD-VEE) =
25 V
FSW
Switching frequency
11
13
90
15 MHz
kHz
Only during primary-side startup
starting after VIN > UVLOP, and ENA
= HIGH; FSS_BURST_P = 125 kHz
Frequency of Spread Spectrum
Modulation (SSM) triangle waveform
FSSM
SSM Percent change of carrier
frequency during Spread Spectrum
Modulation (SSM) by triangle
waveform
SSM Percentage
change of
FCARRIER
Only during primary-side startup
starting after VIN > UVLOP, and ENA
= HIGH; FSS_BURST_P = 125 kHz
5
%
Timer begins when VIN > UVLOP
and ENA = High and reset when
Powergood pin indicates Good
tSOFT_START_TIME_O
Primary-side soft-start time-out
28.4
ms
UT
(VDD-VEE) OUTPUT VOLTAGE (Secondary-side. All voltages with respect to VEE)
VVDD_RANGE
VVDD_RANGE
(VDD – VEE) Output voltage range
(VDD – VEE) Output voltage range
POUT_MAX up to 1.5W @ TA = 105oC
POUT_MAX up to 1.3W @ TA = 105oC
18
15
25
25
V
V
Secondary-side (VDD – VEE)
output voltage, over load, line and
temperature range, externally adjust
with external resistor divider
VVDD_DC_ACCURAC (VDD – VEE) Output voltage DC
-1.3
1.3
%
regulation accuracy
Y
(VDD-VEE) REGULATION HYSTERETIC COMPARATOR (Secondary-side. All voltages with respect to VEE)
Feedback regulation reference voltage
for (VDD – VEE)
VFBVDD_REF
(VDD – VEE) output in regulation
2.4675
2.5 2.5325
V
FBVDD Hysteresis comparator
hysteresis settings. Hysteresis at
the FBVDD pin. [The (VDD-VEE)
hysteresis would amplify this FBVDD
hysteresis by the feedback resistor
divider gain.]
VFBVDD_HYST
9
10
12.3
mV
(COM-VEE) OUTPUT VOLTAGE (Secondary-side. All voltages with respect to VEE)
Secondary-side (COM – VEE), adjust
with external resistor divider
(VDD-
VEE)
VVEE_RANGE
(COM – VEE) Output voltage range
2.5
V
Secondary-side (COM – VEE)
output voltage, over load, line and
temperature range, externally adjust
with external resistor
(COM - VEE)
Output voltage DC
regulation accuracy
VVEE_DC_ACURACY
–1.3
1.3
%
divider
VISO2 REGULATION HYSTERETIC COMPARATOR (Secondary-side. All voltages with respect to VEE)
Feedback regulation reference voltage
for (COM – VEE)
VFBVEE_REF
(COM – VEE) output in regulation
Rising threshold
2.4675
2.5 2.5325
0.73
V
V
VRLIM_SHORT_CHRG Rlim Short Charge comparator rising
threshold to exit PWM
_CMP_RISE
tRLIM_SHORT_CHRG_ On-Time during RLIM pin Short
RLIM pin < 0.645 V, while FBVEE pin
< 2.48 V
1.2
5
us
us
Charge PWM mode
ON_TIME
tRLIM_SHORT_CHRG_ Off-Time during RLIM pin Short
RLIM pin < 0.645 V, while FBVEE pin
< 2.48 V
Charge PWM mode
OFF_TIME
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Over operating temperature range (TJ = –40 °C to 150 °C), VVIN = 21 V to 27 V, CIN = 10 µF, COUT = 2.2 µF, RLIM = 1 kΩ,
VENA = 5 V, unless otherwise noted. All typical values at TA = 25 °C and VVIN = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
(VDD-VEE) UVLOs COMPARATOR (Secondary-side. All voltages with respect to VEE)
(VDD – VEE) undervoltage lockout
rising threshold
VVDD_UVLO_RISING
VVDD_UVLO_HYST
Voltage at FBVDD
Voltage at FBVDD
0.9
0.2
V
V
(VDD – VEE) undervoltage lockout
hysteresis
(VDD-VEE) OVLOs COMPARATOR (Secondary-side. All voltages with respect to VEE)
(VDD – VEE) over-voltage lockout
rising threshold
VVDD_OVLOS_RISING
Voltage from VDD to VEE, rising
Voltage from VDD to VEE, falling
29.45
27.55
31
29
32.55
30.45
V
V
VVDD_OVLOS_FALLIN (VDD – VEE) over-voltage lockout
falling threshold
G
SOFT-START (Secondary-side. All voltages with respect to VEE)
Blank out time after soft start before
tblankout
PG for (VDD-VEE) UVP and (COM-
VEE) UVP & OVP
3
ms
(VDD-VEE) UVP, UNDER -VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE)
(VDD – VEE) under-voltage protection
rising threshold, VUVP = VREF × 90%
VVDD_UVP_RISING
VVDD_UVP_HYST
2.175
2.25
20
2.35
V
(VDD – VEE) under-voltage protection
hysteresis
mV
(VDD-VEE) OVP, OVER-VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE)
(VDD – VEE) over-voltage lockout
rising threshold, VOVP = VREF ×110%
VVDD_OVP_RISING
VVDD_OVP_HYST
2.7
2.75
20
2.825
V
(VDD – VEE) over-voltage protection
hysteresis
mV
(COM-VEE) UVP, UNDER -VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE)
(COM – VEE) under-voltage protection
rising threshold, VUVP = VREF × 90%
VVEE_UVP_RISING
VVEE_UVP_HYST
2.1
2.25
20
2.4
V
(COM – VEE) under-voltage protection
hysteresis
mV
(COM-VEE) OVP, OVER-VOLTAGE PROTECTION COMPARATOR (Secondary-side. All voltages with respect to VEE)
(COM – VEE) over-voltage protection
rising threshold, VOVP = VREF × 110%
VVEE_OVP_RISING
VVEE_OVP_HYST
2.7
2.75
20
2.825
V
(COM – VEE) over-voltage protection
hysteresis
mV
TSHUTS THERMAL SHUTDOWN COMPARATOR (Secondary-side. All voltages with respect to VEE)
TSHUTSSECONDAR Secondary -side over-temperature
First time at power-up Tj needs to be <
130oC to turnon.
145
15
150
20
155
25
°C
°C
shutdown rising threshold
Y_RISE
TSHUTSSECONDAR Secondary-side over-temperature
shutdown hysteresis
Y_HYST
CMTI (Common Mode Transient Immunity)
Positive VEE with respect to GNDP
Negative VEE with respect to GNDP
150
V/ns
V/ns
CMTI
Common Mode Transient Immunity
-150
INTEGRATED MAGLAM TRANSFORMER (Primary-side to Secondary-side. Note: these values unique for each version of XFMR)
N
Transformer effective turns ratio
Secondary side to primary side
1.18
-
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7.9 安全限值
参数
测试条件
最大值
单位
RθJA = 52.3°C/W，VVIN = 27V，TJ = 150°C，TA
= 25°C，POUT = 2.5W ((1)) ((2))
188
250
mA
IS
安全输入均方根电流
RθJA = 52.3°C/W，VVIN = 21V，TJ = 150°C，TA
mA
= 25°C，POUT = 2.5W ((1)) ((2))
RθJA = 52.3°C/W，TJ = 150°C，TA = 25°C ((1))
PS
TS
安全功率耗散（输入功率 - 输出功率）
2.39
150
W
((2))
((1)) ((2))
安全温度
°C
(1) 最高安全温度 TS 具有与为器件指定的最大结温 TJ 相同的值。IS 和 PS 参数分别表示安全电流和安全功率耗散。请勿超出 IS 和 PS 的最
大限值。这些限值随环境温度 TA 的变化而变化。
(2) 在“热性能信息”表中，结至空气热阻 RθJA 是安装在引线式表面贴装封装、高 K JEDEC 测试板上的器件的热阻。可以使用这些公式计算
每个参数的值：TJ = TA + RθJA × P，其中 P 为器件中耗散的功率。TJ(max) = TS = TA + RθJA × PS，其中 TJ(max) 为最大允许结温。
7.10 Typical Characteristics
图 7-1. SOA Derating Curves: VVDD-VEE = 18 V, VCOM-VEE = 5 V, No
图 7-2. SOA Derating Curves: VVDD-VEE = 20 V, VCOM-VEE = 5 V, No
Load.
Load
图 7-3. SOA Derating Curves: VVDD-VEE = 25 V, VCOM-VEE = 5 V, No Load
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7.10 Typical Characteristics (continued)
图 7-4. Start-up: VIN = 24 V, VVDD-VEE = 25 V, VCOM-VEE = 5 V, No 图 7-5. Shutdown: VIN = 24 V, VVDD-VEE = 25 V, VCOM-VEE = 5 V, No
Load
Load
图 7-6. Load Transient Response: No Load to 1 W, VIN = 24 V,
图 7-7. Load Transient Response: 1 W to No Load, VIN = 24 V,
VVDD-VEE = 25 V, VCOM-VEE = 5 V
VVDD-VEE = 25 V, VCOM-VEE = 5 V
图 7-8. VVDD-VEE Load Regulation: VIN = 21 V, VVDD-VEE = 25 V,
图 7-9. VVDD-VEE Load Regulation: VIN = 24 V, VVDD-VEE = 25 V,
VCOM-VEE = 5 V
VCOM-VEE = 5 V
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7.10 Typical Characteristics (continued)
图 7-11. VCOM-VEE Load Regulation: VIN = 21 V, VVDD-VEE = 25 V,
图 7-10. VVDD-VEE Load Regulation: VIN = 27 V, VVDD-VEE = 25 V,
VCOM-VEE = 5 V
VCOM-VEE = 5 V
图 7-12. VCOM-VEE Load Regulation: VIN = 24 V, VVDD-VEE = 25 V,
图 7-13. VCOM-VEE Load Regulation: VIN = 27 V, VVDD-VEE = 25 V,
VCOM-VEE = 5 V
VCOM-VEE = 5 V
图 7-14. Efficiency vs Load on VVDD-VEE: VIN = 21 V, VVDD-VEE
=
图 7-15. Efficiency vs Load on VVDD-VEE: VIN = 24 V, VVDD-VEE =
25 V, VCOM-VEE = 5 V, No Load on VCOM-VEE
25 V, VCOM-VEE = 5 V, No Load on VCOM-VEE
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7.10 Typical Characteristics (continued)
图 7-17. Input Current vs Load on VVDD-VEE: VIN = 21 V, VVDD-VEE
图 7-16. Efficiency vs Load on VVDD-VEE: VIN = 27 V, VVDD-VEE
=
= 25 V, VCOM-VEE = 5 V, No Load on VCOM-VEE
25 V, VCOM-VEE = 5 V, No Load on VCOM-VEE
图 7-18. Input Current vs Load on VVDD-VEE: VIN = 24 V, VVDD-VEE
图 7-19. Input Current vs Load on VVDD-VEE: VIN = 27 V, VVDD-VEE
= 25 V, VCOM-VEE = 5 V, No Load on VCOM-VEE
= 25 V, VCOM-VEE = 5 V, No Load on VCOM-VEE
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8 Detailed Description
8.1 Overview
UCC14241-Q1 device is suitable for applications that have limited board space and require more integration.
These devices are also suitable for very-high voltage applications, where power transformers meeting the
required isolation specifications are bulky and expensive. The low-profile, low-center of gravity, and low weight
provides a higher vibration tolerance than systems using large bulky transformers. The device is easy-to-use
and provides flexibility to adjust both positive and negative output voltages as needed when optimizing the
gate voltage for maximum efficiency while protecting gate oxide from over-stress with its tight voltage regulation
accuracy.
The device integrates a high-efficiency, low-emissions isolated DC/DC converter for powering the gate drive of
SiC or IGBT power devices in traction inverter motor drives, industrial motor drives, or other high voltage DC/DC
converters. This DC/DC converter provides greater than 1.5 W of power.
The integrated DC/DC converter uses switched mode operation and proprietary circuit techniques to reduce
power losses and boost efficiency. Specialized control mechanisms, clocking schemes, and the use of an on-
chip transformer provide high efficiency and low radiated emissions.
The integrated transformer provides power delivery throughout a wide temperature range while maintaining
a 5000-VRMS isolation, and an 1000-VRMS continuous working voltage. The low isolation capacitance of the
transformer provides high CMTI allowing fast dv/dt switching and higher switching frequencies, while emitting
less noise.
The VVIN supply is provided to the primary-side power controller that switches the input stage connected to the
integrated transformer. Power is transferred to the secondary-side output stage, and regulated to a level set by
the resistor divider connected between the (VDD – VEE) pin and the FBVDD pin with respect to the VEE pin.
The output voltage is adjustable with external resistor divider allowing a wide (VDD – VEE) range.
For optimal performance ensure to maintain the VVIN input voltage within the recommended operating voltage
range. Do not exceed the absolute maximum voltage rating to avoid over-stressing the input pins.
A fast hysteretic feedback burst control loop monitors (VDD – VEE) and ensures the output voltage is kept
within the hysteresis with low overshoots and undershoots during load and line transients. The burst control
loop enables efficient operation across full load and allows a wide VOUT adjustability throughout the whole VVIN
range. The undervoltage lockout (UVLO) protection monitors the input voltage pin, VIN, with hysteresis and input
filter ensuring robust system performance under noisy conditions. The overvoltage lockout (OVLO) protection
monitors the input voltage pin, VIN, protects against over-voltage stress by disabling switching and reducing the
internal peak voltage. Controlled soft-start timing, provided throughout the full power-up time, limits the peak
input inrush current while charging the output capacitor and load.
The UCC14241-Q1 also provides a second output rail, (COM – VEE), that is used as a negative bias for the gate
drivers, allowing quicker turn-off switching for the IGBTs, and also to protect from unwanted turn-on during fast
switching of SiC devices. (COM – VEE) has a simple, yet fast and efficient bias controller to ensure the positive
and negative rails are regulated during the PWM switching. The COM pin can be connected from the source of
SiC device or emitter of an IGBT device. An external current limiting resistor allows the designer to program the
sink and source current peak according to the needs of the gate drive system.
A fault protection and powergood status pin provides a mechanism for the host controller to monitor the status
of the DC/DC converter and provide proper sequencing of power and PWM control signals to the gate driver.
Fault protection includes undervoltage, overvoltage, over-temperature shutdown, and a 100 μs isolated channel
communication interface watchdog timer.
A typical soft-start ramp-up time is approximately 3 ms, but varies based on input voltage, output voltage, output
capacitance, and load. If either output is shorted or over-loaded, the device is not able to power-up within the
28.4-ms soft-start watch-dog-timer protection time, so the device latches off for protection. The latch can be
reset by toggling the ENA pin or powering VIN down and up.
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The output load must be kept low until start-up is complete and PG pin is low. When powering up, do not apply a
heavy load to (VDD – VEE) or (COM – VEE) outputs until the /PG pin has indicated power is good (pulling logic
low) to avoid problems providing the power to ramp-up the voltage.
TI recommends to use the PG status indicator as a trigger point to start the PWM signal into the gate driver. PG
output removes any ambiguity as to when the outputs are ready by providing a robust closed loop indication of
when both (VDD –VEE) and (COM – VEE) outputs have reached their regulation threshold within ±10%.
Do not allow the host to begin PWM to gate driver until after PG goes low. This action typically occurs less than
28.4 ms after VVIN > VVIN_UVLOP and ENA goes high. The /PG status output indicates the power is good after soft
start of (VDD – VEE) and (COM – VEE) and are within ±10% of regulation.
If the host is not monitoring PG, then ensure that the host does not begin PWM to gate driver until 30 ms after
VVIN > VVIN_UVLOP and ENA goes high to allow enough time for power to be good after soft start of VDD and
VEE.
8.2 Functional Block Diagram
VIN
VDD
Q1
Q2
Q3
Q4
Source
D1
D3
RLIM
Sink
D2
D4
GNDP
VEE
Gate-drive logic
and
level shifting
Oscillator
SSM
FBVEE
Enable
Power off/on
FBVDD
ENA
PG
Secondary-
side feedback
regulation
and
RX
TX
Primary-side
controller and
fault monitoring
+
fault monitoring
VREF
VEEA
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8.3 Feature Description
8.3.1 Power Stage Operation
The UCC14241-Q1 module uses an active full-bridge inverter on the primary-side and a passive full-bridge
rectifier on the secondary-side. The small integrated transformer has a relatively high carrier frequency to reduce
the size for integrating into the 36-pin SSOP package. The power stage carrier frequency operates within 10
MHz to 16 MHz. The power stage carrier frequency is determined by input voltage with a feed-forward control:
when VVIN is 21 V, the frequency is 16 MHz; when VVIN is 27 V, the frequency is 10 MHz; when VVIN is between
21 V and 27 V, the frequency reduces gradually from 16 MHz to 10 MHz as VVIN voltage rises. Spread spectrum
modulation, SSM, is used to reduce emissions. ZVS operation is maintained to reduce switching power losses.
The UCC14241-Q1 module creates two regulated outputs. It can be configured as a single output converter,
VDD to VEE only, or a dual-output converter, VDD to VEE and COM to VEE. Even though the module uses VEE
as the reference point to create two positive output voltages, the outputs can use COM as the reference point
and become a positive and a negative output.
These two outputs are controlled independently through hysteresis control. Furthermore, the VDD-VEE is the
main output, and COM to VEE uses the main output as its input to created a second regulated output voltage.
8.3.1.1 VDD-VEE Voltage Regulation
The VDD-VEE output is the main output of the module. The power stage operation is determined by the sensed
VDD-VEE voltage on FBVDD pin. As shown in 图 8-1, the VDD-VEE voltage is sensed through a voltage divider
RFBVDD_TOP and RFBVDD_BOT. When FBVDD voltage stays below the turn-off threshold, roughly 10 mV above the
VFBVDD_REF, the power stage operates, delivers power to the secondary side and makes the VDD-VEE output
voltage rise. After the output reaches the turn-off threshold, the power stage turns off. Output voltage drops
because of the load current. After the output voltage drops below the turn-on threshold, roughly 10 mV below the
VFBVDD_REF, the power stage is turned on again. With the accurate voltage reference and hysteresis control, the
VDD-VEE output voltage can be regulated with high accuracy. To improve the noise immunity, a small capacitor
of 330 pF should be added between FBVDD and VEE pins. Excessive capacitor slows down the hysteresis loop
and can cause excessive output voltage ripple or even stability issue.
Power stage
VIN
VDD
RFBVDD_TOP
FBVDD
GNDP
COUT1
–
+
CFBVDD
RFBVDD_BOT
VFBVDD_REF
VEE
图 8-1. VDD-VEE Voltage Regulation
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8.3.1.2 COM-VEE Voltage Regulation
COM-VEE output takes VDD-VEE output as its input and creates a regulated output voltage. It can be
considered as an LDO output from VDD-VEE, though the operation principle is not quite the same. Given
its input voltage is VDD-VEE, the maximum output voltage from COM to VEE is the voltage between VDD and
VEE.
The COM-VEE output regulator stage uses the internal high-side or low-side FETs in series with the external
current-limit resistor (RLIM) to charge or discharge the COM-VEE output voltage. The hysteresis control is used
to control the switching instance of the two FETs, to achieve an accurately regulated COM-VEE voltage. As
shown in 图 8-2, the COM-VEE output voltage is sensed through the voltage divider RFBVEE_TOP and RFBVEE_BOT
on FBVEE pin. TI recommends a 330-pF capacitor on FBVEE pin to filter out the switching frequency noise.
When the voltage on FBVEE is below the charging threshold, 20 mV below the VFBVEE_REF, the charging resistor
is kept on and discharging resistor is kept off. COM-VEE output voltage rises. After FBVEE voltage reaches
the stop charging threshold, 20 mV above the VFBVEE_REF, the charging resistor is turned off. Output voltage
rise stops. When the charging resistor is turned off, the discharge resistor is controlled by another hysteresis
controller, based on FBVEE pin voltage, with the same reference voltage VFBVEE_REF, and 20-mV of hysteresis.
The COM-VEE output regulator stage will protect from having the high-side FET stay ON for a long time
during a COM to VEE short. This protection feature is implemented by monitoring the RLIM-pin voltage
and controlling the high-side FET duty-ratio. When the COM pin voltage is lower than 0.645 V while the
FBVEE voltage is below 2.48 V, the hysteretic control of the COM-VEE regulator is overridden by an
approximately 20 % duty-ratio control on high-side FET, with a typical on-time of tRLIM_SHORT_CHRG_ ON_TIME
and off-time of tRLIM_SHORT_CHRG_ OFF_TIME in each duty cycle. When the COM pin voltage is higher than
VRLIM_SHORT_CHRG_CMP_RISE, the duty ratio control is disabled and the hysteretic control resumes to normal
operation.
VDD
VDD
COUT2
RLIM
COM
RCharge
+
–
VFBVEE_REF
RLIM
SW
20 mV
RFBVEE_TOP
FBVEE
COUT3
SW
+
–
RDischarge
VFBVEE_REF
1.25 mV
RFBVEE_BOT
CFBVEE
VEE
VEE
图 8-2. COM-VEE Voltage Regulation
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2.52V
2.50125V
VFBVEE_REF = 2.5V
2.48V
TurnON
Charge FET
TurnON
Charge FET
TurnOFF
CHARGE FET
Discharge Comparitor
Discharge Control
TurnON
Discharge FET
图 8-3. COM-VEE Voltage Regulation Diagram
8.3.1.3 Power Handling Capability
The maximum power handling capability is determined by both circuit operation and thermal condition. For a
given output voltage, the maximum power increases with input voltage before triggering the thermal protection.
An over-power-protection (OPP) is implemented to limit maximum output power and reduces power stage RMS
current at high input voltage. The OPP is implemented by a feed-forward control from the input voltage to the
OPP burst duty cycle (DOPP). The DOPP adds a "baby" burst within the on-time of "Mama" burst from the main
feedback loop for the (VDD-VEE) regulation. When the input voltage increases, the DOPP reduces automatically
to limit the averaged output power.
At high ambient temperature, the thermal performance determines the maximum power and safe operating area
(SOA). A protective thermal shut-down is triggered after overtemperature is detected. The high-efficiency and
optimized thermal design for transformer and silicon provide a high power handling capability at high ambient
temperature in a small package.
(VDD-VEE)
OPP burst
(VDD-VEE) burst
图 8-4. Diagram of Over-Power-Protection with baby burst
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8.3.2 Output Voltage Soft Start
UCC14241-Q1 power-up diagram of two output rails with soft start is shown in 图 8-5. After VVIN > VVIN_UVLOP
and ENA is pulled high, the soft-start sequence starts with burst duty cycle control with soft duty cycle increment.
The burst duty cycle gradually increases from 12.5% to 50% over time by the primary-side control signal
(DSS_PRI), so both VVDD-VEE and VCOM-VEE increase ratiometrically with a controlled shallow rising slope. When
VVDD-VEE is increased above VVDD_UVLOS, there is a sufficient bias voltage for the feedback-loop communication
channel, so the burst feedback control on the secondary side takes over. As a result, the DSS_PRI is pulled high
and does not affect burst duty cycle anymore. The burst duty cycle is determined by comparing VFBVDD and
VREF. VREF increases from 0.9V to 2.5 V with seven increment steps, where the first 0.4-V step boosts VREF
from 0.9V to 1.1V, and then the following six 0.2-V steps boosts VREF from 1.1V to 2.5V. Each step lasts 128
µs. After VVDD-VEE > VVDD_UVP, the RLIM source-sink regulator for VCOM-VEE is enabled. The polarity of source or
sink current of RLIM pin is determined by comparing VFBVEE and VREF so as to keep VCOM-VEE in tight regulation.
Once VVDD-VEE or VCOM-VEE rises across its UVP threshold, there is a 3-ms (typical) blanking time for VVDD-VEE
UVP and VCOM-VEE UVP and OVP, and then the power good signal is issued by pulling PG voltage low. The
3-ms (typical) blanking time is only applied during start up before the power good signal is issued. It provides
enough time for both VVDD-VEE and VCOM-VEE to settle in their hysteresis band of regulation after start up, so that
the converter does not shut down due to the overshoot or undershoot during start up.
The soft-start feature greatly reduces the input inrush current during power-up. In addition, if VVDD-VEE cannot
reach to VVDD_UVLOS within 28.4 ms, then the device shuts down in a safe-state. The 28.4-ms soft-start time-out
protects the module under output short circuit condition before power up.
VIN
VIN_UVLOP
tdelay
UVLOP
ENA
PG
D = 12.5%
D = 25%
D = 50% D = 100%
DSS(PRI)
VDD_UVLOS
Comparator_Enable
2.5V
128µs
VVDD_OVP
VREF
VVDD_UVP
VVEE_OVP
VVEE_UVP
VVDD_UVLOS
VVDD-VEE
VCOM-VEE
RLIM Comparator_Enable
图 8-5. Output voltage Soft-Start Diagram
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8.3.3 ENA and PG
The ENA input pin and PG output pin on the primary-side use 5-V TTL and 3.3-V LVTTL level logic thresholds.
The active-high enable input (ENA) pin is used to turn-on the isolated DC/DC converter of the module. Either
3.3-V or 5-V logic rails can be used. Maintain the ENA pin voltage below 5.5 V. After ENA pin voltage becomes
above the enable threshold VEN_IR, UCC14241-Q1 enables, starts switching, goes through the soft-start process
and delivers power to the secondary side. After ENA pin voltage falls below the disable threshold VEN_IF
UCC14241-Q1 disables, stops switching.
,
The ENA pin can also be used to reset the UCC14241-Q1 device after it enters the protection safe-state mode.
After a detected fault, the protection logic will latch off and place the device into a safe state. When all the faults
are cleared, the ENA-pin can be used to clear the UCC14241-Q1 latch by toggling the ENA pin voltage below
VEN_IF for longer than 150 μs, then toggling back up to 3.3 V or 5 V. The device will then exit the latch-off mode
and we initiate a soft-start. 图 8-6 illustrates the latch-off reset timing.
ENA
150 µs
Latched-off
Latch-off state
Latch-off reset
Run
Power-stage state
Stop
PG
Delay time
determined by
output condition
图 8-6. Latch-off Reset Using ENA Pin
The active-low power-good (PG) pin is an open-drain output that indicates (short) when the module has no fault
and the output voltages are within ±10% of the output voltage regulation setpoints. Connect a pull-up resistor (>
1 kΩ) from PG pin to either a 5-V or 3.3-V logic rail. Maintain the PG pin voltage below 5.5 V without exceeding
its recommended operating voltage. The logic of PG pin can be illustrated using 图 8-7.
1.1×VFBVDD_REF
+
–
FBVDD
+
–
0.9×VFBVDD_REF
Isolation
+
1.1×VFBVEE_REF
PG
–
FBVEE
+
–
0.9×VFBVEE_REF
Protections (Over-temperature, output over
voltage, input UVLO, input OVLO)
+
ENA
VEN_IR/VEN_IF
GNDP
–
图 8-7. PG Pin Logic
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8.3.4 Protection Functions
UCC14241-Q1 is equipped with a full feature of protection functions, include input undervoltage lockout,
overvoltage lockout protections, output undervoltage protection, overvoltage protection, overpower protection,
and over-temperature protection. The input undervoltage and overvoltage lockout protections have the auto
recovery response. All other protections have the latch-off response. After the latch-off-response protections are
triggered, the converter enters a latch off state, stops switching until the latch is reset by either toggling the ENA
pin Off then On, or by lowering the VVIN voltage below the VVIN_ANALOG_UVLOP_FALLING threshold, and then above
the VVIN_UVLOP_RISING threshold.
8.3.4.1 Input Undervoltage Lockout
UCC14241-Q1 can take wide input voltage range, from 21 V to 27 V. When the input voltage becomes too low,
the output either cannot be regulated due to the transformer turns ratio limitation, or the converter operates with
too much current stress. Either way, the converter must shut down to protect the system.
The UCC14241-Q1 enters input undervoltage lockout when VVIN voltage becomes lower than the UVLO
threshold VVIN_UVLOP_FALLING. In UVLO mode, the converter stops switching. After VIN pin voltage becomes
lower than the VIN analog undervoltage lockout falling threshold VVIN_VULOP_FALLING , UCC14241-Q1 resets all
the protections. After that, after the VVIN voltage becomes above the UVLO threshold VVIN_UVLOP_RISING, the
converter is enabled. Depending on the ENA pin voltage, the converter can start switching, go through the
soft-start process, or in the disable mode, waiting for ENA pin voltage becomes high.
8.3.4.2 Input Overvoltage Lockout
The input overvoltage lockout protection is used to protect the UCC14241-Q1 devices from overvoltage damage.
It has an auto-recovery response. When the VVIN pin voltage becomes higher than the input overvoltage lockout
threshold VVIN_OVLO_RISE, switching stops, converter stops sending energy to the secondary side. After input
overvoltage lockout protection, after VVIN pin voltage drop below the recovery threshold VVIN_OVLO_FALLING
,
depending on the ENA pin voltage status, the converter can either resuming operation, go through the full
soft-start process, or in the disabled mode, wait for ENA pin becomes high. The input overvoltage lockout does
not reset other latch-off protections.
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8.3.4.3 Output Overvoltage Protection
The UCC14241-Q1 devices sense the output voltage through FBVDD and FBVEE pins to control the output
voltage. To prevent the output voltage becomes too high, damages the load or UCC14241-Q1 device itself, the
UCC14241-Q1 devices are equipped with the output overvoltage protection. There are two levels of overvoltage
protection, based on the feedback pin voltage, and the output voltage.
During the normal operation, because of load transient, or load unbalancing between two outputs, the output
voltages can exceed its regulation level. Based on the pin voltages on FBVDD and FBVEE, after the voltage
exceeds the threshold, VVDD_OVP_RISE, or VVEE_OVP_RISE (10% above the target regulation voltage), the converter
stops switching immediately.
In rare cases, the voltage divider becomes malfunction and gives the wrong output voltage information. In
turn, the control loop can regulate the output voltages at a wrong voltage level. The UCC14241-Q1 device
is also equipped with a fail-safe overvoltage protection. After the VDD-VEE voltage becomes higher than
the overvoltage protection threshold VVDD_OVLOS_RISE, the converter shuts down immediately. This fail-safe
protection level is set at 31 V. It is meant to protect UCC14241-Q1 devices, instead of the load. The design must
ensure the voltage feedback divider normal operation at all conditions.
The output overvoltage protections have the latch-off response.
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8.3.4.4 Overpower Protection
The Over Power Protection, OPP, limits the maximum average output power. When the output is overloaded,
it is important to shutdown the module to prevent it from further damage, or propagating the fault into other
portion of the entire system. Given the extremely high switching frequency, it is not practical to implement the
traditional cycle-by-cycle current limit. Instead, the UCC14241-Q1 device relies on the Over Power Protection
(OPP) working together with the output undervoltage protection.
As discussed in Power Handling Capability, with the input voltage feedforward, and the "baby" burst duty cycle
adjustment, the maximum power delivery capability of the UCC14241-Q1 is well controlled. The impact of OPP
on the relationship between Vin and maximum output power is shown in 图 8-8.
Max
Power
Disable OPP
Enable OPP
Vin
图 8-8. Maximum Output Power Under Different Input Voltage Condition
When the load exceeds the maximum power delivery capability, the output voltage starts to droop. When the
output voltage falls below the Under Voltage Protection threshold, the output undervoltage protection is triggered
and the parts latches off into a safe state.
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8.3.4.4.1 Output Undervoltage Protection
The output voltage under voltage protection is based on the FBVDD and FBVEE pin voltages. When the FBVDD
pin voltage becomes lower than its UVP threshold VVDD_UVP_FALL, or the FBVEE pin voltage becomes lower than
its UVP threshold VVEE_UVP_FALL, the undervoltage protection is activated. The UCC14241-Q1 stops switching,
and the PG pin becomes open.
During soft start, the output voltages rise from zero. Both FBVDD and FBVEE pin voltage are below the
UVP thresholds. The UVP is disabled during the soft start. If the pin voltage cannot reach the UVP recovery
thresholds (VVDD_UVP_RISE, VVEE_UVP_RISE) after the soft start completes, undervoltage protection is activated.
The UCC14241-Q1 stops switching, and the PG pin becomes open.
The undervoltage protection has a latched-off response. After it is activated, the latch-off state can be cleared by
recycling VVIN. Toggling ENA pin can also reset the latch-off state. Refer to ENA and PG section for details.
8.3.4.5 Overtemperature Protection
UCC14241-Q1 integrates the primary-side, secondary-side power stages, as well as the isolation transformer.
The power loss caused by the power conversion causes the module temperature higher than the ambient
temperature. To ensure the safe operation of the power module, the UCC14241-Q1 device is equipped
with over-temperature protection. Both the primary-side power stage, and the secondary-side power stage
temperatures are sensed and compared with the over-temperature protection threshold. If the primary-side
power stage temperature becomes higher than TSHUTPPRIMARY_RISE, or the secondary-side power stage
temperature becomes higher than TSHUTSSECONDARY_RISE , the module enters over-temperature protection
mode. The module stops switching; PG pin becomes open. After protection, the module enters latch-off mode.
When the power stage temperature drops below the over-temperature recovery threshold, recycling VVIN, or
toggling ENA pin voltage brings the model out of latch-off mode. Depending on ENA pin voltage, the module
either starts switching, delivering power to the secondary side, or in the standby mode waiting for ENA pin
voltage becomes high.
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8.4 Device Functional Modes
Depending on the input and output conditions, ENA pin voltage, as well as the device temperature, the
UCC14241-Q1 operates in one of the below operation modes.
1. Disable mode. In this mode, the module is off, but waiting for ENA pin becoming high to start operate.
2. Soft-start mode. In this mode, the module starts to deliver power to the secondary side. The primary-side
operation duty cycle and secondary-side references are raised gradually to reduce the stress to the module.
3. Normal operation mode. In this mode, the module operates normally, delivers power to the secondary side.
4. Protection mode, auto-recovery. In this mode, the module is off, due to the input UVLO or OVLO protection.
After the input voltage fault is cleared, depending on the ENA pin voltage condition, it either becomes
disabled mode if the ENA pin voltage is low, or it goes through soft-start mode to the normal operation mode.
5. Protection mode, latched-off. In this mode, the module is off, due to other protections. The module remains
off even the fault causing the protection is cleared. Recycling VVIN operation must ensure the input voltage
goes below the analog UVLO falling threshold (VVIN_ ANALOG_UVLOP_FALLING ) first to reset the latch-off state,
or the ENA pin is toggled Low (OFF) then High (ON).
表 8-1 lists the supply functional modes for this device. The ENA pin has an internal weak pull-down resistance
to ground, but TI does not recommend leaving this pin open.
表 8-1. Device Functional Modes
INPUT
ENA
OUTPUTS
Operation Mode
V(VDD – VEE)
V(COM – VEE)
VVIN
FAULT
PG Open Drain
High
Isolated Output1 Isolated Output2
Protection mode,
auto-recovery
VVIN < VVIN_UVLOP_RISING
X
X
OFF
OFF
OFF
OFF
VVIN_UVLOP_RISING < VVIN
VVIN_OVLO_RISING
<
LOW
HIGH
HIGH
X
X
High
Disable mode
VVIN_UVLOP_RISING < VVIN
VVIN_OVLO_RISING
<
<
Regulating at
Setpoint
Regulating at
Setpoint
NO FAULT
YES FAULT
X
Low
Normal operation
VVIN_UVLOP_RISING < VVIN
VVIN_OVLO_RISING
Protection mode,
latched-off
OFF
OFF
OFF
OFF
High
Protection mode,
auto-recovery
VVIN > VVIN_OVLO_RISING
High
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The UCC14241-Q1 device is suitable for applications that have limited board space and desire more integration.
This device is also suitable for very high voltage applications, where power transformers meeting the required
isolation specifications are bulky and expensive.
9.2 Typical Application
The following figures show the typical application schematics for the UCC14241-Q1 device configurations
supplying an isolated load.
GNDP
GNDP
PG
VEE
VEEA
FBVDD
FBVEE
RLIM
VEE
VDD
COUT2
PG
ENA
ENA
RLIM
GNDP
COM
RFBVEE_TOP
VIN
VIN
VEE
CIN
VIN
VDD
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
CFBVEE
VDD
RFBVEE_BOT
COUT3
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
RFBVDD_TOP
COUT1
CFBVDD
RFBVDD_BOT
图 9-1. Dual Adjustable Output Configuration
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GNDP
GNDP
PG
VEE
VEEA
FBVDD
FBVEE
RLIM
VEE
VDD
RFBVDD_TOP
PG
ENA
ENA
GNDP
RFBVDD_BOT
CVINA
CFBVDD
VIN
RVINA
VEE
VIN
VIN
VDD
CIN
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
COUT2
VDD
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
COUT1
图 9-2. Single Adjustable Output Configuration
9.2.1 Design Requirements
Designing with the UCC14241-Q1 module is simple. First, choose single output or dual output. Determine the
voltage for each output and then set the regulation through resistor dividers. The gate charge of the power
device determines the amount of output decoupling capacitance needed at the gate driver input. Calculate the
RLIM resistor value for regulating the (COM – VEE) voltage rail for a dual output. Finally, add the recommended
input and output capacitors according to the procedure below.
9.2.2 Detailed Design Procedure
Place ceramic decoupling capacitors as close as possible to the device pins. For the input supply, place the
capacitors between pins 6 to 7 (VIN) and pins 8 to 9 (GNDP). For the isolated output supply, (VDD – VEE),
place the capacitors between pins 28 to 29 (VDD) and pins 30 to 31 (VEE). For the isolated output supply,
(COM – VEE), place an RLIM resistor between the RLIM pin and the gate driver COM supply input. Also place
decoupling capacitors at the gate driver supply pins (VDD and COM) and at gate driver supply pins (COM and
VEE) with values according to the following component calculation sections. These locations are of particular
importance to all the decoupling capacitors because the capacitors supply the transient current associated with
the fast switching waveforms of the power drive circuits. Ensure the capacitor dielectric material is compatible
with the target application temperature.
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9.2.2.1 Capacitor Selection
The UCC14241-Q1 device creates an isolated output VDD-VEE as its main output. The device also creates
a second output COM-VEE, using VDD-VEE as its power source. Because both outputs are isolated from
the input, and sharing VEE as the common reference point, the UCC14241-Q1 outputs can be configured as
dual-output two-positive, dual-output two-negative, or dual-output one-positive and one-negative. UCC14241-Q1
output can also be used as a single positive output or single negative output.
When the module is configured as dual-output, one-positive output, one-negative output; it is very important to
properly select the output capacitor ratios COUT2 and COUT3 to optimize the regulation and avoid causing an
over-voltage or under-voltage fault.
表 9-1. Calculated Capacitor Values
CAPACITOR
VALUE (µF)
NOTES
Place two 10-μF and a 0.1-μF high-frequency decoupling capacitor in parallel close to VIN
pins. A capacitance greater than 20 uF can be used to reduce the voltage ripple when the
series impedance from the voltage source to the VIN pins is large.
CIN
20 + 0.1
Add a 10-μF and a 0.1-μF capacitor for high-frequency decoupling of (VDD – VEE). Place
close to the VDD and VEE pins. A capacitance greater than 10 uF can be used to reduce
the output voltage ripple.
COUT1
10 + 0.1
Bulk charge, decoupling output capacitors are required at the gate driver pins. The COUT2
and COUT3 capacitance ratio is important to optimize the dual output voltage divider accuracy
during charge or discharge switching cycles.
COUT2
COUT3
See below
See below
The selection of COUT2 and COUT3 is based on the gate charge requirement for the gate driver load, the charge
balancing during the start-up, and the expected maximum current loading.
During the startup, the ratio between COUT2 and COUT3 must be equal to the ratio between (COM−VEE) and
(VDD−COM) and offset by the loading current from VDD-COM and COM-VEE, to allow both COM to VEE and
VDD to VEE voltages reaches steady state at the same time, as shown in 方程式 1.
First calculate the COUT2 value based on the Gate charge of the power device QG_Total, whether IGBT or SiC
power MOSFET, and the percent of voltage droop wanted during the turn-on of the gate with respect to the
positive gate voltage applied, VDD to COM.
where
Q
G_Total
C
=
(1)
OUT2
Percent_Cdroop
× V
VDD − COM
100
•
QG_Total is the total gate charge of the power switch
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Then calculate the COUT3 value based on the output voltage ratios, the load current expected, and the variation
of the output capacitors.
C
× V
× I
− I
OUT2
VDD − COM
MAX_POWER
COM − VEE
VDD − COM
C
=
(2)
OUT3
V
× I
− I
COM − VEE
MAX_POWER
where the load IVDD-COM and ICOM-VEE are the load currents respectively, and the IMAX_POWER is the SOA
Maximum Power (PMAX_SOA) at 25oC ambient temperature divided by the VVDD-VEE output voltage.
I
I
= I
+ I
(3)
(4)
VDD − COM
COM − VEE
Q_Driver_VDD −COM
Otℎer_load_VDD −COM
= I
+ I
Q_Driver_COM − VEE
Otℎer_load_COM − VEE
where
•
•
•
I(VDD-COM) is the total current from VDD to COM, excluding average gate drive current.
I(COM-VEE) is the total current from COM to VEE, excluding average gate drive current.
IQ_DRIVER_VDD-COM is the maximum quiescent current of the gate driver from (VDD – COM), and any current
pulled from VDD by external logic must be included.
•
•
•
IQ_DRIVER_COM-VEE is the maximum quiescent current of the gate driver from (COM – VEE),
IOther_load_VDD-COM is the maximum current pulled from VDD to COM by external logic.
IOther_load_COM-VEE is the maximum current pulled from COM to VEE by external logic.
and
P
MAX
VDD − VEE
I
=
V
(5)
POWER
The approximate PMAX value can be extracted from the provided SOA curves at the 25oC ambient temperature.
Calculate COUT3 using worst case capacitor values based on expected variation, COUT2_maximum. This action
makes sure the capacitor ratio tends to push the COM-VEE voltage to a slightly lower value than the target
regulation value during start up.
备注
COUT2 and COUT3 are the total capacitance on the VDD and VEE outputs. They include the capacitors from both
the isolated bias supply and the gate driver circuit.
The sizes of COUT2 and COUT3 are determined by the gate driver load gate charge and ripple voltage
requirement. COUT1 can then be used to reduce the total ripple voltage and to soften the start-up time.
Please also be noted that the ceramic capacitors lose their capacitance when voltage is applied. The design
needs to consider the reduced capacitance due to the DC bias effect.
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9.2.2.2 RLIM Resistor Selection
The UCC14241-Q1 device creates an isolated output VDD-VEE as its main output. It also creates a second
output COM-VEE, using VDD-VEE as its power source. Because both outputs are isolated from the input, and
sharing VEE as the common reference point, the UCC14241-Q1 outputs can be configured as dual-output
two-positive, dual-output two-negative, or dual-output one-positive and one-negative, as shown in 图 9-3.
VDD
RLIM
VEE
VOUT1
VDD
RLIM
VEE
COM
VIN
VIN
VOUT2
VOUT2
GNDP
GNDP
VOUT1
COM
(a) Dual-output, two-positive
(b) Dual-output, two-negative
VDD
RLIM
VEE
VOUT1
VIN
COM
GNDP
VOUT2
(c) Dual-output, one-positive, one-negative
图 9-3. Dual output configurations
When the module is configured as dual-positive or dual-negative outputs, the RLIM resistor is a true current
limiting resistor. Set up the RLIM resistor value as the maximum load current needed for VCOM-VEE, using 方程式
6. IVOUT2_max is the maximum load current for VCOM-VEE output.
V
COM − VEE
R
=
− R
LIM_INT
(6)
LIM
I
VDD − COM _max
RLIM_INT is the internal switch resistance value of 30 Ω typical.
For isolated gate driver applications, one positive and one negative outputs are needed. In this case, VDD-VEE
is the total output voltage, and the middle point becomes the reference point. Because the total voltage between
VDD and VEE is always regulated through the FBVDD feedback, the RLIM pin only must regulate the middle
point voltage so that it can give the correct positive and negative voltages. The RLIM control is achieved through
FBVEE pin as described in COM-VEE Voltage Regulation.
Based on Capacitor Selection, when selecting the output capacitor ratio proportional to the voltage ratio, the
capacitors form a voltage divider. The middle point voltage must naturally give the correct positive and negative
voltages. At the same time, for the gate driver circuit, the gate charge pulled out from the positive rail capacitor
during turn-on is fed back to the negative rail capacitor during turn-off, the two output rail load must always be
balanced. However, due to the gate driver circuit quiescent current unbalancing, and the two-rail capacitance
tolerances, the middle point voltage can move away with time. The RLIM pin provides an opposite current to
keep the middle point voltage at the correct level.
As illustrated in 图 9-4 (a), without considering the gate charge, the gate driver circuit quiescent current loads the
positive rail and negative rail differently. The net current shows up as a DC offset current to the middle point.
As illustrated in 图 9-4 (b), every time the gate driver circuit turns-on the main power switch, it pulls the charge
out of the positive and negative rail output capacitors. When the module power stage provides energy to the
secondary side, refreshing those capacitors, the same charge is fed into both capacitors. If the capacitor values
are perfect, the voltage rise in the capacitors will be proportional. The positive and negative voltages would not
change. However, due to the capacitor tolerances, the capacitor values are not perfectly matched. The voltages
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will rise at different ratios with the smaller capacitor rising faster. Over time, the middle point voltage, COM,
would pull to a different value. A load across one of the capacitors will pull towards a voltage imbalance. The
RLIM function counteract the voltage imbalance and bring the COM voltage back into regulation.
VDD=Q/COUT2
VEE=Q/COUT3
ISO Driver
ISO Driver
Iq_off=Iq_VDD−Iq_VEE
VDD/ VEE=COUT3/COUT2
VDD
VDD
VDD
RLIM
VEE
VDD
RLIM
VEE
Q
COUT2
Iq_VDD
VIN
VDD
VEE
VIN
COM
Iq_off
OUT
COM
VEE
COM
Q
COM
Iq_VEE
GNDP
COUT3
GNDP
COM
VEE
(a) Load current unbalancing
(b) Capacitance unbalancing
图 9-4. Source of voltage unbalancing
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Considering these two effects, the RLIM must provide enough current to compensate this offset current. The
RLIM must be low enough to provide enough current, but not too low otherwise the middle point voltage is
corrected at each turn on and turn off edge of the gate driver and excessive power loss is generated.
The RLIM resistor chosen can provide enough current for the load using the following equations, whichever has
lower RLIM value. 方程式 7 shows source current due to capacitor variation and gate driver quiescent current
(IQ). 方程式 8 shows sink current due to capacitor variation and IQ.
R
(7)
(8)
LIM_MAX
V
VDD − COM
=
C
× 1 − ∆ C
C
OUT3
× 1 − ∆ C
OUT3
× 1 − ∆ C
OUT3
+ C
−
× Q
× f
+
I
− I
COM − VEE VDD − COM
G_Total
SW
C
C
+ C
OUT2
OUT3
OUT2
OUT2
OUT3
OUT3
− R
LIM_INT
R
LIM_MAX
V
COM − VEE
=
C
× 1 − ∆ C
C
OUT2
× 1 − ∆ C
OUT2
+ C × 1 − ∆ C
OUT3
OUT2
−
× Q
× f
+
I
− I
COM − VEE VDD − COM
G_Total
SW
C
+ C
C
OUT2
OUT3
OUT2
OUT2
OUT3
− R
LIM_INT
Select RLIM value to be the lowest of either 1) the RLIM needed for capacitor imbalance and the load, or 2) the
RLIM needed to respond to a 10% overshoot of VCOM-VEE within 1.5 ms with the given load current.
where
V
COM − VEE
R
=
− R
LIM_INT
(9)
LIM_MAX_for_oversℎoot
0 . 10 × V
COM − VEE
C
×
+ I
− I
VDD − COM COM − VEE
OUT3_max
1 . 5 ms
•
•
QG_Total is the total gate charge of power switch.
fSW is the switching frequency of gate drive load.
RLIM value determines response time of (COM – VEE) regulation. Too low an RLIM value can cause oscillation
and can overload (VDD – VEE). Too high an RLIM value can give offset errors, due to slow response. If RLIM is
greater than above calculations, then there is not enough current available to replenish the charge to the output
capacitors, causing a charge imbalance where the voltage is not able to maintain regulation, and eventually
exceeds the OVP2 or UVP2 FAULT thresholds and shutting down the device for protection. Choose RLIM value
to be 10% less than the smaller value of the two calculated results.
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9.3 System Examples
The UCC14241-Q1 module is designed to allow a microcontroller host to enable it with the ENA pin for proper
system sequencing. The /PG output also allows the host to monitor the status of the module. The /PG pin goes
low when there are no faults and the output voltage is within ±10% of the set target output voltage. The output
voltage is meant to power a gate driver for either IGBT or SiC FET power device. The host can start sending
PWM control to the gate driver after the /PG pin goes low to ensure proper sequencing. Shown below is the
system diagram for the dual-output configuration and a system diagram for the single output configuration.
VIN
VDD
VDD
VIN
CIN
GNDP
COUT2
Buck
RLIM
COUT1
EMITTER/
SOURCE
400-800V
RLIM
Open- Drain
From Battery
COM
/PG
COUT3
ENA
5V/3.3V
VEE
VEE
EMITTER/
SOURCE
Microcontroller
VDD
VCC
5V/3.3V
VCC
/PG_BIAS
PWM
Control
GATE
VEE
PWM
ON_BIAS
To Motor
GNDP
-
Similar Isolated DC DC + Isolated Gate Driver Block as Above
图 9-5. Dual Output System Configuration
VIN
VDD
VDD
VIN
CIN
GNDP
Buck
RLIM
COUT
400-800V
RLIM
Open- Drain
From Battery
/PG
ENA
5V/3.3V
GATE
VEE
VEE
EMITTER
/ SOURCE
EMITTER
/ SOURCE
Microcontroller
VDD
VCC
5V/3.3V
VCC
/PG_BIAS
PWM
Control
GATE
VEE
PWM
ON_BIAS
To Motor
GNDP
-
Similar Isolated DC DC + Isolated Gate Driver Block as Above
图 9-6. Single Output System Configuration
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9.4 Power Supply Recommendations
The recommended input supply voltage (VVIN) for UCC14241-Q1 is between 21 V and 27 V. To help ensure
reliable operation, adequate decoupling capacitors must be located as close to supply pins as possible. Local
bypass capacitors must be placed between the VIN and GNDP pins at the input; between VDD and VEE at the
isolated output supply; and COM and VEE at the lower voltage output supply. TI recommends low ESR, ceramic
surface mount capacitors. TI further suggests placing two such capacitors: one with a value of 2.2 μF for supply
bypassing and an additional 0.1-μF capacitor in parallel for high frequency filtering. The input supply must have
an appropriate current rating to support output load required by the end application.
9.5 Layout
9.5.1 Layout Guidelines
The UCC14241-Q1 integrated isolated power solution simplifies system design and reduces board area usage.
Follow these guidelines for proper PCB layout to achieve optimum performance.
•
Place decoupling capacitors as close as possible to the device pins. For the input supply, place the
capacitors between pin 7 (power VIN) and pins 8–18 (power GNDP). For the isolated output supply, place
the capacitors between pin 28, 29 (VDD) and pins 19–25, 30–31, 35–36 (VEE). This location is of particular
importance to the input decoupling capacitor because this capacitor supplies the transient current associated
with the fast switching waveforms of the power drive circuits.
The capacitors between pin 6 (analog VIN) and pins 1, 2, and 5 (analog GNDP) are optional and
recommended.
•
•
•
•
•
•
Because the device does not have a thermal pad for heat-sinking, the device dissipates heat through the
respective GND pins. Ensure that enough copper (preferably a connection to the ground plane) is present on
GNDP and VEE pins for best heat-sinking.
If space and layer count allow, TI recommends to connect the VIN, GNDP, VDD, and VEE pins to internal
ground or power planes through multiple vias. Alternatively, make the traces that are connected to these pins
as wide as possible to minimize losses.
Minimize capacitive coupling between the RLIM pin and the FBVEE pin by separating the traces while
routing, and if possible use a via near the FBVEE pin to route the feedback connection through a different
layer.
A minimum of four layers is recommended to accomplish a good thermal PCB design. Inner layers can be
used to create a high-frequency bypass capacitor between GNDP and VEE, which in turn mitigates radiated
emissions.
Pay close attention to the spacing between primary ground plane (GNDP) and secondary ground plane
(VEE) on the outer layers of the PCB. The effective creepage and clearance of the system is reduced if the
two ground planes have a lower spacing than that of the UCC14241-Q1 package.
To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces or
copper below the UCC14241-Q1 module.
9.5.2 Layout Example
The layout example shown in the following figures is from the evaluation board UCC14241-Q1EVM,
UCC14240EVM-052, and based on the 图 9-1 design.
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图 9-7. UCC14241-Q1EVM, PCB Top Layer, Assembly (same EVM used as UCC14240-Q1)
图 9-8. UCC14241-Q1EVM, Signal Layer 2 (Same as Layer 3)
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图 9-9. UCC14241-Q1EVM, Signal Layer 3 (Same as Layer 2)
图 9-10. UCC14241-Q1EVM, PCB Bottom Layer, Assembly (Mirrored View)
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10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
For related documentation, see the following:
•
Texas Instruments, Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs Requiring
Single, Positive or Dual, Positive/Negative Bias Power user's guide
•
Texas Instruments, Isolation Glossary
10.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI
的《使用条款》。
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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12 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
UCC14241-Q1
SSOP
DWN
36
750
330.0
16.4
10.85
13.4
4.0
16.0
16.0
Q1
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PUCC14241QDWNQ1
ACTIVE
SO-MOD
DWN
36
37
TBD
Call TI
Call TI
-40 to 125
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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Copyright © 2023，德州仪器 (TI) 公司
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