RF430FRL152H [TI]
具有 SPI/I2C 接口和 14 位 Δ-Σ ADC 的 NFC ISO15693 传感器感应器;型号: | RF430FRL152H |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 SPI/I2C 接口和 14 位 Δ-Σ ADC 的 NFC ISO15693 传感器感应器 传感器 |
文件: | 总54页 (文件大小:2658K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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RF430FRL152H, RF430FRL153H, RF430FRL154H
ZHCSD28C –NOVEMBER 2012–REVISED DECEMBER 2014
RF430FRL15xH NFC ISO 15693 传感器应答器
1 器件概述
1.1 特性
1
– 紧凑型时钟系统
• 兼容 ISO/IEC 15693 和 ISO/IEC 18000-3(模式
1)标准的射频 (RF) 接口
• 电源系统采用电池或 13.56MHz 磁场供电
• 14 位 Σ-Δ 模数转换器 (ADC)
• 内部温度传感器
• 电阻传感器偏置接口
• CRC16 CCITT 发生器
• MSP430™ 混合信号微控制器
– 2KB FRAM
•
•
•
4MHz 高频时钟
256kHz 内部低频时钟源
外部时钟输入
– 具有 3 个捕捉/比较寄存器的 16 位 Timer_A
– LV 端口逻辑
•
•
•
400µA 时,VOL 低于 0.15V
400µA 时,VOH 高于 (VDDB – 0.15V)
所有端口均可提供 Timer_A PWM 信号
– eUSCI_B 模块支持 3 线和 4 线 SPI 和 I2C
– 32 位看门狗定时器 (WDT_A)
– 4KB SRAM
– 8KB ROM
– 电源电压范围:1.45V 至 1.65V
– 低功耗
– ROM 开发模式(将 ROM 地址映射到 SRAM 以
进行固件开发)
– 全 4 线制 JTAG 调试接口
• 如需完整的模块描述,请参见《RF430FRL15xH 系
列技术参考手册》(文献编号:SLAU506)
• 关于应用操作和编程,请参见《RF430FRL15xH 固
件用户指南》(文献编号:SLAU603)
•
•
激活模式 (AM):140µA/MHz (1.5V)
待机模式 (LPM3):16µA
– 16 位精简指令集计算机 (RISC) 架构
– 最高 2MHz CPU 系统时钟
1.2 应用
•
工业无线传感器
•
医用无线传感器
1.3 说明
RF430FRL15xH 器件是一款 13.56MHz 应答器芯片,该芯片中包含可编程的 16 位 MSP430™ 低功耗微控
制器。 该器件采用嵌入式通用 FRAM 非易失性存储器来存储程序代码或用户数据,例如校准和测量数据。
RF430FRL15xH 支持通过兼容 ISO/IEC 15693 和 ISO/IEC 18000-3(模式 1)标准的 RFID 接口以及 SPI
或 I2C 接口进行通信、参数设置和配置。 该器件具有内部温度传感器功能和板载 14 位 Σ-Δ 模数转换器
(ADC),支持传感器测量,并且可通过 SPI 或 I2C 来连接数字传感器。
RF430FRL15xH 器件经过优化可在完全无源(无电池)或单节电池供电(半有源)模式下运行,从而延长
便携式和无线传感应用中电池的使用寿命。 FRAM 是非易失性存储器,其完美结合了 SRAM 的速度、灵活
性和耐用性与闪存的稳定性和可靠性,并且总功耗更低。
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLAS834
RF430FRL152H, RF430FRL153H, RF430FRL154H
ZHCSD28C –NOVEMBER 2012–REVISED DECEMBER 2014
www.ti.com.cn
器件信息(1)
封装
器件型号
RF430FRL152H
封装尺寸(2)
4mm x 4mm
4mm x 4mm
4mm x 4mm
VQFN (24)
VQFN (24)
VQFN (24)
RF430FRL153H
RF430FRL154H
(1) For the most current part, package, and ordering information for all available devices, see the Package
Option Addendum in 节 9, or see the TI web site at www.ti.com.
(2) 这里显示的尺寸为近似值。 要获得包含误差值的封装尺寸,请参见节 9中的机械数据。
1.4 功能方框图
图 1-1 显示了 RF430FRL15xH 器件的框图。
RST/NMI
P1.0 to P1.7
VDDB VSS VDDH
LF-OSC
HF-OSC
VDDSW
VDD2X
VDDD
CP1
IO Port
8 I/Os
with
interrupt
capability
Power
Supply
System
CRC
Reset
Int-Logic
8KB
ROM
4KB
RAM
2KB
FRAM
ACLK
Clock
System
CLKIN
16 bit
SMCLK
CP2
MCLK
MAB
CPU and
Working
Registers
TMS, TCK,
TDI, TDO
ANT2
4W-JTAG
ISO
15693
Decode
and
ISO
15693
Analog
Front End
Timer_A
eUSCI_B0
14-Bit
Sigma-
Delta
Debug
support
Watchdog
WDTA
32/16 Bit
CRES
LRES
3 CC
Registers
SPI
I2C
ADC
Encode
ANT1
ADC0/ADC1/ADC2
TEMP1/TEMP2
图 1-1. 功能框图
2
器件概述
版权 © 2012–2014, Texas Instruments Incorporated
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com.cn
ZHCSD28C –NOVEMBER 2012–REVISED DECEMBER 2014
内容
1
器件概述.................................................... 1
5.17 JTAG ................................................ 18
5.18 RFPMM, Power Supply Switch ..................... 19
5.19 RFPMM, Bandgap Reference....................... 19
5.20 RFPMM, Voltage Doubler........................... 19
5.21 RFPMM, Voltage Supervision ...................... 19
5.22 SD14, Performance ................................. 20
5.23 SVSS Generator .................................... 20
5.24 Thermistor Bias Generator.......................... 21
5.25 Temperature Sensor ................................ 21
1.1 特性 ................................................... 1
1.2 应用 ................................................... 1
1.3 说明 ................................................... 1
1.4 功能方框图............................................ 2
修订历史记录............................................... 4
Device Comparison ..................................... 5
Terminal Configuration and Functions.............. 6
4.1 Pin Diagram .......................................... 6
4.2 Signal Descriptions ................................... 7
4.3 Pin Multiplexing....................................... 9
4.4 Connections for Unused Pins ........................ 9
Specifications ........................................... 10
5.1 Absolute Maximum Ratings ........................ 10
5.2 ESD Ratings ........................................ 10
5.3 Recommended Operating Conditions............... 10
2
3
4
5.26 RF13M, Power Supply and Recommended
Operating Conditions................................ 21
5.27 RF13M, ISO/IEC 15693 ASK Demodulator......... 21
5.28 RF13M, ISO/IEC 15693 Compliant Load Modulator 21
Detailed Description ................................... 22
6.1 CPU ................................................. 22
6.2 Instruction Set....................................... 22
6.3 Operating Modes.................................... 23
6.4 Interrupt Vector Addresses.......................... 24
6.5 Memory.............................................. 26
6.6 Peripherals .......................................... 27
6.7 Port Schematics..................................... 33
6.8 Device Descriptors (TLV) ........................... 41
Applications, Implementation, and Layout ....... 42
器件和文档支持 .......................................... 43
8.1 器件支持............................................. 43
8.2 文档支持............................................. 44
8.3 相关链接............................................. 44
8.4 Community Resources.............................. 45
8.5 商标.................................................. 45
8.6 静电放电警告 ........................................ 45
8.7 术语表 ............................................... 45
机械封装和可订购信息 .................................. 45
9.1 封装信息............................................. 45
5
6
5.4
5.5
5.6
Recommended Operating Conditions, Resonant
Circuit................................................ 11
Active Mode Supply Current Into VDDB Excluding
External Current .................................... 11
Low-Power Mode Supply Current (Into VDDB
)
Excluding External Current.......................... 11
5.7 Digital I/Os (P1, RST/NMI) .......................... 12
7
8
5.8
High-Frequency Oscillator (4 MHz), HFOSC ....... 12
Low-Frequency Oscillator (256 kHz), LFOSC ...... 12
5.9
5.10 Wake-Up From Low-Power Modes ................. 13
5.11 Timer_A ............................................. 13
5.12 eUSCI (SPI Master Mode) Recommended
Operating Conditions................................ 14
5.13 eUSCI (SPI Master Mode) .......................... 14
5.14 eUSCI (SPI Slave Mode) ........................... 16
5.15 eUSCI (I2C Mode)................................... 18
5.16 FRAM................................................ 18
9
版权 © 2012–2014, Texas Instruments Incorporated
内容
3
RF430FRL152H, RF430FRL153H, RF430FRL154H
ZHCSD28C –NOVEMBER 2012–REVISED DECEMBER 2014
www.ti.com.cn
2 修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from November 13, 2014 to December 8, 2014
Page
•
•
•
•
更正了《RF430FRL15xH 系列技术参考手册》标题的全部实例 ................................................................ 1
更正了《RF430FRL15xH 固件用户指南》标题的全部实例 ..................................................................... 1
Moved Tstg to Absolute Maximum Ratings table ................................................................................ 10
Changed title of Section 5.2 to ESD Ratings .................................................................................... 10
4
修订历史记录
Copyright © 2012–2014, Texas Instruments Incorporated
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ZHCSD28C –NOVEMBER 2012–REVISED DECEMBER 2014
3 Device Comparison
Table 3-1 summarizes the available family members.
Table 3-1. Device Comparison(1)
13.56-MHz
ISO/IEC 15693
Front End
FRAM
(KB)
SRAM
(KB)
Device
Timer
eUSCI_B
SD14
RF430FRL152H
RF430FRL153H
RF430FRL154H
2
2
2
4
4
4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
No
Yes
(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in 节 9, or see
the TI web site at www.ti.com.
Copyright © 2012–2014, Texas Instruments Incorporated
Device Comparison
5
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ZHCSD28C –NOVEMBER 2012–REVISED DECEMBER 2014
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4 Terminal Configuration and Functions
4.1 Pin Diagram
Figure 4-1 shows the pin assignments on the 24-pin RGE package.
24 23 22 21 20 19
ANT1
ANT2
VDDSW
VDDB
CP1
1
2
3
4
5
6
18
17
16
15
14
13
ADC2/TEMP2
ADC1/TEMP1
TST1
SVSS
TST2
CP2
ADC0
7
8
9 10 11 12
VSS
Exposed die
attached pad
Figure 4-1. 24-Pin RGE Package (Top View)
6
Terminal Configuration and Functions
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ZHCSD28C –NOVEMBER 2012–REVISED DECEMBER 2014
4.2 Signal Descriptions
Table 4-1 describes the signals.
Table 4-1. Signal Descriptions
TERMINAL
I/O(1)
DESCRIPTION
NAME
NO.
1
ANT1
ANT2
VDDSW
VDDB
CP1
I
I
Antenna input 1
2
Antenna input 2
3
Switched supply voltage
Battery supply voltage
Charge pump flying cap terminal 1
Charge pump flying cap terminal 2
Voltage doubler output
4
5
CP2
6
VDD2X
7
P1.3
General-purpose digital I/O
SPI slave transmit enable
Timer_A TA0 OUT2 output
SPI_STE
TA0.2
8
I/O
ACLK
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
Timer_A TA0 clock signal TA0CLK input
TA0CLK
P1.2
General-purpose digital I/O
SPI clock
SPI_CLK
MCLK
TA0.0
9
I/O
MCLK output
Timer_A TA0 OUT0 output
Reset input active low
RST/NMI
10
I
Non-maskable interrupt input
P1.1
General-purpose digital I/O
SPI slave out master in
SPI_SOMI
SCL
I2C clock
11
I/O
ACLK
TA0.2
CCI0.0
ACLK output (divided by 1, 2, 4, or 8 )
Timer_A TA0 OUT2 output
Timer_A TA0 CCR0 capture: CCI0B input, compare
P1.0
General-purpose digital I/O
SPI slave in master out
I2C data
SPI_SIMO
SDA
12
I/O
SMCLK
TA0.1
SMCLK output
Timer0_A3 OUT1 output
CCI0.0
ADC0
TST2
SVSS
TST1
Timer_A TA0 CCR0 capture: CCI0A input, compare
ADC input pin 0
13
14
15
16
17
18
I
Internal; connect to GND
Sensor reference potential
Internal; connect to GND
ADC1 / TEMP1
ADC2 / TEMP2
ADC input pin 1 / Resistive bias pin 1
ADC input pin 2 / Resistive bias pin 2
(1) I = input, O = output
Copyright © 2012–2014, Texas Instruments Incorporated
Terminal Configuration and Functions
7
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
I/O(1)
DESCRIPTION
NO.
TMS
JTAG test mode select
P1.7
General-purpose digital I/O
Timer_A TA0 OUT1 output
Timer_A TA0 OUT0 output
19
I/O
TA0.1
TA0.0
CCI0.2
Timer_A TA0 CCR2 capture: CCI2B input, compare
TDO
JTAG test data output
P1.6
General-purpose digital I/O
20
21
I/O
I/O
TA0.0
TA0.2
CCI0.2
Timer_A TA0 OUT0 output
Timer_A TA0 OUT2 output
Timer_A TA0 CCR2 capture: CCI2A input, compare
TDI
JTAG test data input
P1.5
General-purpose digital I/O
Timer_A TA0 OUT2 output
MCLK output
TA0.2
MCLK
CCI0.1
Timer_A TA0 CCR1 capture: CCI1B input, compare
TCK
JTAG test clock
P1.4
General-purpose digital I/O
Timer_A TA0 OUT1 output
SMCLK output
TA0.1
SMCLK
CCI0.1
22
I/O
O
Timer_A TA0 CCR1 capture: CCI1A input, compare
CLKIN
VDDH
VDDD
VSS
External clock input pin
23
24
Rectified voltage from RF-AFE
Digital supply voltage
Ground reference, bonded to exposed pad(2)
Pad
(2) VSS combines both digital ground (DVSS) and analog ground (AVSS
)
8
Terminal Configuration and Functions
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ZHCSD28C –NOVEMBER 2012–REVISED DECEMBER 2014
4.3 Pin Multiplexing
The GPIO port pins are multiplexed with other functions including analog peripherals and serial
communication modules. The pin functions are selected by a combination of register values and device
modes. For schematics of the port pins and details of the multiplexing for each, refer to 节 6.7.
4.4 Connections for Unused Pins
The correct termination of all unused pins is listed in Table 4-2.
Table 4-2. Connection of Unused Pins
Pin
TDI/TMS/TCK
RST/NMI
Potential
Open
Comment
When used for JTAG function
10-nF capacitor to GND/VSS
VCC or VSS
Open
Px.0 to Px.7
TDO
Set to port function, output direction
Open
Convention: leave TDO terminal as JTAG function
Copyright © 2012–2014, Texas Instruments Incorporated
Terminal Configuration and Functions
9
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5 Specifications
5.1 Absolute Maximum Ratings(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MIN
MAX
1.65
3.6
UNIT
V
Voltage applied at VDDB referenced to VSS (VAMR
Voltage applied at VANT referenced to VSS (VAMR
)
-0.3
-0.3
)
V
Voltage applied to any pin (references to VSS
)
-0.3 VDDB + 0.3
V
Diode current at any device pin(2)
±2
mA
Current derating factor when I/O ports are switched in parallel electrically and logically(3)
0.9
(4) (5) (6)
Storage temperature range, Tstg
-40
125
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are referenced to VSS
.
(3) The diode current increases to ±4.5 mA when two pins are connected, it increases to ±6.75 mA when three pins are connected, and so
on.
(4) Soldering during board manufacturing must follow the current JEDEC J-STD-020 specification with peak reflow temperatures not higher
than classified on the device label on the shipping boxes or reels. If hand soldering is required for application prototyping, peak
temperature must not exceed 250°C for a total of 5 minutes for any single device.
(5) Data retention on FRAM memory cannot be ensured when exceeding the specified maximum storage temperature, Tstg
.
(6) Programming of devices with user application code should only be performed after reflow or hand soldering. Factory programmed
information, such as calibration values, are designed to withstand the temperatures reached in the current JEDEC J-STD-020
specification.
5.2 ESD Ratings
VALUE
UNIT
Electrostatic discharge (ESD)
performance
VESD
Human body model (HBM), per ANSI/ESDA/JEDEC JS001(1)(2)
±2000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) Low leakage pin: ADC0 has reduced ESD tolerance of ±500 V HBM.
5.3 Recommended Operating Conditions
Typical data are based on VDDB = 1.5 V, TA = 25°C (unless otherwise noted)
MIN NOM
1.45
MAX UNIT
VDDB
VSS
Supply voltage during program execution
Supply voltage (GND reference)
Operating free-air temperature
1.65
V
V
0
TA
0
70
°C
nF
µF
(1)
CVDDB
CVDDSW
Capacitor on VDDB
100
2.2
(1)
Capacitor on VDDSW
Charge pump capacitor between CP1 and CP2.
Recommended ratio between CFLY and CVDD2X is ≥ 1:10.
CFLY
10
nF
nF
(1)
Capacitor on VDD2x
.
CVDD2X
100
Recommended ratio between CFLY and CVDD2X is ≥ 1:10.(1)
(1)
CVDDD
CSVSS
fSYSTEM
fCLKIN
Capacitor on VDDD
1
1
µF
µF
(1)
Capacitor between SVSS and VSS
System frequency(2) (3)
2
MHz
kHz
External clock input frequency
32
(1) Low equivalent series resistance (ESR) capacitor
(2) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
(3) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
10
Specifications
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ZHCSD28C –NOVEMBER 2012–REVISED DECEMBER 2014
5.4 Recommended Operating Conditions, Resonant Circuit
MIN
NOM
MAX UNIT
fc
Carrier frequency
13.56
MHz
VANT_peak
Z
Antenna input voltage
Impedance of LC circuit
Coil inductance
3.6
V
6.5
15.5
kΩ
µH
pF
LRES
CRES
QT
2.66
(1)
Resonance capacitance
Tank quality factor
51.8 – CIN
30
(1) See the RF13M parameter section.
5.5 Active Mode Supply Current Into VDDB Excluding External Current
over recommended operating free-air temperature (unless otherwise noted)(1)
Frequency (fMCLK = fSMCLK
)
EXECUTION
MEMORY
PARAMETER
VDDB
1 MHz
2 MHz
UNIT
TYP
330
MAX
420
TYP
480
MAX
(2)
IAM, FRAM
FRAM
RAM
1.5 V
1.5 V
1.5 V
580
µA
µA
µA
(2)
IAM, RAM
220
220
300
300
250
230
320
300
(2)
IAM, ROM
ROM
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) fACLK = 256 kHz, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0
5.6 Low-Power Mode Supply Current (Into VDDB) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
0ºC
TYP
20ºC
TYP
45ºC
TYP
70ºC
TYP
PARAMETER
VDDB
UNIT
MAX
MAX
MAX
MAX
fMCLK = off, fSMCLK
=
1 MHz, fACLK = 32 kHz,
CPUOFF = 1, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
(2)
(3)
(4)
ILPM0
ILPM3
ILPM4
1.5 V
170
12
230
190
13
210
16
260
25
340
µA
µA
µA
fMCLK = fSMCLK = off,
fACLK = 16 kHz,
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 0
1.5 V
1.5 V
20
16
65
60
fMCLK = fSMCLK = fACLK
0 Hz
=
11
12
15
24
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 1
(1) Including current for WDT clocked by ACLK.
(2) CSS: SELM=SELS=HF_CLK, SELA=LF_CLK, DIVM=/2 (2MHz), DIVS=/4 (1MHz), DIVA=/8 (32kHz)
SD14: reset values
RFPMM: battery switch on (EN_BATSWITCH=1)
(3) CSS: SELM=HF_CLK, SELS=SELA=LF_CLK, DIVM=/2 (2MHz), DIVS=/32 (8kHz), DIVA=/16 (16kHz)
SD14: reset values
RFPMM: EN_BATSWITCH=1(battery switch enabled)
(4) CSS: SELM=HF_CLK, SELS=SELA=LF_CLK, DIVM=/2 (2MHz), DIVS=/32 (8kHz), DIVA=/16 (16kHz)
SD14: reset values
RFPMM: EN_BATSWITCH=1(battery switch enabled)
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Specifications
11
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ZHCSD28C –NOVEMBER 2012–REVISED DECEMBER 2014
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5.7 Digital I/Os (P1, RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDDB = 1.5 V, IOH = -400 µA(1) for port P1
VDDB = 1.5 V, IOL = 400 µA(2) for port P1
VDDB = 1.5 V
MIN
TYP
MAX UNIT
VDDB
– 0.15
VOH
VOL
VIH
High-level output voltage
Low-level output voltage
High-level input voltage
V
0.15
V
V
0.7 ×
VDDB
0.3 ×
VDDB
VIL
Low-level input voltage
VDDB = 1.5 V
V
IOH
IOL
ILKG
tINT
High-level output current
Low-level output current
VDDB = 1.45 V to 1.65 V for port P1
VDDB = 1.45 V to 1.65 V for port P1
VDDB = 1.45 V to 1.65 V
-400
-100
µA
µA
nA
ns
400
100
High-impedance leakage current
External interrupt timing(3)
P1.x, VDDB = 1.45 V to 1.65 V
200
35
35
47
10
VDDB=1.5 V, For pullup: VIN = VSS
,
RPULL
RRST
REXT
CEXT
Pullup or pulldown resistor
30
30
40
40
kΩ
kΩ
kΩ
nF
For pulldown: VIN = VDDB for port P1
Pullup on RST/NMI
External pullup resistor on RST
terminal (optional)
External capacitor on RST terminal
(1) The maximum total current IOH, for all outputs combined should not exceed 500 µA to hold the maximum voltage drop specified, limited
by low leakage switches.
(2) The maximum total current IOL, for all outputs combined should not exceed 500 µA to hold the maximum voltage drop specified.
(3) An external signal sets the interrupt flag every time the minimum interrupt pulse duration tINT is met.
5.8 High-Frequency Oscillator (4 MHz), HFOSC
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fHFOSC
TEST CONDITIONS
MIN
3.04
45%
TYP
3.8
50%
1
MAX UNIT
4.56 MHz
55%
±20%
Duty cycle
tSTART
µs
5.9 Low-Frequency Oscillator (256 kHz), LFOSC
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fLFO
TEST CONDITIONS
MIN
243
TYP
256
MAX UNIT
269 kHz
55%
trimmed ±5%
Duty cycle
tSTART
45%
50%
11
µs
12
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5.10 Wake-Up From Low-Power Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDDB
MIN
TYP
MAX UNIT
Wake-up time from LPM0 to active
mode(1)
tWAKE-UP LPM0
tWAKE-UP LPM34
tWAKE-UP RESET
1.5 V
3.2
6
260
310
µs
µs
µs
Wake-up time from LPM3 or LPM4 to
active mode(1)
1.5 V
1.5 V
160
210
Wake-up time from RST to active
mode.(2)
VDDB stable
(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is fetched. This time includes the activation of the FRAM during wake-up. fMCLK = 2 MHz.
(2) The wake-up time is measured from the rising edge of the RST signal until the first instruction of the user program is fetched. This time
includes the activation of the FRAM during wake-up. fMCLK = 2 MHz.
5.11 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDDB
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
fTA
Timer_A input clock frequency
External: TACLK
Duty cycle = 50% ± 10%
1.5 V
4
MHz
ns
All capture inputs, Minimum pulse
duration required for capture
tTA,cap
Timer_A capture timing
1.5 V
20
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5.12 eUSCI (SPI Master Mode) Recommended Operating Conditions
PARAMETER
CONDITIONS
VDDB
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
Duty cycle = 50% ± 10%
feUSCI
eUSCI input clock frequency
1.5 V
fSYSTEM MHz
5.13 eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VDDB
MIN
TYP
MAX
UNIT
UCSTEM = 0,
UCMODEx = 01 or 10
1.5 V
1
UCxCLK
cycles
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
STE lead time, STE active to clock
UCSTEM = 1,
UCMODEx = 01 or 10
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1
1
1
UCSTEM = 0,
UCMODEx = 01 or 10
STE lag time, Last clock to STE
inactive
UCxCLK
cycles
UCSTEM = 1,
UCMODEx = 01 or 10
UCSTEM = 0,
UCMODEx = 01 or 10
55
35
40
30
STE access time, STE active to SIMO
data out
ns
ns
UCSTEM = 1,
UCMODEx = 01 or 10
UCSTEM = 0,
UCMODEx = 01 or 10
STE disable time, STE inactive to
SIMO high impedance
UCSTEM = 1,
UCMODEx = 01 or 10
tSU,MI
tHD,MI
SOMI input data setup time
SOMI input data hold time
1.5 V
1.5 V
35
0
ns
ns
UCLK edge to SIMO valid,
CL = 20 pF
tVALID,MO
tHD,MO
SIMO output data valid time(2)
SIMO output data hold time(3)
1.5 V
1.5 V
30
ns
ns
CL = 20 pF
0
(1) fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-1 and Figure 5-2.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-
1 and Figure 5-2.
14
Specifications
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UCMODEx = 01
UCMODEx = 10
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
SIMO
tSTE,ACC
tVALID,MO
tSTE,DIS
Figure 5-1. SPI Master Mode, CKPH = 0
UCMODEx = 01
STE
tSTE,LEAD
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
SIMO
tSTE,ACC
tVALID,MO
tSTE,DIS
Figure 5-2. SPI Master Mode, CKPH = 1
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5.14 eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VDDB
1.5 V
1.5 V
1.5 V
MIN
7
TYP
MAX UNIT
tSTE,LEAD
tSTE,LAG
tSTE,ACC
STE lead time, STE active to clock
STE lag time, Last clock to STE inactive
STE access time, STE active to SOMI data out
ns
ns
0
65
40
ns
STE disable time, STE inactive to SOMI high
impedance
tSTE,DIS
1.5 V
ns
tSU,SI
tHD,SI
SIMO input data setup time
SIMO input data hold time
1.5 V
1.5 V
2
5
ns
ns
UCLK edge to SOMI valid,
CL = 20 pF
tVALID,SO
tHD,SO
SOMI output data valid time(2)
SOMI output data hold time(3)
1.5 V
1.5 V
30
ns
ns
CL = 20 pF
4
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-3 and Figure 5-4.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-3
and Figure 5-4.
16
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UCMODEx = 01
UCMODEx = 10
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tSU,SIMO
tHD,SIMO
tLOW/HIGH
tLOW/HIGH
SIMO
tACC
tVALID,SOMI
tDIS
SOMI
Figure 5-3. SPI Slave Mode, CKPH = 0
UCMODEx = 01
UCMODEx = 10
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tACC
tDIS
tVALID,SO
SOMI
Figure 5-4. SPI Slave Mode, CKPH = 1
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5.15 eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-5)
PARAMETER
TEST CONDITIONS
VDDB
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
External: UCLK
feUSCI
eUSCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ± 10%
fSCL
SCL clock frequency
1.5 V
1.5 V
0
4.0
0.6
4.7
0.6
0
400 kHz
µs
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
1.5 V
µs
tHD,DAT
tSU,DAT
Data hold time
Data setup time
1.5 V
1.5 V
ns
ns
250
4.0
0.6
50
fSCL = 100 kHz
fSCL > 100 kHz
UCGLITx = 0
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
UCCLTOx = 1
UCCLTOx = 2
UCCLTOx = 3
tSU,STO
Setup time for STOP
1.5 V
µs
600
300
150
75
ns
ns
25
Pulse duration of spikes suppressed by input
filter
tSP
1.5 V
12.5
6.25
ns
ns
27
30
33
ms
ms
ms
tTIMEOUT
Clock low time-out
1.5 V
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-5. I2C Mode Timing
5.16 FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
tWRITE
Word or byte write time
Read/write endurance
Data retention duration
125
ns
1015
10
cycles
years
tRetention
TJ = 25°C
5.17 JTAG
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TCK input frequency, 4-wire JTAG(1)
(1) fTCK may be restricted to meet the timing requirements of the module selected.
VDDB
MIN
TYP
MAX UNIT
MHz
fTCK
1.5 V
0
4
18
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5.18 RFPMM, Power Supply Switch
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Positive going switching threshold
VTH+ = VDDB-VDDR
VTH+
VTH-
35
60
mV
mV
mV
Negative going switching threshold
VTH- = VDDB-VDDR
-60
30
-35
70
Switching voltage hysteresis
VHYST = VTH+-VTH-
VHYST
110
IBASVBAT
VDROP
VDDB input leakage current
VDDB = 1.65 V, Battery switch open
20
50
nA
(1)
VDROP= VDDB - VDDSW
mV
(1) Battery switch closed. Current = 400 µA
5.19 RFPMM, Bandgap Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Output voltage
TEST CONDITIONS
VDDSW = 1.4 V to 1.65 V
MIN
TYP
MAX UNIT
908 mV
VREF
892
5.20 RFPMM, Voltage Doubler
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Output voltage
TEST CONDITIONS
MIN TYP
MAX UNIT
2 ×
VDD2X
VDDSW = 1.4 V, IDD2X = 1 µA, cont = 0
VDDSW
–
mV
74mV
2 ×
VDD2X
Output voltage
VDDSW = 1.4 V, IDD2X = 100 µA, cont = 1
VDDSW
–
mV
104mV
5.21 RFPMM, Voltage Supervision
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VDDBTH+
VDDSW
1.5 V
1.5 V
MIN
TYP
1.45
1.40
1.40
1.35
1.00
0.90
2.70
2.475
MAX UNIT
Positive threshold
Negative threshold
Positive threshold
Negative threshold
Positive threshold
Negative threshold
Positive threshold
Negative threshold
V
V
V
V
V
V
V
V
VDDBTH-
VDDSWTH+
VDDSWTH-
VDDDTH+
1.5 V
1.5 V
1.5 V
1.5 V
VDDDTH-
VDD2XTH+
VDD2XTH-
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5.22 SD14, Performance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN NOM
MAX UNIT
Internal LF oscillator as clock source for
SD14 module
fM
Modulator clock frequency
2
kHz
RES
OSR
B
Resolution
8
14
2048
1
Bit
Oversampling ratio
Bandwidth of input signal
Input voltage range
40
Hz
VI
VI = VADCx - VSVSS
0
-0.75
-2%
VREF
mV
% of
Voffset
Offset error
Complete signal chain
0.75
2%
FSR(1)
VGErr
Gain error(2)
complete signal chain
complete signal chain
(3)
∆EG/∆T
Gain error temperature coefficient.
100 ppm/K
% of
2
EUnadjusted
tStart
Total unadjusted error
Startup time
-2
FSR(1)
CLK
cycles
20
(1) FSR = Full Scale Range (SD14 pre-amplifier Gain PGA gain - SD14 gain =1) .
(2) The gain error EG specifies the deviation of the actual gain Gact from the nominal gain Gnom: EG = (Gact – Gnom)/Gnom. It covers process,
temperature and supply voltage variations.
(3) Not production tested.
5.23 SVSS Generator
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Output voltage
TEST CONDITIONS
ISVSS = -5uA .. 0uA
MIN
TYP
MAX UNIT
VSVSS
tSettling
80
125
165
mV
Settling time after switching SVSS on
(95% of final voltage)
Switch from VIRTGND = 1 to VIRTGND = 0
400
1000
ms
20
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5.24 Thermistor Bias Generator
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Output current
TEST CONDITIONS
VOUT = 0 to 0.7 V
MIN
TYP
MAX UNIT
3.0 µA
IOUT,TH
2.0
2.4
5.25 Temperature Sensor
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Temperature coefficient
TEST CONDITIONS
MIN
TYP
MAX UNIT
tc
35.7
LSB/K
5.26 RF13M, Power Supply and Recommended Operating Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Antenna rectified voltage
Input capacitance
TEST CONDITIONS
IDDH = 100 µA
2 V RMS
MIN
1.8
TYP
2
MAX UNIT
VDDH
CIN
3.6
V
31.5
35
38.5
pF
5.27 RF13M, ISO/IEC 15693 ASK Demodulator
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Input signal data rate 100% downlink modulation, 100% ASK, ISO/IEC 15693
Modulation depth 100%, test as defined in ISO10373
Modulation depth 10%, test as defined in ISO10373
Delta propagation delay of RXD_10 to VIN
MIN
6
TYP
MAX UNIT
26 kbps
100%
DR100
m100
90%
7%
0
m10
30%
|tPLH– tPHL
tPLH, tPHL
tpd100
|
2.35
7.07
7.07
µs
µs
µs
µs
Propagation delay of RXD_10 to VIN
0
Propagation delay of RXD_100
tD100
Minimum pulse duration of RxD_100
5
5.28 RF13M, ISO/IEC 15693 Compliant Load Modulator
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Uplink subcarrier modulation frequency
MIN
0.2
0.5
10
TYP
MAX UNIT
fPICC
1
MHz
V
VA_MOD
VSUB15
Modulated antenna voltage, VA_unmod = 2,3V
Uplink modulation subcarrier level, ISO/IEC 15693
mV
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6 Detailed Description
6.1 CPU
The MSP430 CPU has a 16-Bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
6.2 Instruction Set
The instruction set consists of the original 51 instructions with three formats and seven address modes.
Each instruction can operate on word and byte data.
22
Detailed Description
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6.3 Operating Modes
The device has one active mode and three software selectable low-power modes of operation. An
interrupt event can wake up the device from any of the three low-power modes, service the request, and
restore back to the low-power mode on return from the interrupt program.
注
The software-selected low-power mode might not be reached if at least one module still
requests a clock on MCLK, SMCLK, or ACLK. The CPU, however, remains off until an
interrupt occurs.
The following operating modes can be configured by software:
•
Active mode AM
–
–
CPU is enabled
All clocks are active.
•
Low-power mode 0 (LPM0)
–
–
–
–
–
CPU is disabled
MCLK is disabled
SMCLK is active
ACLK is active
HFOSC is off, if not selected for SMCLK or ACLK
•
•
Low-power mode 3 (LPM3)
–
–
–
–
–
CPU is disabled
MCLK is disabled
SMCLK is disabled
ACLK is active
HFOSC is off, if not selected for ACLK
Low-power mode 4 (LPM4)
–
–
–
–
–
CPU is disabled
MCLK is disabled
SMCLK is disabled
ACLK is disabled
HFOSC is off, LFOSC is on
LPM1 is identical to LPM0, and LPM2 is identical to LPM3, because the SCG0 bit has no influence on
HFOSC.
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Detailed Description
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6.4 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FFE0h.
Address Range 0FFDFh to 0FFD0h is reserved for bootcode signatures. The vector contains the 16-bit
address of the appropriate interrupt-handler instruction sequence.
表 6-1. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
System Reset
Power-Up
WDTIFG(1)
Reset
FFFEh
15, highest
External Reset
Watchdog
System NMI
SVMIFG, VMAIFG(1)
(Non)maskable
(Non)maskable
0FFFCh
0FFFAh
14
13
Vacant memory access
User NMI
NMIIFG(1)(2)
NMI
TimerA0_A3
TA0CCR0 CCIFG0(3)
Maskable
Maskable
0FFF8h
0FFF6h
12
11
TA0CCR1 CCIFG1
TA0CCR2 CCIFG2
TimerA0_A3
TA0CTL TAIFGTA0IV(1)(3)
Watchdog,
Interval Timer Mode
WDTIFG
Maskable
Maskable
0FFF4h
0FFF2h
10
9
RF13MRXIFG, RF13MTXIFG, RF13MRXWMIFG,
RF13MTXWMIFG, RF13MSLIFG,
RF13MOUFLIFG, RF13MRXEIFG,
RF13MIVx(1)(3)
RF13M Module
(SPI mode)
UCB0RXIFG, UCB0TXIFG
(I2C mode)
UCB0ALIFG, UCB0NACKIFG, UCB0STTIFG,
UCB0STPIFG, UCB0RXIFG3, UCB0TXIFG3,
UCB0RXIFG2, UCB0TXIFG2, UCB0RXIFG1,
UCB0TXIFG1, UCB0RXIFG0, UCB0TXIFG0,
UCB0CNTIFG, UCB0CLTOIFG, UCB0BIT9IFG
eUSCIB
Maskable
0FFF0h
8
(SD14IV)(1)(3)
Sigma Delta ADC
I/O Port P1
SD14OVIFG, SD14IFG(1)(3)
Maskable
Maskable
0FFEEh
0FFECh
7
6
P1IFG.0 to P1IFG.7
(P1IV)(1)(3)
RFPMMIFGV2X, RFPMMIFGVH, RFPMMIFGVR,
RFPMMIFGVB, RFPMMIFGVF, RFPMMIV
RFPMM
Maskable
0FFEAh
5
0FFE8h
⋮
4
⋮
Reserved
Reserved(4)
0FFDCh
0
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(3) Interrupt flags are located in the module.
(4) Reserved interrupt vectors at these addresses are not used in this device and can be used for regular program code if necessary. To
maintain compatibility with other devices, it is recommended to reserve these locations.
24
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表 6-1. Interrupt Sources, Flags, and Vectors (continued)
SYSTEM
INTERRUPT
WORD
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
ADDRESS
0FFDAh
0FFD8h
0FFD6h
0FFD4h
0FFD2h
0FFD0h
CRC Value
CRC Length
Loader Signature 1
Loader Signature 0
JTAG Signature 1
JTAG Signature 0
Signatures
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6.5 Memory
表 6-2 shows the memory organization of the devices.
表 6-2. Memory Map RF430FRL152H, RF430FRL153H, RF430FRL154H
TYPE
RF430FRL152H
RF430FRL153H
RF430FRL154H
Normal Mode
RF430FRL152H
RF430FRL153H
RF430FRL154H
ROM Development Mode
Memory (FRAM)
Main: interrupt vector
Total Size
FRAM
2048 B = 2 KB
0FFFFh-0FFE0h
Main: Code Memory
Bank A(1)(2)
Bank B(1)
Bank C(1)
Bank D
512 B
0FFFFh-0FE00h
512 B
0FDFFh-0FC00h
512 B
0FBFFh-0FA00h
448 B
0F9FFh-0F840h
Boot Data (TLV)
Application ROM
Size
FRAM
64 B
01A3Fh-01A00h
64 B
01A3Fh-01A00h
Size
ROM
7168 B = 7 KB
05FFFh-04400h
3584 B = 3.5 KB
051FFh-04400h
ROM Development Memory Size
SRAM
-
-
3584 B = 3.5 KB
02BFFh-01E00h
SRAM Memory
Size
SRAM
4096 B = 4 KB
02BFFh-01C00h
512 B = 0.5 KB
01DFFh-01C00h
Peripherals
Size
4096 B = 4 KB
00FFFh-00000h
4096 B = 4 KB
00FFFh-00000h
(1) Write protectable. See also 表 6-3
(2) Address range includes interrupt vector.
6.5.1 FRAM
The FRAM can be programmed through the JTAG port or in-system by the CPU, data are received
through RF, SPI or I2C Sensor Interface.
Features of the FRAM include:
•
•
•
Low-power ultra-fast-write non-volatile memory
Byte and word access capability
Automated wait state generation
The following address ranges can be write protected by setting the corresponding bit in the SYSCNF
register, see the RF430FRL15xH Family Technical Reference Manual (SLAU506).
表 6-3. Write Protectable FRAM Address Ranges
BIT
Address Range
512 B
0FFFFh-0FE00h
FRAMLCK2
512 B
0FDFFh-0FC00h
FRAMLCK1
FRAMLCK0
512 B
0FBFFh-0FA00h
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6.5.2 SRAM
The SRAM memory is made up of 8 sectors. Each sector can be completely powered down to save
leakage; however, all data is lost. Features of the SRAM memory include:
•
•
•
SRAM memory has 8 sectors of 512 B each.
Each sector 0 to 8 can be complete disabled; however, data retention is lost.
Each sector 0 to 8 automatically enters low-power retention mode when possible.
6.5.3 Application ROM
The Application ROM consists of four parts. The RF Library provides ISO/IEC 15693 functions necessary
for operating the 13.65 MHz front end. The Function library holds the device and memory function used by
the boot code and RF library. These functions are user accessible. The ROM contains the predefined
application FW. The boot code checks the password and releases control to the application or enables
JTAG on password match, enters LPM4 and waits for debug session, see the RF430FRL15xH Firmware
User's Guide (SLAU603).
6.6 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. All peripherals can be
managed using all instructions. For complete module descriptions, see the RF430FRL15xH Family
Technical Reference Manual (SLAU506).
6.6.1 Digital I/O, (P1.x)
There is one I/O port implemented, P1, with eight I/O lines RF430FRL15xH.
•
•
•
•
•
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Programmable pullup or pulldown resistor on all ports.
Edge-selectable interrupt input capability for all ports on P1.
Read and write access to port-control registers is supported by all instructions.
6.6.2 Versatile I/O Port P1
The versatile I/O ports P1 feature device dependent reset values. The reset values for the
RF430FRL15xH devices are shown in 表 6-4.
表 6-4. Versatile Port Reset Values
PORT
NUMBER
PxOUT
PxDIR
PxREN
PxSEL0
PxSEL1
RESET
PORTS ON
COMMENT
P1.0, input
P1.0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
yes
yes
yes
yes
yes
yes
yes
yes
P1.1
P1.1, input
P1.2
P1.2, input
P1.3
P1.3, input
P1.4
JTAG TCK, P1.4, input
JTAG TDI, P1.5, input
JTAG TDO, P1.6, output
JTAG TMS, P1.7, input
P1.5
P1.6
P1.7
6.6.3 Oscillator and System Clock
The clock system in the RF430FRL15xH devices is supported by the Compact Clock System (CCS)
module that includes support for an internal trimmable 256-kHz current-controlled low-frequency oscillator
(LFOSC) and an internal 4-MHz current-controlled high-frequency oscillator (HFOSC).
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The CCS module is designed to meet the requirements of both low system cost and low power
consumption. The CCS provides a fast turn-on of the oscillators in less than 1 ms. The CCS module
provides the following clock signals:
•
•
Auxiliary clock (ACLK), sourced from the 256-kHz internal LFOSC.
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
•
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources made available to ACLK.
6.6.4 Compact System Module (C-SYS_A)
The Compact SYS module handles many of the system functions within the device. These include power-
on reset and power-up clear handling, NMI source selection and management, reset interrupt vector
generators, as well as, configuration management. It also includes a data exchange mechanism through
JTAG called a JTAG mailbox that can be used in the application.
表 6-5. System Module Interrupt Vector Registers
INTERRUPT VECTOR
INTERRUPT VECTOR
WORD ADDRESS
OFFSET
PRIORITY
REGISTER
SYSRSTIV, System Reset
No interrupt pending
Brownout (BOR)
SVMBOR (BOR)
RST/NMI (BOR)
DoBOR (BOR)
Security violation (BOR)
DoPOR (POR)
WDT time-out (PUC)
WDT key violation (PUC)
CCS key violation
PMM key violation
Peripheral area fetch (PUC)
Reserved
019Eh
00h
02h
Highest
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h-3Eh
00h
Lowest
Highest
SYSSNIV, System NMI
No interrupt pending
SVMIFG
019Ch
02h
VMAIFG
04h
JMBINIFG
06h
JMBOUTIFG
08h
Reserved
0Ah-3Eh
00h
Lowest
Highest
SYSUNIV, User NMI
No interrupt pending
NMIFG
019Ah
0198h
02h
OFIFG
04h
BERR
06h
Reserved
08h-3Eh
00h
Lowest
Lowest
SYSBERRIV, Bus Error
No interrupt pending
Reserved
02h-3Eh
6.6.5 Watchdog Timer (WDT_A)
The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart
after a software problem occurs. If the selected time interval expires, a system reset is generated. If the
watchdog function is not needed in an application, the module can be configured as an interval timer and
can generate interrupts at selected time intervals.
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6.6.6 Reset, NMI, SVMOUT System
The reset system of the RF430FRL15xH devices features the function reset input, reset output, and NMI
input.
6.6.7 Timer_A (Timer0_A3)
Timer_A is a 16-bit timer/counter with three capture/compare registers. Timer_A can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
表 6-6. Timer0_A3 Signal Connections
INPUT PIN
NUMBER
DEVICE INPUT
SIGNAL
MODUL INPUT
SIGNAL
MODULE
OUTPUT SIGNAL
DEVICE OUTPUT
SIGNAL
OUTPUT PIN
NUMBER
MODULE BLOCK
8 – P1.3
TA0CLK
ACLK (internal)
SMCLK (internal)
TA0CLK
TA0.0
TACLK
ACLK
SMCLK
TACLK
CCI0A
CCI0B
GND
Timer
NA
NA
12 – P1.0
11 – P1.1
9 – P1.2
20 – P1.6
19 – P1.7
TA0.0
CCR0
CCR1
CCR2
TA0
TA1
TA2
TA0.0
TA0.1
TA0.2
VSS
VDDB
Vcc
22 – P1.4
21 – P1.5
TA0.1
CCI1A
CCI1B
GND
12 – P1.0
22 – P1.4
19 – P1.7
TA0.1
VSS
VDDB
Vcc
20 – P1.6
19 – P1.7
TA0.2
CCI2A
CCI2B
GND
11 – P1.1
8 – P1.3
TA0.2
VSS
21 – P1.5
20 – P1.6
VDDB
Vcc
6.6.8 Enhanced Universal Serial Communication Interface (eUSCI_B0)
The eUSCI_B0 module is used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3 pin or 4 pin) and I2C.
The eUSCI_B0 module provides support for SPI (3 pin or 4 pin) or I2C.
6.6.9 ISO/IEC 15693 Analog Front End (RF13M)
The ISO/IEC 15693 module supports contact-less communication over the analog front end according to
ISO/IEC 15693 with data rates up to 26.48 kbps for receive and 26.48 kbps for transmit. It includes
decode of receive data and encode of transmit data, both synchronous with the AFE carrier clock.
6.6.10 ISO/IEC 15693 Decoder/Encoder (RF13M)
The module interfaces directly to the analog front end to ensure correct timing for transmit and receive of
data derived from the 13.56-MHz carrier frequency.
6.6.11 CRC16 Module (CRC16)
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data
checking purposes. The CRC16 module is compliant with ISO/IEC 13239, it is 16 bits long, polynominal is:
x16 + x12 + x5 + 1, direction is backward, and preset is 0xFFFF. For more information see ISO/IEC 13239.
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6.6.12 14-Bit Sigma-Delta ADC (SD14)
A sigma-delta modulator is provided for high resolution analog-to-digital conversion of quasi-dc voltages:
•
•
•
First-order integrator, 1-bit comparator, 1-bit DAC
Sampling frequency of up to 2 kHz
Fully differential
6.6.13 Programmable Gain Amplifier (SD14)
The PGA features a very high-impedance input and a programmable gain combined with full offset
compensation, very low offset drift, and low noise.
6.6.14 Peripheral Register Map
表 6-7. Peripheral Register Map
BASE
ADDRESS
MODULE NAME
RF13M
REGISTER DESCRIPTION
REGISTER
OFFSET
RF13M RX/TX High/Low Watermark Configuration Register
RF13M RX/TX FIFO Fill Level register
RF13M CRC accumulator Register
RF13M Transmit Data FIFO Register
RF13M Receive Data FIFO Register
RF13M Interrupt Vector Register
RF13M Interrupt Register
RF13MWMCFG
RF13MFIFOFL
RF13MCRC
RF13MTXF
RF13MRXF
RF13MIV
0800h
0Eh
0Ch
0Ah
08h
06h
04h
02h
00h
0Ch
0Ah
08h
06h
04h
02h
00h
2Eh
2Ch
2Ah
20h
1Eh
1Ch
1Ah
18h
16h
14h
0Eh
0Ch
0Ah
08h
07h
06h
02h
00h
RF13MINT
RF13M Control Register
RF13MCTL
SD14IV
SD14
SD14 Interrupt Vector Register
SD14 Intermediate Conversion Result Register
SD14 Intermediate Conversion Result Register
SD14 Intermediate Conversion Result Register
SD14 Conversion Result
0700h
SD14MEM3
SD14MEM2
SD14MEM1
SD14MEM0
SD14CTL1
SD14 Control Register 1
SD14 Control Register 0
SD14CTL0
eUSCI_B0
Interrupt Vector Word Register
Interrupt Flags Register
UCB0IV
0640h
UCB0IFG
Interrupt Enable Register
UCB0IE
I2C Slave Address Register
Address Mask Register
UCB0I2CSA
UCB0ADDMASK
UCB0ADDRX
UCB0I2COA3
UCB0I2COA2
UCB0I2COA1
UCB0I2COA0
UCB0TXBUF
UCB0RXBUF
UCB0TBCNT
UCB0STATW
UCB0BR1
Received Address Register
I2C Own Address 3 Register
I2C Own Address 2 Register
I2C Own Address 1 Register
I2C Own Address 0 Register
Transmit Buffer Register
Receive Buffer Register
Byte Counter Threshold Register
Status Word Register
Bit Rate 1 Register
Bit Rate 0 Register
UCB0BR0
Control Word 1 Register
UCB0CTLW1
UCB0CTLW0
Control Word 0 Register
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表 6-7. Peripheral Register Map (continued)
BASE
ADDRESS
MODULE NAME
REGISTER DESCRIPTION
REGISTER
OFFSET
Timer0_A3
Timer0_A Interrupt Vector Register
TA0IV
TA0CCR2
TA0CCR1
TA0CCR0
TA0R
0340h
2Eh
16h
14h
12h
10h
06h
04h
02h
00h
1Ch
1Ah
18h
0Eh
0Ch
0Ah
06h
04h
02h
00h
1Eh
1Ch
1Ah
18h
14h
10h
0Eh
0Ch
0Ah
08h
06h
00h
10h
0Eh
0Ch
0Ah
08h
02h
00h
0Ch
06h
04h
02h
00h
06h
04h
00h
Capture/Compare Register 2
Capture/Compare Register 1
Capture/Compare Register 0
Timer0_A Counter Register
Capture/Compare Control 2 Register
Capture/Compare Control 1 Register
Capture/Compare Control 0 Register
Timer0_A Control Register
TA0CCTL2
TA0CCTL1
TA0CCTL0
TA0CTL
Port P1
Port P1 Interrupt Flag Register
Port P1 Interrupt Enable Register
Port P1 Interrupt Edge Select Register
Port P1 Interrupt Vector Word Register
Port P1 Selection 1 Register
Port P1 Selection 0 Register
Port P1 Pullup/Pulldown Enable Register
Port P1 Direction Register
P1IFG
0200h
P1IE
P1IES
P1IV
P1SEL1
P1SEL0
P1REN
P1DIR
Port P1 Outout Register
P1OUT
Port P1 Input Register
P1IN
CSYS_A
Reset Vector Generator Register
System NMI Vector Generator Register
User NMI Vector Generator Register
Bus Error Vector Generator Register
System Configuration Actuator 0 Register
System Configuration Register
JTAG Mailbox Output Register 1
JTAG Mailbox Output Register 0
JTAG Mailbox Input Register 1
JTAG Mailbox Input Register 0
JTAG Mailbox Control Register
System Control Register
SYSRSTIV
SYSSNIV
SYSUNIV
SYSBERRIV
SYSCA0
SYSCNF
SYSJMBO1
SYSJMBO0
SYSJMBI1
SYSJMBI0
SYSJMBC
SYSCTL
CCSCTL8
CCSCTL7
CCSCTL6
CCSCTL5
CCSCTL4
CCSCTL1
CCSCTL0
WDTCTL
CRCRESR
CRCINIRES
CRCDIRB
CRCDI
0180h
CCS
CCS Control 8 Register
0160h
CCS Control 7 Register
CCS Control 6Register
CCS Control 5 Register
CCS Control 4 Register
CCS Control 1 Register
CCS Control 0 Register
WDT_A, CRC
FRAM Control
Watchdog Timer Control Register
CRC Result Reverse Register
CRC Initialization and Result Register
CRC Data In Reverse Byte Register
CRC Data In Register
0150h
0140h
General Control 1 Register
GCCTL1
GCCTL0
FRCTL0
General Control 0 Register
FRAM Control 0 Register
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OFFSET
表 6-7. Peripheral Register Map (continued)
BASE
ADDRESS
MODULE NAME
REGISTER DESCRIPTION
REGISTER
RFPMM
RFPMM Interrupt Vector Register
RFPMMIV
RFPMMIFG
RFPMMIE
RFPMMCTL1
RFPMMCTL0
SFRRPCR
SFRIFG1
0120h
08h
06h
04h
02h
00h
04h
02h
00h
RFPMM Interrupt Flag Register
RFPMM Interrupt Enable Register
RFPMM Control Register 1
RFPMM Control Register 0
Special Functions
SFR Reset Pin Control Register
SFR Interrupt Flag Register
SFR Interrupt Enable Register
0100h
SFRIE1
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6.7 Port Schematics
6.7.1 Port P1.0 Input/Output
Pad Logic
P1REN.x
Vss
Vcc
0
1
P1DIR.x
00
01
10
11
eUSCI_B0
PortsOn
P1OUT.x
SPI_SIMO/SDA
SMCLK
00
01
10
11
TA0.1
P1.0/SPI_SIMO/SDA/SMCLK/TA0.1/CCI0.0
P1SEL0.x
P1SEL1.x
P1IN.x
EN1
EN2
#
Modul x IN
P1IES.x
D
Set
Q
Bus
Keeper
P1IFG.x
P1IE.x
P1IRQ.x
表 6-8. Port P1.0 Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1.0 (I/O)
RSELx/
ASELx
P1DIR.x
P1SEL1.x
P1SEL0.x
I:0; O:1
0
0
0
1
0
0
0
0
X
SPI_SIMO/SDA(2)
1
1
1
0
P1.0/SPI_SIMO/SDA/SMCLK/TA0.1/CCI0.0
(1) X = Don't care
0
SMCLK
1
0
TA0.1
1
1
Timer A0, CCI0A
≠0
≠0
(2) Module controls direction of port, depending on whether RF430 device is master or slave.
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6.7.2 Port P1.1 Input/Output
Pad Logic
P1REN.x
Vss
Vcc
0
1
P1DIR.x
00
01
10
11
eUSCI_B0
PortsOn
P1OUT.x
SPI_SOMI/SCL
ACLK
00
01
10
11
TA0.2
P1.1/SPI_SOMI/SCL/ACLK/TA0.2/CCI0.0
P1SEL0.x
P1SEL1.x
P1IN.x
EN1
EN2
#
Modul x IN
P1IES.x
D
Set
Q
Bus
Keeper
P1IFG.x
P1IE.x
P1IRQ.x
表 6-9. Port P1.1 Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
RSELx/ASE
Lx
P1SEL1.x
P1SEL0.x
P1.1 (I/O)
SPI_SOMI/SCL(2)
I:0; O:1
0
0
0
1
0
0
0
0
X
1
1
1
0
P1.1/SPI_SOMI/SCL/ACLK/TA0.2/CCI0.0
(1) X = Don't care
1
ACLK
1
0
TA0.2
1
1
Timer A1, CCI0B
≠0
≠0
(2) Module controls direction of port, depending on whether RF430 device is master or slave.
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RF430FRL152H, RF430FRL153H, RF430FRL154H
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ZHCSD28C –NOVEMBER 2012–REVISED DECEMBER 2014
6.7.3 Port P1.2 Input/Output
Pad Logic
P1REN.x
Vss
Vcc
0
1
P1DIR.x
00
01
10
11
eUSCI_B0
PortsOn
P1OUT.x
SPI_CLK
MCLK
00
01
10
11
TA0.0
P1.2/SPI_CLK/MCLK/TA0.0
P1SEL0.x
P1SEL1.x
P1IN.x
EN1
EN2
#
Modul x IN
P1IES.x
D
Set
Q
Bus
Keeper
P1IFG.x
P1IE.x
P1IRQ.x
表 6-10. Port P1 (P1.2) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
RSELx/ASEL
x
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.2 (I/O)
SPI_CLK(2)
I:0; O:1
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
P1.2/SPI_CLK/MCLK/TA0.0
(1) X = Don't care
2
MCLK
TA0.0
(2) Module controls direction of port, depending on whether RF430 device is master or slave.
版权 © 2012–2014, Texas Instruments Incorporated
Detailed Description
35
提交文档反馈意见
产品主页链接: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
ZHCSD28C –NOVEMBER 2012–REVISED DECEMBER 2014
www.ti.com.cn
6.7.4 Port P1.3 Input/Output
Pad Logic
P1REN.x
Vss
Vcc
0
1
P1DIR.x
00
01
10
11
eUSCI_B0
PortsOn
P1OUT.x
SPI_STE
TA0.2
00
01
10
11
P1.3/SPI_STE/TA0.2/ACLK/TA0CLK
P1SEL0.x
P1SEL1.x
P1IN.x
EN1
EN2
#
Modul x IN
P1IES.x
D
Set
Q
Bus
Keeper
P1IFG.x
P1IE.x
P1IRQ.x
表 6-11. Port P1 (P1.3) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1.3 (I/O)
RSELx/ASE
Lx
P1DIR.x
P1SEL1.x
P1SEL0.x
I:0; O:1
0
0
0
1
0
0
0
0
X
SPI_STE(2)
1
1
1
X
P1.3/SPI_STE/TA0.2/ACLK/TA0CLK
(1) X = Don't care
3
TA0.2
1
0
ACLK
1
1
TA0CLK
≠0
≠0
(2) Module controls direction of port, depending on whether RF430 device is master or slave.
36
Detailed Description
版权 © 2012–2014, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com.cn
ZHCSD28C –NOVEMBER 2012–REVISED DECEMBER 2014
6.7.5 Port P1.4 Input/Output
Pad Logic
Pad Logic
to clock system
P1REN.x
Vss
Vcc
0
1
P1DIR.x
PortsOn
00
01
10
11
P1OUT.x
TA0.1
00
01
10
11
SMCLK
RFU
P1.4/TA0.1/SMCLK/TCK/CCI0.1/CLKIN
P1SEL0.x
P1SEL1.x
P1IN.x
TCK to JTAG logic
Enable from JTAG logic
EN1
EN2
#
Module X IN
P1IES.x
D
Set
Q
Bus
Keeper
P1IFG.x
P1IE.x
P1IRQ.x
表 6-12. Port P1.4 Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
JTAG Mode
P1.4 (I/O)
I:0; O:1
0
0
0
1
0
0
0
0
0
1
0
Timer_A0.1
1
1
1
0
X
X
SMCLK
1
0
TCK/P1.4/TA0.1/SMCLK/CCI0.1
(1) X = Don't care
4
Reserved
1
1
Timer_A0.CCI1A
JTAG-TCK(2)(3)(4)
CLKIN from bypass
≠0
X
X
≠0
X
X
(2) JTAG signals TMS, TCK, and TDI read as 1 when not configured as explicit JTAG terminals.
(3) JTAG overrides digital output control when configured as explicit JTAG terminals.
(4) JTAG function with enabled pullup resistors is default after power up.
版权 © 2012–2014, Texas Instruments Incorporated
提交文档反馈意见
Detailed Description
37
产品主页链接: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
ZHCSD28C –NOVEMBER 2012–REVISED DECEMBER 2014
www.ti.com.cn
6.7.6 Port P1.5 Input/Output
Pad Logic
P1REN.x
Vss
Vcc
0
1
P1DIR.x
00
01
10
11
PortsOn
P1OUT.x
TA0.2
MCLK
RFU
00
01
10
11
P1.5/TA0.2/MCLK/TDI/CCI0.1
P1SEL0.x
P1SEL1.x
P1IN.x
TDI to JTAG logic
Enable from JTAG logic
EN1
EN2
#
Module X IN
P1IES.x
D
Set
Q
Bus
Keeper
P1IFG.x
P1IE.x
P1IRQ.x
表 6-13. Port P1.5 Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
JTAG Mode
P1.5 (I/O)
Timer_A0.2
MCLK
I:0; O:1
0
0
0
1
0
0
0
0
0
1
1
1
1
0
X
1
0
TDI/P1.5/TA0.2/MCLK/CCI0.1
(1) X = Don't care
5
1
1
Timer_A0 CCI1B
JTAG-TDI(2)(3)(4)
≠0
X
≠0
X
(2) JTAG signals TMS, TCK, and TDI read as 1 when not configured as explicit JTAG terminals.
(3) JTAG overrides digital output control when configured as explicit JTAG terminals.
(4) JTAG function with enabled pullup resistors is default after power up.
38
Detailed Description
版权 © 2012–2014, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com.cn
ZHCSD28C –NOVEMBER 2012–REVISED DECEMBER 2014
6.7.7 Port P1.6 Input/Output
Pad Logic
P1REN.x
Vss
Vcc
0
1
P1DIR.x
00
01
10
11
from JTAG logic
PortsOn
P1OUT.x
TA0.0
00
01
10
11
TA0.2
TDO from JTAG
TDO/P1.6/TA0.0/TA0.2/CCI0.2
P1SEL0.x
P1SEL1.x
P1IN.x
enable JTAG Mode
EN1
EN2
#
Module X IN
P1IES.x
D
Set
Q
Bus
Keeper
P1IFG.x
P1IE.x
P1IRQ.x
表 6-14. Port P1.6 Pin Functions
CONTROL BITS OR SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.6 (I/O)
I:0; O:1
0
0
0
1
Timer_A0.0
1
1
1
0
TDO/P1.6/TA0.0/TA0.2/CCI0.2
6
Timer_A0.2
JTAG-TDO(1)(2)
1
0
1
1
Timer_A0 CCI2A
≠0
≠0
(1) JTAG signals TMS, TCK, and TDI read as 1 when not configured as explicit JTAG terminals.
(2) JTAG overrides digital output control when configured as explicit JTAG terminals.
版权 © 2012–2014, Texas Instruments Incorporated
提交文档反馈意见
Detailed Description
39
产品主页链接: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
ZHCSD28C –NOVEMBER 2012–REVISED DECEMBER 2014
www.ti.com.cn
6.7.8 Port P1.7 Input/Output
Pad Logic
P1REN.x
Vss
Vcc
0
1
P1DIR.x
00
01
10
11
PortsOn
P1OUT.x
TA0.1
TA0.0
RFU
00
01
10
11
P1.7/TA0.1/TA0.0/TMS/CCI0.2
P1SEL0.x
P1SEL1.x
P1IN.x
TMS to JTAG logic
Enable from JTAG logic
EN1
EN2
#
Module X IN
P1IES.x
D
Set
Q
Bus
Keeper
P1IFG.x
P1IRQ.x
表 6-15. Port P1.7 Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
JTAG Mode
P1.7 (I/O)
I:0; O:1
0
0
0
1
0
0
0
0
0
1
Timer_A0.1
1
1
1
0
X
Timer_A0.0
1
0
TMS/P1.7/TA0.1/TA0.0/CCI0.2
(1) X = Don't care
7
Reserved
1
1
Timer_A0.CCI2B
JTAG-TMS(2)(3)(4)
≠0
X
≠0
X
(2) JTAG signals TMS, TCK, and TDI read as 1 when not configured as explicit JTAG terminals.
(3) JTAG overrides digital output control when configured as explicit JTAG terminals.
(4) JTAG function with enabled pullup resistors is default after power up.
40
Detailed Description
版权 © 2012–2014, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com.cn
ZHCSD28C –NOVEMBER 2012–REVISED DECEMBER 2014
6.8 Device Descriptors (TLV)
表 6-16 list the complete contents of the device descriptor tag-length-value (TLV) structure for each device
type.
表 6-16. RF430FRL15xH Boot Data and Device Descriptor Table
Size
bytes
Description
Address
FRL152H
FRL153H
FRL154H
Info Block
Die Record
Boot Data Length
CRC length
Boot Data CRC value
Device ID
Device ID
Lot #0
01A00h
01A01h
01A02h
01A04h
01A05h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Bh
01A0Ch
01A0Dh
01A0Eh
01A0Fh
01A10h
01A12h
01A14h
01A16h
01A18h
01A1Ah
01A1Ch
01A1Eh
1
03h
03h
03h
03h
03h
03h
1
2
per unit
E7h
per unit
FBh
per unit
FCh
1
1
81h
81h
81h
1
per unit
per unit
per unit
per unit
per unit
per unit
per unit
A2h / A3h
per unit
per unit
0FFFFh
0FFFFh
01A14h
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
A2h / A3h
per unit
per unit
0FFFFh
0FFFFh
01A14h
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
A2h / A3h
per unit
per unit
0FFFFh
0FFFFh
01A14h
per unit
per unit
per unit
per unit
per unit
Lot #1
1
UID0
1
UID1
1
UID2
1
UID3
1
UID4
1
UID5
1
Lot #2
1
Fab ID / Wafer Number
Reserved
Reserved
Calibration Pointer
Reserved
Reserved
Reserved
Reserved
Reserved
1
2
2
Calibration
2
2
2
2
2
2
01A3E -
01A20h
ECC
ECC of previous data
32
per unit
per unit
per unit
表 6-17. UID (Unique Identifier) Definition
Description
Lot ID 0
Lot ID 1
UID0
Address
Bit7
LotNr[7]
LotNr[15]
TI[7]
Bit6
LotNr[6]
LotNr[14]
TI[6]
Bit5
LotNr[5]
LotNr[13]
TI[5]
Bit4
LotNr[4]
LotNr[12]
TI[4]
Bit3
LotNr[3]
LotNr[11]
TI[3]
Bit2
Bit1
LotNr[1]
LotNr[9]
TI[1]
Bit0
0x1A06
0x1A07
0x1A08
0x1A09
0x1A0A
0x1A0B
0x1A0C
0x1A0D
0x1A0E
0x1A0F
LotNr[2]
LotNr[10]
TI[2]
LotNr[0]
LotNr[8]
TI[0]
UID1
TI[15]
TI[14]
TI[13]
TI[12]
TI[11]
TI[10]
TI[9]
TI[8]
UID2
TI[23]
TI[22]
TI[21]
TI[20]
TI[19]
TI[18]
TI[17]
TI[25]
TI[33]
1
TI[16]
UID3
TI[31]
TI[30]
TI[29]
TI[28]
TI[27]
TI[26]
TI[24]
UID4
TI[39]
TI[38]
TI[37]
TI[36]
TI[35]
TI[34]
TI[32]
UID5
1
0
1
0
0
0
TI[40]
Lot ID 2
FabID
LotNr[23]
Wafer[4]
LotNr[22]
Wafer[3]
LotNr[21]
Wafer[2]
LotNr[20]
Wafer[1]
LotNr[19]
Wafer[0]
LotNr[18]
FabNr[2]
LotNr[17]
FabNr[1]
LotNr[16]
FabNr[0]
版权 © 2012–2014, Texas Instruments Incorporated
Detailed Description
41
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产品主页链接: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
ZHCSD28C –NOVEMBER 2012–REVISED DECEMBER 2014
www.ti.com.cn
7 Applications, Implementation, and Layout
JTAG signals
C9
C8
24 23 22 21 20 19
L1
C1
ANT1
ANT2
VDDSW
VDDB
CP1
ADC2
1
2
3
4
5
6
18
17
16
15
14
13
R2
ADC1/TEMP1
TST1
C2
SVSS
C7
TST2
B1
C3
CP2
ADC0
C4
VDD2X
7
8
9
10 11 12
C5
VDD2X
Analog
Sensor 1
Analog
Sensor 2
SVSS
SVSS
C6
Two analog sensors connected through I2C, supplied by VDD2X (≈3 V)
图 7-1. Application Circuit
表 7-1 lists the bill of materials for this application.
表 7-1. Bill of Materials
Name
L1
Value
3 µH
Description
RF inductance (nominal)
C1
C2
C3
C4
C5
C6
C7
C8
C9
B1
8.2 pF
2.2 µF
100 nF
10 nF
100 nF
10 nF
1µF
RF tuning capacitor (nominal)
Decoupling cap at VDDSW
Decoupling cap at VDDB
Charge pump capacitor
Decoupling cap at VDD2X
Decoupling cap at RST
Bypass capacitor between SVSS and VSS
Decoupling cap at VDD
Decoupling cap at VDDH
Battery
100 nF
100 nF
1.5 V
R2
100 kΩ
Reference resistor
42
Applications, Implementation, and Layout
版权 © 2012–2014, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com.cn
ZHCSD28C –NOVEMBER 2012–REVISED DECEMBER 2014
8 器件和文档支持
8.1 器件支持
8.1.1 开发支持
TI 提供了大量的开发工具,其中包括评估处理器性能、生成代码、开发算法实现、以及完全集成和调试软件
及硬件模块的工具。 工具支持文档以电子文档形式提供,包含在 Code Composer Studio™ 集成开发环境
(IDE)中。
有关 NFC 应答器的开发工具和驱动程序的概述,请访问 NFC/RFID 工具和软件页面。
8.1.2 器件和开发工具命名规则
为了指明产品开发周期所处的阶段,TI 为所有 RF430 MCU 器件和支持工具的产品型号分配了前缀。 每个
商业系列成员都具有以下三个前缀中的一个:RF、P 或 X(例如,RF430FRL152H)。 德州仪器 (TI) 建议
为其支持的工具使用三个可用前缀指示符中的两个:RF 和 X。这些前缀代表了产品开发的发展阶段:即从
工程原型设计(X 表示器件和工具)直到完全合格的生产器件和工具(RF 表示器件和工具)。
器件开发进化流程:
X - 试验器件不一定代表最终器件的电气技术规格
P - 最终的芯片模型符合器件的电气技术规格,但是未经完整的质量和可靠性验证
RF - 完全合格的生产器件
支持工具开发发展流程:
X - 还未经德州仪器 (TI) 完整内部质量测试的开发支持产品。
RF – 完全合格的开发支持产品
X 和 P 器件和 X 开发支持工具在供货时附带如下免责条款:
“开发的产品用于内部评估用途。”
RF 器件和 RF 开发支持工具已进行完全特性描述,并且器件的质量和可靠性已经完全论证。 TI 的标准保修
证书适用。
预测显示原型器件(X 和 P)的故障率大于标准生产器件。 由于它们的预计的最终使用故障率仍未定义,德
州仪器 (TI) 建议不要将这些器件用于任何生产系统。 只有合格的产品器件将被使用。
TI 器件的命名规则也包括一个带有器件系列名称的后缀。 这个后缀包括封装类型(例如,RGE)和温度范
围(例如,T)。图 8-1 提供了解读任一系列产品成员完整器件名称的图例。
版权 © 2012–2014, Texas Instruments Incorporated
器件和文档支持
43
提交文档反馈意见
产品主页链接: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
ZHCSD28C –NOVEMBER 2012–REVISED DECEMBER 2014
www.ti.com.cn
RF 430 FRL
H A I
R XX
RGE
152
Processor Family
430 MCU Platform
Device Type
Optional: Additional Features
Optional: Tape and Reel
Packaging
Optional: Temperature Range
Optional: Revision
Device Designator
Wireless Technology
Processor Family
RF = Embedded RF Radio
X = Experimental Silicon
P = Prototype Device
430 MCU Platform
Device Type
TI’s Low Power Microcontroller Platform
FR = FRAM Memory
L = Low-Power Series
Device Designator
Various Levels of Integration Within a Series
Wireless Technology
Optional: Revision
HF = High Frequency
A = Device Revision
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = -40°C to 85°C
T = -40°C to 105°C
Packaging
www.ti.com/packaging
Optional: Tape and Reel
T = Small Reel (7 inch)
R = Large Reel (11 inch)
No Markings = Tube or Tray
Optional: Additional Features -EP = Enhanced Product (-40°C to 105°C)
-HT = Extreme Temperature Parts (-55°C to 150°C)
图 8-1. 器件命名规则
8.2 文档支持
下列文档描述了 RF430FRL15xH 器件。
SLAU506
SLAU603
RF430FRL15xH 系列技术参考手册。 详细介绍了这款器件系列提供的所有模块和外设。
RF430FRL15xH 固件用户指南。 详细介绍了为这些器件提供的固件。
8.3 相关链接
表 8-1 列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件,并且可以快速访问样片或
购买链接。
表 8-1. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
请单击此处
RF430FRL152H
RF430FRL153H
RF430FRL154H
44
器件和文档支持
版权 © 2012–2014, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: RF430FRL152H RF430FRL153H RF430FRL154H
RF430FRL152H, RF430FRL153H, RF430FRL154H
www.ti.com.cn
ZHCSD28C –NOVEMBER 2012–REVISED DECEMBER 2014
8.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
8.5 商标
MSP430, Code Composer Studio, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
8.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
9 机械封装和可订购信息
9.1 封装信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知
且不对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
版权 © 2012–2014, Texas Instruments Incorporated
机械封装和可订购信息
45
提交文档反馈意见
产品主页链接: RF430FRL152H RF430FRL153H RF430FRL154H
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
RF430FRL152HCRGER
RF430FRL153HCRGER
RF430FRL154HCRGER
ACTIVE
VQFN
VQFN
VQFN
RGE
24
24
24
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
0 to 70
0 to 70
0 to 70
RF430
FRL152H
ACTIVE
ACTIVE
RGE
NIPDAU
NIPDAU
RF430
FRL153H
RGE
RF430
FRL154H
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Aug-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
RF430FRL152HCRGER VQFN
RF430FRL153HCRGER VQFN
RF430FRL154HCRGER VQFN
RGE
RGE
RGE
24
24
24
3000
3000
3000
330.0
330.0
330.0
12.4
12.4
12.4
4.3
4.3
4.3
4.3
4.3
4.3
1.5
1.5
1.5
8.0
8.0
8.0
12.0
12.0
12.0
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Aug-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
RF430FRL152HCRGER
RF430FRL153HCRGER
RF430FRL154HCRGER
VQFN
VQFN
VQFN
RGE
RGE
RGE
24
24
24
3000
3000
3000
338.1
338.1
338.1
338.1
338.1
338.1
20.6
20.6
20.6
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
VQFN - 1 mm max height
RGE0024C
PLASTIC QUAD FLATPACK- NO LEAD
4.1
3.9
A
B
4.1
3.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 2.5
2.1±0.1
(0.2) TYP
12
7
20X 0.5
6
13
SYMM
25
2X
2.5
1
18
0.30
PIN 1 ID
(OPTIONAL)
24X
0.18
0.1
24
19
0.50
C A B
C
SYMM
0.05
24X
0.30
4224376 / C 07/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGE0024C
PLASTIC QUAD FLATPACK- NO LEAD
(3.8)
2.1)
(
24
19
24X (0.6)
24X (0.24)
1
18
20X (0.5)
25
SYMM
(3.8)
2X
(0.8)
(Ø0.2) VIA
TYP
6
13
(R0.05)
7
12
2X(0.8)
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MIN
0.07 MAX
ALL AROUND
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224376 / C 06/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGE0024C
PLASTIC QUAD FLATPACK- NO LEAD
(3.8)
4X ( 0.94)
24
19
24X (0.6)
24X (0.24)
1
18
20X (0.5)
SYMM
(3.8)
(0.57)
TYP
6
13
25
(R0.05) TYP
METAL
TYP
7
12
(0.57)
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
80% PRINTED COVERAGE BY AREA
SCALE: 20X
4224376 / C 06/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
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