SMJ320C40TBBS60/10 [TI]
32-BIT, 60MHz, OTHER DSP, UUC325, DIE-325;
| 型号： | SMJ320C40TBBS60/10 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 32-BIT, 60MHz, OTHER DSP, UUC325, DIE-325 时钟 外围集成电路 |
| 文件： | 总65页 (文件大小：1335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
D
D
D
D
SMJ: QML Processing to MIL--PRF--38535
SM: Standard Processing
TMP: Commercial Level Processing TAB
Operating Temperature Ranges:
-- Military (M) --55°C to 125°C
-- Special (S) --55°C to 100°C
-- Commercial (C) --25°C to 85°C
-- Commercial (L) 0°C to 70°C
D
D
IEEE Standard 1149.1† Test-Access Port
(JTAG)
Two Identical External Data and Address
Buses Supporting Shared Memory Systems
and High Data-Rate, Single-Cycle
Transfers:
-- High Port-Data Rate of 100 MBytes/s
(Each Bus)
-- 16G-Byte Continuous
Program/Data/Peripheral Address Space
-- Memory-Access Request for Fast,
Intelligent Bus Arbitration
D
Highest Performance Floating-Point Digital
Signal Processor (DSP)
-- C40-60:
-- Separate Address-, Data-, and
Control-Enable Pins
33-ns Instruction Cycle Time:
60 MFLOPS, 30 MIPS, 330 MOPS,
384 MBps
-- Four Sets of Memory-Control Signals
Support Different Speed Memories in
Hardware
-- C40-50:
40-ns Instruction Cycle Time:
50 MFLOPS, 25 MIPS, 275 MOPS,
320 MBps
D
Packaging:
-- 325-Pin Ceramic Grid Array (GF Suffix)
-- 352-Lead Ceramic Quad Flatpack
(HFH Suffix)
-- C40-40:
50-ns Instruction Cycle Time:
40 MFLOPS, 20 MIPS, 220 MOPS,
256 MBps
-- 324-Pad JEDEC-Standard TAB Frame
D
D
Fabricated Using Enhanced Performance
Implanted CMOS (EPIC™) Technology by
Texas Instruments (TI™)
Separate Internal Program, Data, and DMA
Coprocessor Buses for Support of Massive
Concurrent Input/Output (I/O) of Program
and Data Throughput, Maximizing
Sustained Central Processing Unit (CPU)
Performance
D
D
Six Communications Ports
6-Channel Direct Memory Access (DMA)
Coprocessor
Single-Cycle Conversion to and From
IEEE-745 Floating-Point Format
x
Single Cycle 1/x, 1/
Source-Code Compatible With SMJ320C30
Validated Ada Compiler
Single-Cycle 40-Bit Floating-Point,
32-Bit Integer Multipliers
12 40-Bit Registers, 8 Auxiliary Registers,
14 Control Registers, and 2 Timers
D
D
D
D
D
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On-Chip Program Cache and
Dual-Access/Single-Cycle RAM for
Increased Memory-Access Performance
-- 512-Byte Instruction Cache
-- 8K Bytes of Single-Cycle Dual-Access
Program or Data RAM
-- ROM-Based Bootloader Supports
Program Bootup Using 8-, 16-, or 32-Bit
Memories Over Any One of the
Communications Ports
D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture.
EPIC and TI are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2001, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
pinouts
352-LEAD HFH QUAD FLATPACK PACKAGE
325-PIN GF GRID ARRAY PACKAGE
†
†
(TOP VIEW)
(BOTTOM VIEW)
352
265
AR
AP
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
1
264
Y
W
U
R
N
V
T
P
M
K
H
F
L
J
G
E
C
A
D
B
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34
9
11 13 15 17 19 21 23 25 27 29 31 33 35
88
177
1
3
5
7
Pin A1
176
89
TAB 325-LEAD OLB/ILB
TAPE AUTOMATED BONDING (TAB) PACKAGE
†
(TOP VIEW)
1
†
See the pin assignments tables and the signal description table for location and description of all pins.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
description
The C40 digital signal processors (DSPs) are 32-bit, floating-point processors manufactured in 0.72-μm,
double-level metal CMOS technology. The 320C40 is a part of the fourth-generation DSPs from Texas
Instruments and is designed primarily for parallel processing.
For additional information when designing for cold temperature operation, please see Texas Instruments
application report 320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature, literature
number SGUA001.
operation
The 320C40 has six on-chip communication ports for processor-to-processor communication with no external
hardware and simple communication software. This allows connectivity to other C4x processors with no
external-glue logic. The communication ports remove input/output bottlenecks, and the independent smart
DMA coprocessor is able to handle the CPU input/output burden.
central processing unit
The 320C40 CPU is configured for high-speed internal parallelism for the highest sustained performance. The
key features of the CPU are:
D
Eight operations/cycle:
-- 40/32-bit floating-point/integer multiply
-- 40/32-bit floating-point/integer arithmetic logic unit (ALU) operation
-- Two data accesses
-- Two address-register updates
IEEE floating-point conversion
D
D
D
D
Divide and square-root support
C3x assembly language compatibility
Byte and halfword accessibility
DMA coprocessor
The DMA coprocessor allows concurrent I/O and CPU processing for the highest sustained CPU performance.
The key features of the DMA processor are:
D
D
D
D
Link pointers that allow DMA channels to autoinitialize without CPU intervention
Parallel CPU operation and DMA transfers
Six DMA channels that support memory-to-memory data transfers
Split-mode operation doubles the available DMA channels to 12 when data transfers to and from a
communication port are required.
communication ports
The C40 is the first DSP with on-chip communication ports for processor-to-processor communication with no
external hardware and simple communication software. The features of the communication ports are:
D
D
D
Direct interprocessor communication and processor I/O
Six communication ports for direct interprocessor communication and processor I/O
20M-byte/s bidirectional interface on each communication port for high-speed multiprocessor interface
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
communication ports (continued)
D
D
Separate 8-word-deep input and output FIFO buffers for processor-to-processor communication and I/O
Automatic arbitration and handshaking for direct processor-to-processor connection
communication-port software reset (C40 silicon revision ≥ 5.0)
The input and output FIFO levels for a communication port can be flushed by writing at least two back-to-back
values to its communication-port software-reset address as specified in Table 1. This feature is not present in
C40 silicon revision < 5.0. This software reset flushes any word or byte already present in the FIFOs but it does
not affect the status of the communication-port pins. Figure 1 shows an example of
communication-port-software reset.
Table 1. Communication-Port Software-Reset Address
0
1
2
3
4
5
0x0100043
0x0100053
0x0100063
0x0100073
0x0100083
0x0100093
; -------------------------------------------------;
; RESET1:Flush’s FIFO data for communication port 1;
; -------------------------------------------------;
RESET1 push
push
push
ldhi
or
AR0
R0
RC
010h,AR0
050h,AR0
1
R0,*+AR0(3)
10
; Save registers
;
;
; Set AR0 to base address of COM 1
;
; Flush FIFO data with back-to-back write
;
flush: rpts
sti
rpts
nop
; Wait
;
ldi
*+AR0(0),R0 ; Check for new data from other port
and
bnz
pop
01FE0h,R0
flush
RC
;
;
; Restore registers
pop
R0
;
pop
AR0
;
rets
; Return
Figure 1. Example of Communication-Port-Software Reset
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
NMI with bus-grant feature (C40 silicon revision ≥ 5.0)
The 320C40 devices have a software-configurable feature that forces the internal-peripheral bus to ready when
the NMI signal is asserted. This feature is not present in C40 silicon revision < 5.0. The NMI bus-grant feature
is enabled when bits 19--18 of the status register (ST) are set to 10b. When enabled, a peripheral bus-grant
signal is generated on the falling edge of NMI. When NMI is asserted and this feature is not enabled, the CPU
stalls on access to the peripheral bus if it is not ready. A stall condition occurs when writing to a full FIFO or
reading an empty FIFO. This feature is useful in correcting communication-port errors when used in conjunction
with the communication-port software-reset feature.
IDLE2 clock-stop power-down mode (C40 silicon revision ≥ 5.0)
The 320C40 has a clock-stop mode or power-down mode (IDLE2) to achieve extremely low power
consumption. When an IDLE2 instruction is executed, the clocks are halted with H1 being held high. To exit
IDLE2, assert one of the IIOF3--IIOF0 pins configured as an external interrupt instead of a general-purpose I/O.
A macro showing how to generate the IDLE2 opcode is given in Figure 2. During this power-down mode:
D
D
D
No instructions are executed
The CPU, peripherals, and internal memory retain their previous state.
The external-bus outputs are idle. The address lines remain in their previous state, the data lines are in
the high-impedance state, and the output-control signals are inactive.
; ------------------------------------------------;
; IDLE2: Macro to generate idle2 opcode
; ------------------------------------------------;
;
IDLE2
.macro
.word
.endm
06000001h
Figure 2. Example of Software Subroutine Using IDLE2
IDLE2 is exited when one of the five external interrupts (NMI and IIOF3--IIOF0) is asserted low for at least four
input clocks (two H1 cycles). The clocks then start after a delay of two input clocks (one H1 cycle). The clocks
can start in the opposite phase; that is, H1 can be high when H3 was high before the clocks were stopped.
However, the H1 and H3 clocks remain 180° out of phase with each other.
During IDLE2 operation, an external interrupt can be recognized and serviced by the CPU if it is enabled before
entering IDLE2 and asserted for at least two H1 cycles. For the processor to recognize only one interrupt, the
interrupt pin must be configured for edge-trigger mode or asserted less than three cycles in level-trigger mode.
Any external interrupt pin can wake up the device from IDLE2, but for the CPU to recognize that interrupt, it must
also be enabled. If an interrupt is recognized and executed by the CPU, the instruction following the IDLE2
instruction is not executed until after execution of a return opcode.
When the device is in emulation mode, the CPU executes an IDLE2 instruction as if it were an IDLE instruction.
The clocks continue to run for correct operation of the emulator.
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
development tools
The C40 is supported by a host of parallel-processing development tools for developing and simulating code
easily and for debugging parallel-processing systems. The code generation tools include:
D
An ANSI C compiler optimized with a runtime support library that supports use of communication ports and
DMA.
D
D
Third-party support for C, C++, and Ada compilers
Several operating systems available for parallel-processing support, as well as DMA and communication
port drivers
D
An assembler and linker with support for mapping program and data to parallel processors
The simulation tools include:
D
D
Parallel DSP system-level simulation with LAI hardware verification (HV) model and full function (FF) model
TI software simulator with high-level language debugger interface for simulating a single processor
The hardware development and verification tools include:
D
D
Parallel processor in-circuit emulator and high-level language debugger: XDS510™
Parallel processor development system (PPDS) with four 320C40s, local and global memory, and
communication port connections
XDS510 is a trademark of Texas Instruments Incorporated.
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
block diagram
Cache
(512 Bytes)
RAM Block 1
(4K Bytes)
ROM Block
(Reserved)
RAM Block 0
(4K Bytes)
32
32
32
32
32
32
32
32
PDATA Bus
PADDR Bus
DDATA Bus
DADDR 1 Bus
DADDR 2 Bus
D31--D0
A30--A0
DE
AE
M
U
X
STAT3--STAT0
LOCK
STRB0,STRB1
R/W0,RW1
PAGE0,PAGE1
RDY0,RDY1
CE0,CE1
DMADATA Bus
DMAADDR Bus
32
32
32
32
32
IR
PC
MUX
X1
X2/CLKIN
CPU1
CPU2
ROMEN
RESET
REG 1
RESETLOC0,
RESETLOC1
NMI
IIOF3-- IIOF0
C
o
n
t
R
R
E
G
2
C
P
U
1
REG2
E
G
1
r
IACK
H1
o
l
40
40
40
40
H3
32-Bit Barrel
Shifter
l
Multiplier
40
e
r
CV
SS
ALU
DV
DD
40
DV
IV
40
SS
SS
40
Extended
40
32
Precision
Registers
(R0--R11)
LADV
LDDV
DD
40
DD
V
DDL
V
SSL
DISP, IR0, IR1
SUBS
ARAU0
ARAU1
BK
32
32
32
32
32
32
32
32
Auxiliary
Registers
(AR0--AR7)
32
32
Other
Registers
(14)
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
block diagram (continued)
PDATA Bus
PADDR Bus
DDATA Bus
DADDR 1 Bus
LD31--LD0
LA30--LA0
LDE
LAE
LSTAT3--LSTAT0
LLOCK
LSTRB0--LSTRB1
LR/W0--LR/W1
LPAGE0--LPAGE1
LRDY0--LRDY1
LCE0, LCE1
M
U
X
DADDR 2 Bus
DMADATA Bus
DMAADDR Bus
MUX
32
32
32
32
COM Port 0
CREQ0
Input
CACK0
FIFO
32
32
CSTRB0
CRDY0
PAU
32
32
DMA Coprocessor
DMA Channel 0
DMA Channel 1
DMA Channel 2
DMA Channel 3
DMA Channel 4
DMA Channel 5
Output
FIFO
C0D7--C0D0
Port Control Registers
COM Port 5
P
e
r
P
e
r
i
32
p
h
e
r
a
l
CREQ5
CACK5
Input
FIFO
32
i
p
h
e
r
a
l
CSTRB5
PAU
32
32
32
Output
FIFO
Six DMA Channels
CRDY5
C5D7--C5D0
Port Control Registers
A
d
d
r
e
s
s
Timer 0
D
a
t
32
Global Control Register
Time Period Register
Timer Counter Register
TCLK0
a
32
32
B
u
s
B
u
s
Timer 1
Global Control Register
Time Period Register
Timer Counter Register
TCLK1
Port Control
Global
Local
32
32
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
memory map
Figure 3 shows the memory map for the 320C40. See the TMS320C4x User’s Guide (literature number
SPRU063) for a detailed description of this memory mapping.
000000000h
Boot-Loader ROM
(Internal)
Structure
Depends
Upon
000000FFFh
000001000h
Accessible Local Bus
(External)
1M
1M
Reserved
ROMEN Bit
0000FFFFFh
000100000h
Peripherals (Internal)
Reserved
Peripherals (Internal)
0001000FFh
000100100h
Reserved
Reserved
0001FFFFFh
000200000h
Reserved
0002FF7FFh
0002FF800h
2G
1M
1K RAM BLK 0 (Internal)
1K RAM BLK 1 (Internal)
1K RAM BLK 0 (Internal)
1K RAM BLK 1 (Internal)
0002FFBFFh
0002FFC00h
0002FFFFFh
000300000h
2G--3M
Structure
Identical
Local Bus
(External)
Local Bus
(External)
07FFFFFFFh
080000000h
Global Bus (External)
Global Bus (External)
2G
0FFFFFFFFh
(a) Internal ROM Disabled
(ROMEN = 0)
(b) Internal ROM Enabled
(ROMEN = 1)
Microprocessor Mode
Microcomputer Mode
Figure 3. Memory Map for 320C40
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
signal descriptions
This section gives signal descriptions for the SMJ320C40 device. The SMJ320C40 signal descriptions table
lists each signal, the number of pins, operating mode(s) (that is, input, output, or high-impedance state as
indicated by I, O, or Z, respectively), and function. All pins labeled NC are not to be connected by the user. A
line over a signal name (for example, RESET) indicates that the signal is active low (true at a logic-0 level). The
signals are grouped according to functions.
SMJ320C40 Signal Descriptions
SIGNAL
†
DESCRIPTION
GLOBAL BUS EXTERNAL INTERFACE (80 PINS)
TYPE
NO. OF
PINS
NAME
D31--D0
32
1
I/O/Z
32-bit data port of the global bus external interface
Data-bus-enable signal for the global bus external interface
31-bit address port of the global bus external interface
Address-bus-enable signal for the global bus external interface
Status signals for the global bus external interface
Lock signal for the global bus external interface
Access strobe 0 for the global bus external interface
Read/write signal for STRB0 accesses
DE
I
O/Z
I
A30--A0
AE
31
1
STAT3--STAT0
LOCK
4
O
1
O
‡
STRB0
1
O/Z
O/Z
O/Z
I
‡
R/W0
1
‡
PAGE0
1
Page signal for STRB0 accesses
‡
RDY0
1
Ready signal for STRB0 accesses
‡
CE0
1
I
Control enable for the STRB0, PAGE0, and R/W0 signals
Access strobe 1 for the global bus external interface
Read/write signal for STRB1 accesses
‡
STRB1
1
O/Z
O/Z
O/Z
I
‡
R/W1
1
‡
PAGE1
1
Page signal for STRB1 accesses
‡
RDY1
1
Ready signal for STRB1 accesses
‡
CE1
1
I
Control enable for the STRB1, PAGE1, and R/W1 signals
LOCAL BUS EXTERNAL INTERFACE (80 PINS)
32-bit data port of the local bus external interface
Data-bus-enable signal for the local bus external interface
31-bit address port of the local bus external interface
Address-bus-enable signal for the local bus external interface
Status signals for the local bus external interface
Lock signal for the local bus external interface
Access strobe 0 for the local bus external interface
Read/write signal for LSTRB0 accesses
LD31--LD0
LDE
32
1
I/O/Z
I
LA30--LA0
LAE
31
1
O/Z
I
LSTAT3--LSTAT0
4
O
LLOCK
1
O
‡
LSTRB0
1
O/Z
O/Z
O/Z
I
LR/W0
LPAGE0
LRDY0
LCE0
1
1
Page signal for LSTRB0 accesses
1
Ready signal for LSTRB0 accesses
1
I
Control enable for the LSTRB0, LPAGE0, and LR/W0 signals
Access strobe 1 for the local bus external interface
Read/write signal for LSTRB1 accesses
‡
LSTRB1
1
O/Z
O/Z
LR/W1
1
†
I = input, O = output, Z = high impedance
STRB0, STRB1 and associated signals (R/W1, R/W0, PAGE0, PAGE1, etc.) are effective over the address ranges defined by the
STRB ACTIVE bits.
‡
§
HFH package has additional power and ground pins to reduce noise problems.
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
signal descriptions (continued)
SMJ320C40 Signal Descriptions (Continued)
SIGNAL
NAME
†
DESCRIPTION
TYPE
NO. OF
PINS
LOCAL BUS EXTERNAL INTERFACE (80 PINS) (CONTINUED)
LPAGE1
1
1
1
O/Z
Page signal for LSTRB1 accesses
LRDY1
LCE1
I
I
Ready signal for LSTRB1 accesses
Control enable for the LSTRB1, LPAGE1, and LR/W1 signals
COMMUNICATION PORT 0 INTERFACE (12 PINS)
Communication port 0 data bus
C0D7--C0D0
CREQ0
8
1
1
1
1
I/O
I/O
I/O
I/O
I/O
Communication port 0 token-request signal
Communication port 0 token-request-acknowledge signal
Communication port 0 data-strobe signal
Communication port 0 data-ready signal
CACK0
CSTRB0
CRDY0
COMMUNICATION PORT 1 INTERFACE (12 PINS)
Communication port 1 data bus
C1D7--C1D0
CREQ1
8
1
1
1
1
I/O
I/O
I/O
I/O
I/O
Communication port 1 token-request signal
Communication port 1 token-request-acknowledge signal
Communication port 1 data-strobe signal
Communication port 1 data-ready signal
CACK1
CSTRB1
CRDY1
COMMUNICATION PORT 2 INTERFACE (12 PINS)
Communication port 2 data bus
C2D7--C2D0
CREQ2
8
1
1
1
1
I/O
I/O
I/O
I/O
I/O
Communication port 2 token-request signal
Communication port 2 token-request-acknowledge signal
Communication port 2 data-strobe signal
Communication port 2 data-ready signal
CACK2
CSTRB2
CRDY2
COMMUNICATION PORT 3 INTERFACE (12 PINS)
Communication port 3 data bus
C3D7--C3D0
CREQ3
8
1
1
1
1
I/O
I/O
I/O
I/O
I/O
Communication port 3 token-request signal
Communication port 3 token-request-acknowledge signal
Communication port 3 data-strobe signal
Communication port 3 data-ready signal
CACK3
CSTRB3
CRDY3
COMMUNICATION PORT 4 INTERFACE (12 PINS)
Communication port 4 data bus
C4D7--C4D0
CREQ4
8
1
1
1
1
I/O
I/O
I/O
I/O
I/O
Communication port 4 token-request signal
Communication port 4 token-request-acknowledge signal
Communication port 4 data-strobe signal
Communication port 4 data-ready signal
CACK4
CSTRB4
CRDY4
†
I = input, O = output, Z = high impedance
STRB0, STRB1 and associated signals (R/W1, R/W0, PAGE0, PAGE1, etc.) are effective over the address ranges defined by the
STRB ACTIVE bits.
‡
§
HFH package has additional power and ground pins to reduce noise problems.
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
signal descriptions (continued)
SMJ320C40 Signal Descriptions (Continued)
SIGNAL
NAME
†
DESCRIPTION
COMMUNICATION PORT 5 INTERFACE (12 PINS)
TYPE
NO. OF
PINS
C5D7--C5D0
CREQ5
8
1
1
1
1
I/O
I/O
I/O
I/O
I/O
Communication port 5 data bus
Communication port 5 token-request signal
Communication port 5 token-request-acknowledge signal
Communication port 5 data-strobe signal
Communication port 5 data-ready signal
INTERRUPTS, I/O FLAGS, RESET, TIMER (12 PINS)
Interrupt and I/O flags
CACK5
CSTRB5
CRDY5
IIOF3-- IIOF0
NMI
4
1
1
1
I/O
I
O
I
Nonmaskable interrupt. NMI is sensitive to a low-going edge.
Interrupt acknowledge
IACK
RESET
Reset signal
RESETLOC1--
RESETLOC0
2
I
Reset-vector location pins
ROMEN
TCLK0
TCLK1
1
1
1
I
On-chip ROM enable (0 = disable, 1 = enable)
I/O
I/O
Timer 0 pin
Timer 1 pin
CLOCK (4 PINS)
Crystal pin
X1
1
1
1
1
O
I
X2/CLKIN
H1
Crystal/oscillator pin
H1 clock
O
O
H3
H3 clock
§
POWER AND GROUND (70 PINS)
§
CV
DV
15
I
I
I
I
I
I
I
I
I
I
I
Ground pins
Ground pins
Ground pins
SS
SS
§
15
§
IV
6
SS
DV
13
§
5-V supply pins
DC
DD
GADV
GDDV
3
5-V supply pins
DC
DD
DD
DD
DD
§
3
5-V supply pins
DC
§
LADV
LDDV
3
5-V supply pins
DC
§
3
5-V supply pins
DC
SUBS
1
4
4
Substrate pin (tie to ground)
V
V
5-V supply pins
DDL
SSL
DC
Ground pins
†
‡
I = input, O = output, Z = high impedance
STRB0, STRB1 and associated signals (R/W1, R/W0, PAGE0, PAGE1, etc.) are effective over the address ranges defined by the
STRB ACTIVE bits.
§
HFH package has additional power and ground pins to reduce noise problems.
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
signal descriptions (continued)
SMJ320C40 Signal Descriptions (Continued)
SIGNAL
NAME
†
DESCRIPTION
TYPE
NO. OF
PINS
EMULATION (7 PINS)
IEEE 1149.1 test port clock
TCK
1
1
1
1
1
1
1
I
O/Z
I
TDO
TDI
IEEE 1149.1 test port data out
IEEE 1149.1 test port data in
IEEE 1149.1 test port mode select
IEEE 1149.1 test port reset
Emulation pin 0
TMS
TRST
EMU0
I
I
I/O
I/O
EMU1
Emulation pin 1
†
I = input, O = output, Z = high impedance
STRB0, STRB1 and associated signals (R/W1, R/W0, PAGE0, PAGE1, etc.) are effective over the address ranges defined by the
STRB ACTIVE bits.
‡
§
HFH package has additional power and ground pins to reduce noise problems.
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
GF package pin assignments — alphabetical listing
NAME
A0
NO.
D32
B32
D30
C29
B30
F28
F24
E29
C27
D28
B28
F26
C25
E27
B26
D26
C23
B24
E25
C21
D24
B22
E23
C19
D22
B20
E21
B18
C17
D20
B16
AG31
AP4
AL5
AN5
AM4
AP6
AM6
NAME
C0D6
C0D7
C1D0
C1D1
C1D2
C1D3
C1D4
C1D5
C1D6
C1D7
C2D0
C2D1
C2D2
C2D3
C2D4
C2D5
C2D6
C2D7
C3D0
C3D1
C3D2
C3D3
C3D4
C3D5
C3D6
C3D7
C4D0
C4D1
C4D2
C4D3
C4D4
C4D5
C4D6
C4D7
C5D0
C5D1
C5D2
C5D3
NO.
AN7
NAME
C5D4
NO.
AM30
AP32
AM32
AL31
AN11
AN13
AM14
AM16
AK32
AJ31
AA33
V34
NAME
NO.
E35
AR25
AE1
AR13
A19
R35
AL1
U33
V32
T34
U31
R33
P34
T32
N33
R31
M34
P32
L33
NAME
D31
NO.
F32
CV
CV
CV
CV
CV
CV
CV
SS
SS
SS
SS
SS
SS
SS
A1
AK8
C5D5
DE
AA31
AR11
AR29
A13
A7
A2
AL7
C5D6
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
A3
AP8
C5D7
A4
AM8
CACK0
CACK1
CACK2
CACK3
CACK4
CACK5
CE0
A5
AK12
AK10
AN9
A6
A17
L35
A7
D0
A8
AL9
D1
D2
AR23
A29
L1
A9
AP10
AM18
AN19
AL19
AP20
AM20
AN21
AL21
AP22
AM22
AN23
AL23
AP24
AM24
AN25
AL25
AP26
AN27
AM26
AK24
AL27
AP28
AK26
AN29
AM28
AL29
AP30
AK28
AN31
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
AE
D3
CE1
D4
AC1
AR17
A23
AJ1
CRDY0
CRDY1
CRDY2
CRDY3
CRDY4
CRDY5
CREQ0
CREQ1
CREQ2
CREQ3
CREQ4
CREQ5
CSTRB0
CSTRB1
CSTRB2
CSTRB3
CSTRB4
CSTRB5
AP12
AP14
AL15
AL17
AH30
AH32
AM10
AM12
AN15
AN17
AN33
AL33
AL11
AL13
AP16
AP18
AM34
AK34
AR19
AR7
D5
D6
D7
D8
AJ35
A21
A25
G35
A11
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
N31
K34
M32
J33
AG1
AM2
R1
L31
AR21
AR15
A15
AR27
G1
M30
K32
H34
J31
G33
K30
F34
H32
E33
D34
G31
C33
H30
E31
N35
AR9
AA35
AD34
B2
CV
CV
CV
CV
CV
CV
CV
CV
EMU0
EMU1
SS
SS
SS
SS
SS
SS
SS
SS
C0D0
C0D1
C0D2
C0D3
C0D4
C0D5
N1
GADV
GADV
GADV
GDDV
GDDV
GDDV
DD
DD
DD
DD
DD
DD
AL35
A27
AR1
U35
V2
A9
E1
A35
A1
J35
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
GF package pin assignments — alphabetical listing (continued)
NAME
H1
NO.
AC3
AC5
W3
AN3
AL3
AH6
AK2
AR5
AR31
AG35
A31
J1
NAME
LA25
LA26
LA27
LA28
LA29
LA30
NO.
R5
NAME
LD26
LD27
LD28
LD29
LD30
LD31
NO.
B4
NAME
STAT0
STAT1
STAT2
STAT3
STRB0
STRB1
SUBS
TCK
NO.
AD32
AE33
AF34
AE31
AD30
AC33
C31
H3
T2
F8
IACK
IIOF0
IIOF1
IIOF2
IIOF3
U3
D6
T4
C3
V4
E5
U5
F6
LADV
LADV
LADV
B34
AB2
AP34
AB4
AG5
AF2
E19
C15
D18
B14
E17
D16
C13
E15
B12
D14
C11
E13
B10
D12
C9
LDDV
LDDV
LDDV
AR35
AP2
U1
DD
DD
DD
DD
DD
DD
IV
IV
IV
IV
IV
IV
Y34
SS
SS
SS
SS
SS
SS
TCLK0
TCLK1
TDO
AE3
LAE
LCE0
LCE1
LD0
LDE
LLOCK
LOCK
AD4
AA5
W33
AH2
AG3
AF6
AE5
AH4
AF4
AA3
Y4
AD2
AB34
AC35
W35
AE35
AN1
AN35
C35
TDI
A5
LPAGE0
LPAGE1
LRDY0
LRDY1
LR/W0
TMS
LA0
LA1
D2
LD1
TRST
D4
LD2
V
V
V
V
DDL
DDL
DDL
DDL
LA2
E3
LD3
LA3
F4
LD4
LA4
H6
LD5
LR/W1
C1
LA5
F2
LD6
LSTAT0
LSTAT1
LSTAT2
LSTAT3
LSTRB0
LSTRB1
NMI
V
V
V
V
A3
SSL
SSL
SSL
SSL
LA6
G5
LD7
AR3
AR33
A33
LA7
G3
LD8
Y2
LA8
H4
LD9
W5
LA9
H2
LD10
LD11
LD12
LD13
LD14
LD15
LD16
LD17
LD18
LD19
LD20
LD21
LD22
LD23
LD24
LD25
AJ3
AD6
AJ5
AG33
AB32
Y32
W31
AF30
AH34
AJ33
AK4
AF32
AC31
X1
W1
LA10
LA11
LA12
LA13
LA14
LA15
LA16
LA17
LA18
LA19
LA20
LA21
LA22
LA23
LA24
K6
X2/CLKIN
AA1
M6
J5
PAGE0
PAGE1
RDY0
J3
K4
E11
F12
D10
B8
K2
RDY1
L3
RESETLOC0
RESETLOC1
RESET
ROMEN
R/W0
L5
M2
M4
N3
E9
C7
F10
B6
N5
R/W1
P2
D8
P4
C5
R3
E7
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
GF package pin assignments — numerical listing
NO.
A1
NAME
GDDV
NO.
AD30
AD32
AD34
AE1
NAME
STRB0
STAT0
EMU1
NO.
AK24
AK26
AK28
AK32
AK34
AL1
NAME
C4D2
NO.
AM30
AM32
AM34
AN1
NAME
C5D4
DD
SSL
A3
V
C4D5
C5D6
A5
IV
C5D2
CSTRB4
SS
A7
DV
CV
DV
DV
DV
DV
CV
DV
DV
DV
CV
DV
CV
CACK4
CSTRB5
V
DDL
DD
SS
A9
AE3
TCLK0
LRDY1
STAT3
AN3
IIOF0
C0D2
SS
SS
DD
SS
DD
SS
SS
DD
SS
SS
DD
SS
SSL
A11
AE5
CV
AN5
SS
A13
A15
A17
A19
A21
A23
A25
A27
A29
A31
A33
A35
AA1
AA3
AA5
AA31
AA33
AA35
AB2
AB4
AB32
AB34
AC1
AC3
AC5
AC31
AC33
AC35
AD2
AD4
AD6
AE31
AE33
AE35
AF2
AL3
IIOF1
C0D1
AN7
C0D6
STAT1
AL5
AN9
C1D5
TRST
AL7
C1D0
AN11
AN13
AN15
AN17
AN19
AN21
AN23
AN25
AN27
AN29
AN31
AN33
AN35
AP2
CACK0
CACK1
CREQ2
CREQ3
C2D1
LCE1
AL9
C1D6
AF4
LR/W1
LRDY0
RESETLOC0
R/W0
AL11
AL13
AL15
AL17
AL19
AL21
AL23
AL25
AL27
AL29
AL31
AL33
AL35
AM2
CSTRB0
CSTRB1
CRDY2
CRDY3
C2D2
AF6
AF30
AF32
AF34
AG1
AG3
AG5
AG31
AG33
AG35
AH2
C2D5
STAT2
C3D1
IV
DV
C2D6
C3D5
SS
V
LPAGE1
LCE0
AE
C3D2
C4D0
GDDV
C3D6
C4D6
DD
X2/CLKIN
LSTAT0
LLOCK
DE
C4D3
C5D3
PAGE0
C5D0
CREQ4
IV
C5D7
V
DDL
SS
LPAGE0
LR/W0
CREQ5
LDDV
DD
CE0
AH4
CV
DV
AP4
C0D0
C0D4
SS
SS
EMU0
AH6
IIOF2
AP6
LADV
AH30
AH32
AH34
AJ1
CRDY4
AM4
C0D3
C0D5
AP8
C1D1
DD
LAE
PAGE1
TDO
CRDY5
AM6
AP10
AP12
AP14
AP16
AP18
AP20
AP22
AP24
AP26
AP28
AP30
AP32
AP34
C1D7
RESETLOC1
AM8
C1D2
CRDY0
CRDY1
CSTRB2
CSTRB3
C2D3
DV
AM10
AM12
AM14
AM16
AM18
AM20
AM22
AM24
AM26
AM28
CREQ0
CREQ1
CACK2
CACK3
C2D0
DD
DV
AJ3
LSTRB0
NMI
DD
H1
AJ5
H3
R/W1
STRB1
TDI
AJ31
AJ33
AJ35
AK2
CACK5
RESET
C2D7
DV
C2D4
C3D3
SS
IIOF3
ROMEN
C0D7
C3D0
C3D7
TCLK1
LDE
AK4
C3D4
C4D4
AK8
C4D1
C5D1
LSTRB1
AK10
AK12
C1D4
C4D7
C5D5
C1D3
LADV
DD
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
GF package pin assignments — numerical listing (continued)
NO.
AR1
AR3
AR5
AR7
AR9
AR11
AR13
AR15
AR17
AR19
AR21
AR23
AR25
AR27
AR29
AR31
AR33
AR35
B2
NAME
GADV
NO.
C1
NAME
NO.
E1
NAME
CV
NO.
H2
NAME
LA9
NO.
P2
NAME
LA22
LA23
D10
V
DD
SSL
DDL
SS
V
C3
LD29
LD24
LD20
LD14
LD10
LD6
LD1
A28
E3
LA2
LD30
LD25
LD19
LD15
LD11
LD7
LD4
LD0
A26
H4
LA8
P4
IV
C5
E5
H6
LA4
P32
P34
R1
SS
CV
DV
DV
CV
DV
DV
CV
DV
DV
CV
DV
DV
C7
E7
H30
H32
H34
J1
D29
D24
D19
D5
SS
C9
E9
DV
SS
SS
DD
SS
SS
DD
SS
SS
DD
SS
SS
DD
SS
SSL
C11
C13
C15
C17
C19
C21
C23
C25
C27
C29
C31
C33
C35
D2
E11
E13
E15
E17
E19
E21
E23
E25
E27
E29
E31
E33
E35
F2
R3
LA24
LA25
D8
IV
R5
SS
J3
LA13
LA12
D20
R31
R33
R35
T2
J5
D4
A23
J31
J33
J35
K2
CV
SS
A19
D15
LA26
LA28
D6
A16
A22
CV
T4
SS
A12
A18
LA15
LA14
LA10
D22
T32
T34
U1
A8
A13
K4
D2
A3
A7
K6
LDDV
DD
IV
SUBS
D28
D30
D25
K30
K32
K34
L1
U3
LA27
LA30
D3
V
D18
U5
LDDV
V
CV
SS
D13
U31
U33
U35
V2
DD
DDL
GADV
LA0
LA1
LD28
LD23
LD17
LD13
LD9
LD5
LD2
A29
A24
A20
A15
A9
LA5
LA3
LD31
LD27
LD21
LD16
A6
DV
D0
DD
DD
B4
LD26
LD22
LD18
LD12
LD8
LD3
A30
A27
A25
A21
A17
A14
A10
A4
D4
F4
L3
LA16
LA17
D16
GADV
DD
DD
B6
D6
F6
L5
GDDV
B8
D8
F8
L31
L33
L35
M2
M4
M6
M30
M32
M34
N1
V4
LA29
D1
B10
D10
D12
D14
D16
D18
D20
D22
D24
D26
D28
D30
D32
D34
F10
F12
F24
F26
F28
F32
F34
G1
D11
V32
V34
W1
W3
W5
W31
W33
W35
Y2
B12
DV
CE1
DD
B14
LA18
LA19
LA11
D17
D14
D9
X1
B16
A11
IACK
LSTAT3
RDY1
LOCK
TMS
B18
A5
B20
D31
D23
B22
B24
DV
SS
B26
G3
LA7
LA6
D27
D21
CV
LSTAT2
LSTAT1
RDY0
TCK
SS
B28
G5
N3
LA20
LA21
D12
D7
Y4
B30
A2
G31
G33
G35
N5
Y32
Y34
B32
A1
A0
N31
N33
N35
B34
LADV
D26
DV
SS
DD
DV
SS
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
HFH package pin assignments — alphabetical listing
NAME
A0
NO.
348
347
346
345
343
342
341
340
339
338
337
336
335
334
333
332
331
324
323
322
321
320
319
318
317
316
315
314
312
311
310
75
NAME
C1D0
C1D1
C1D2
C1D3
C1D4
C1D5
C1D6
C1D7
C2D0
C2D1
C2D2
C2D3
C2D4
C2D5
C2D6
C2D7
C3D0
C3D1
C3D2
C3D3
C3D4
C3D5
C3D6
C3D7
C4D0
C4D1
C4D2
C4D3
C4D4
C4D5
C4D6
C4D7
C5D0
C5D1
C5D2
C5D3
C5D4
C5D5
C5D6
C5D7
NO.
168
167
166
165
164
163
162
161
131
130
129
128
127
126
125
124
120
119
118
117
116
115
114
113
108
107
106
105
104
103
102
101
99
NAME
CACK0
CACK1
CACK2
CACK3
CACK4
CACK5
CE0
NO.
153
149
144
138
86
NAME
NO.
241
263
282
306
307
327
328
349
41
40
39
38
37
35
34
33
32
31
30
29
28
27
26
25
17
16
15
14
13
12
11
10
9
NAME
NO.
53
†
CV
CV
CV
CV
CV
CV
CV
CV
DE
SS
SS
SS
SS
SS
SS
SS
SS
†
†
†
†
†
†
†
‡
A1
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
63
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
A2
77
A3
91
A4
100
112
121
135
146
160
169
179
195
219
23
A5
82
A6
51
A7
CE1
42
A8
CRDY0
CRDY1
CRDY2
CRDY3
CRDY4
CRDY5
CREQ0
CREQ1
CREQ2
CREQ3
CREQ4
CREQ5
CSTRB0
CSTRB1
CSTRB2
CSTRB3
CSTRB4
151
147
142
136
84
D0
A9
D1
D2
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
AE
D3
D4
80
D5
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
154
150
145
139
87
D6
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
D7
24
D8
44
D9
45
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
61
83
62
152
148
143
137
85
89
90
110
111
133
134
157
158
182
183
220
221
242
243
261
262
283
284
308
309
CSTRB5
81
†
CV
CV
CV
CV
CV
CV
CV
CV
CV
CV
CV
CV
CV
CV
18
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
†
†
†
†
†
†
†
†
†
†
†
†
†
19
46
47
88
109
132
155
156
178
196
217
218
240
C0D0
C0D1
C0D2
C0D3
C0D4
C0D5
C0D6
C0D7
177
176
175
174
173
172
171
170
98
8
97
6
96
5
95
4
94
3
93
2
92
1
†
‡
§
¶
#
CV and IV pins are connected internally.
SS
SS
DV , LADV , LDDV , GDDV , and GADV pins are connected internally.
DD
DD
DD
DD
DD
DV pins are connected internally.
SS
V
V
pins are connected internally.
pins are connected internally.
DDL
SSL
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
HFH package pin assignments — alphabetical listing (continued)
NAME
NO.
329
330
350
351
59
NAME
LA12
LA13
LA14
LA15
LA16
LA17
LA18
LA19
LA20
LA21
LA22
LA23
LA24
LA25
LA26
LA27
LA28
LA29
LA30
NO.
247
246
245
244
237
236
235
234
233
232
231
230
229
228
227
225
224
223
222
226
238
239
256
205
192
199
303
302
301
300
299
297
296
295
294
293
292
291
290
289
NAME
LD14
LD15
LD16
LD17
LD18
LD19
LD20
LD21
LD22
LD23
LD24
LD25
LD26
LD27
LD28
LD29
LD30
LD31
NO.
288
287
286
279
278
277
276
275
274
273
272
271
270
269
267
266
265
264
268
280
281
298
200
207
48
NAME
RDY0
NO.
52
§
DV
DV
DV
DV
SS
SS
SS
SS
§
§
§
RDY1
43
RESET
RESETLOC0
RESETLOC1
ROMEN
R/W0
79
78
EMU0
EMU1
76
60
180
73
‡
‡
‡
‡
‡
‡
‡
‡
GADV
313
325
326
344
7
DD
DD
DD
DD
DD
DD
DD
DD
GADV
GADV
GADV
GDDV
GDDV
GDDV
GDDV
H1
R/W1
65
STAT0
STAT1
STAT2
STAT3
STRB0
STRB1
SUBS
67
68
70
21
71
22
74
36
66
204
203
212
181
184
185
186
20
352
54
H3
TCK
IACK
IIOF0
IIOF1
IIOF2
TCLK0
TCLK1
TDO
201
202
55
‡
‡
‡
‡
LDDV
DD
DD
DD
DD
‡
‡
‡
‡
LADV
LADV
LADV
LADV
LDDV
LDDV
LDDV
TDI
56
DD
DD
DD
DD
IIOF3
TMS
57
†
IV
IV
IV
IV
IV
IV
IV
TRST
58
SS
SS
SS
SS
SS
SS
SS
†
†
†
†
†
†
¶
69
LDE
LLOCK
LOCK
V
V
V
V
V
V
V
V
49
DDL
DDL
DDL
DDL
¶
¶
¶
122
123
159
206
285
260
259
258
257
255
254
253
252
251
250
249
248
LAE
LCE0
LCE1
LD0
140
213
304
50
LPAGE0
LPAGE1
LRDY0
LRDY1
LR/W0
LR/W1
LSTAT0
LSTAT1
LSTAT2
LSTAT3
LSTRB0
LSTRB1
NMI
190
197
191
198
189
194
208
209
210
211
188
193
187
72
#
#
#
#
SSL
SSL
SSL
LD1
141
214
305
215
216
LA0
LA1
LA2
LA3
LA4
LA5
LA6
LA7
LA8
LA9
LA10
LA11
LD2
LD3
SSL
LD4
X1
LD5
X2/CLKIN
LD6
LD7
LD8
LD9
LD10
LD11
LD12
LD13
PAGE0
PAGE1
64
†
‡
§
¶
#
CV and IV pins are connected internally.
SS
SS
DV , LADV , LDDV , GDDV , and GADV pins are connected internally.
DD
DD
DD
DD
DD
DV pins are connected internally.
SS
V
V
pins are connected internally.
pins are connected internally.
DDL
SSL
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
HFH package pin assignments — numerical listing
NO.
1
NAME
D31
D30
D29
D28
D27
D26
NO.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
NAME
D0
NO.
81
NAME
CSTRB5
CACK5
CREQ5
CRDY4
CSTRB4
CACK4
NO.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
NAME
NO.
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
NAME
C1D7
C1D6
C1D5
C1D4
C1D3
C1D2
C1D1
‡
DV
DD
†
2
CE1
82
IV
IV
SS
SS
†
3
RDY1
83
§
4
DV
DV
CV
CV
84
C2D7
C2D6
C2D5
C2D4
C2D3
C2D2
C2D1
C2D0
SS
SS
SS
SS
§
†
†
5
85
6
86
‡
7
GDDV
87
CREQ4
DD
†
8
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
LOCK
88
CV
DV
DV
DV
C1D0
SS
SS
SS
¶
§
§
‡
‡
9
V
89
DV
DD
DDL
#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
V
90
C0D7
C0D6
C0D5
C0D4
C0D3
C0D2
C0D1
C0D0
SSL
CE0
RDY0
DE
91
DD
†
92
C5D7
C5D6
C5D5
C5D4
C5D3
C5D2
C5D1
C5D0
CV
DV
DV
DV
SS
SS
SS
§
§
‡
93
TCK
TDO
TDI
94
95
DD
96
CRDY3
CSTRB3
CACK3
TMS
TRST
EMU0
97
†
†
†
CV
98
CV
DV
SS
SS
DD
‡
CV
99
CREQ3
SS
†
‡
¶
IV
EMU1
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DV
V
DDL
ROMEN
SS
DD
‡
‡
§
#
GDDV
GDDV
DV
DV
DV
C4D7
C4D6
C4D5
C4D4
C4D3
C4D2
C4D1
C4D0
V
SSL
IIOF0
DD
SS
SS
§
‡
§
CRDY2
CSTRB2
CACK2
DV
DV
DD
§
SS
SS
§
DV
DV
SS
DD
§
PAGE1
R/W1
IIOF1
IIOF2
SS
D15
D14
D13
D12
D11
D10
D9
CREQ2
‡
STRB1
STAT0
DV
IIOF3
DD
CRDY1
CSTRB1
CACK1
CREQ1
CRDY0
CSTRB0
CACK0
NMI
STAT1
LSTRB0
LR/W0
LPAGE0
LRDY0
LCE0
†
†
IV
CV
DV
DV
DV
SS
SS
SS
SS
§
§
‡
STAT2
STAT3
PAGE0
R/W0
STRB0
AE
D8
DD
D7
C3D7
C3D6
C3D5
C3D4
C3D3
C3D2
C3D1
C3D0
LSTRB1
D6
CREQ0
LR/W1
†
‡
D5
CV
CV
DV
DV
DV
SS
SS
SS
SS
DD
‡
†
§
§
†
GDDV
D4
RESETLOC1
CV
DD
SS
‡
DV
LPAGE1
LRDY1
LCE1
DD
D3
RESETLOC0
RESET
†
D2
IV
SS
‡
D1
CRDY5
DV
LDE
DD
†
‡
§
¶
#
CV and IV pins are connected internally.
SS
SS
DV , LADV , LDDV , GDDV , and GADV pins are connected internally.
DD
DD
DD
DD
DD
DV pins are connected internally.
SS
V
V
pins are connected internally.
pins are connected internally.
DDL
SSL
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
HFH package pin assignments — numerical listing (continued)
NO.
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
NAME
TCLK0
TCLK1
H3
NO.
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
NAME
NO.
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
NAME
NO.
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
NAME
A20
†
‡
CV
DV
DV
LDDV
SS
SS
SS
DD
†
§
§
CV
DV
DV
A19
SS
§
§
A18
SS
SS
H1
LA15
LA14
LA13
LA12
LA11
LA10
LA9
A17
†
‡
‡
LAE
IV
GADV
DD
SS
†
IV
LD16
LD15
LD14
LD13
LD12
LD11
LD10
LD9
GADV
SS
DD
†
LLOCK
LSTAT0
LSTAT1
LSTAT2
LSTAT3
CV
CV
DV
DV
SS
†
§
§
SS
SS
SS
LA8
A16
A15
A14
A13
A12
A11
A10
A9
IACK
LA7
¶
V
LA6
DDL
#
V
LA5
LD8
SSL
X1
LA4
LD7
‡
‡
‡
X2/CLKIN
LADV
LD6
DD
†
CV
CV
DV
DV
DV
LA3
LA2
LA1
LA0
LD5
SS
SS
†
‡
‡
LDDV
DD
LD4
LD3
LD2
LD1
LD0
A8
DD
§
A7
SS
SS
§
§
§
†
DV
A6
SS
SS
SS
LA30
LA29
LA28
LA27
DV
CV
A5
A4
¶
‡
LD31
LD30
LD29
LD28
V
GADV
DDL
DD
#
V
A3
SSL
‡
†
LADV
CV
CV
DV
DV
A2
DD
SS
SS
SS
SS
†
§
§
LA26
LA25
LA24
LA23
LA22
LA21
LA20
LA19
LA18
LA17
LA16
A1
LDDV
A0
DD
†
LD27
LD26
LD25
LD24
LD23
LD22
LD21
LD20
LD19
LD18
LD17
CV
DV
DV
SS
§
§
A30
A29
A28
SS
SS
SUBS
‡
GADV
DD
A27
A26
A25
A24
A23
A22
A21
‡
‡
LADV
DD
LADV
DD
†
CV
LDDV
DD
SS
†
‡
§
¶
#
CV and IV pins are connected internally.
SS
SS
DV , LADV , LDDV , GDDV , and GADV pins are connected internally.
DD
DD
DD
DD
DD
DV pins are connected internally.
SS
V
V
pins are connected internally.
pins are connected internally.
DDL
SSL
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
SMJ320C40 (Rev. 5) Inner Lead Bond (ILB) Information for TAB
325 Die Side Number 4 244
243
Pad Number One
1
Die Designator
XXXXX
Die Side Number 3
Die Side Number 1
81
163
Zero-Zero
(Origin)
82
Die Side Number 2
162
Figure 4. SMJ320C40 Die Numbering Format
(See Table 2)
The inner lead bond (ILB) pitch for the tape automated bonding (TAB) leadframe is the same as the die bond
pad pitch. Table 2 provides a reference for the following:
A. The TAB lead numbers. The TAB lead numbers are the same as the die bond pad numbers.
B. The C40 signal identities in relation to the pad numbers
C. There are 325 bond pad locations, 325 TAB leads, and 324 test pad locations.
D. The C40 X-,Y-coordinates, where bond pad 82 serves as the origin, (0,0)
E. The inner lead bond pitch (ILB) is the same as the die bond pitch.
F.
The outer lead pitch is 0.25 ± 0.01 mm.
G. The test pad pitch is 0.40 ± 0.01 mm.
H. The tape width is 48 mm.
I.
In addition, the following notes are significant:
J. X,Y coordinate data is in microns.
K. Average pitch is 126 μm (4.96 mils).
L. Smallest pitch value is 126 μm (4.96 mils).
Outer lead bond (OLB) 18, 19 connect to test pad 18.
M. The active silicon dimensions are 12424.86 μm × 12035.52 μm (489.16 mils × 473.83 mils).
N. The die size is approximately 12598.40 μm × 12192.00 μm (496.00 mils × 480.00 mils).
O. Distance from diced silicon to polyimide support ring is 889 μm (35.0 mils).
P.
Bond pad dimensions are 108.00 μm × 108.00 μm (4.25 mils × 4.25 mils).
Q. Center of bond pad to edge of die minimum (without scribe) = 107.80 μm (4.24 mils).
R. The nominal die thickness is 381 ± 50.8 μm (15 ± 2 mils).
S. The polyimide encapsulant thickness is approximately 304.8 μm (12 mils).
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
Table 2. SMJ320C40 Die Pad/TAB Lead Information : Rev. 5 (0,72 μm)
DIE SIDE #1
PITCH OF LEAD
(#, #) REFERENCES WHICH DIE
BOND PADS
C40 DIE BOND
PAD LOCATIONS
DIE/TAB BOND
PAD IDENTITY
X-COORDINATE OF THE
DIE BOND PAD (μm)
Y-COORDINATE OF THE
DIE BOND PAD (μm)
1
D31
D30
D29
D28
D27
D26
11368.44
11242.44
11116.44
10990.44
10864.44
10738.44
10612.44
10486.44
10360.44
10234.44
10108.44
9982.44
9856.44
9730.44
9604.44
9478.44
9352.44
9226.44
9100.44
8974.44
8848.44
8722.44
8596.44
8470.44
8344.44
8218.44
8092.44
7966.44
7840.44
7714.44
7588.44
7462.44
7336.44
7210.44
7084.44
6958.44
6832.44
6706.44
6550.02
6377.22
6225.12
6099.12
126.00 (1, 2)
126.00 (2, 3)
2
3
126.00 (3, 4)
4
126.00 (4, 5)
5
126.00 (5, 6)
6
126.00 (6, 7)
7
GDDV
126.00 (7, 8)
DD
8
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
126.00 (8, 9)
9
126.00 (9, 10)
126.00 (10, 11)
126.00 (11, 12)
126.00 (12, 13)
126.00 (13, 14)
126.00 (14, 15)
126.00 (15, 16)
126.00 (16, 17)
126.00 (17, 18)
126.00 (18, 19)
126.00 (19, 20)
126.00 (20, 21)
126.00 (21, 22)
126.00 (22, 23)
126.00 (23, 24)
126.00 (24, 25)
126.00 (25, 26)
126.00 (26, 27)
126.00 (27, 28)
126.00 (28, 29)
126.00 (29, 30)
126.00 (30, 31)
126.00 (31, 32)
126.00 (32, 33)
126.00 (33, 34)
126.00 (34, 35)
126.00 (35, 36)
126.00 (36, 37)
126.00 (37, 38)
156.42 (38, 39)
172.80 (39, 40)
152.10 (40, 41)
126.00 (41, 42)
126.00 (42, 43)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
CV
SS
SS
IV
GDDV
DD
VSS
D
-- 429.48
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
GDDV
D4
DD
D3
D2
D1
D0
CE1
RDY1
DV
CV
SS
SS
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
Table 2. SMJ320C40 Die Pad/TAB Lead Information : Rev. 5 (0,72 μm) (Continued)
DIE SIDE #1 (CONTINUED)
PITCH OF LEAD
(#, #) REFERENCES WHICH DIE
BOND PADS
C40 DIE BOND
PAD LOCATIONS
DIE/TAB BOND
PAD IDENTITY
X-COORDINATE OF THE
Y-COORDINATE OF THE
DIE BOND PAD
DIE BOND PAD
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
LOCK
5973.12
5847.12
5721.12
5564.70
5391.90
5219.10
5046.30
4894.20
4737.78
4564.98
4392.18
4240.08
4114.08
3988.08
3962.08
3736.08
3610.08
3484.08
3358.08
3232.08
3106.08
2980.08
2854.08
2726.64
2600.64
2474.64
2318.22
2143.98
1991.88
1835.46
1662.66
1510.56
1384.56
1258.56
1132.56
1006.56
880.56
126.00 (43, 44)
126.00 (44, 45)
156.42 (45, 46)
172.80 (46, 47)
172.80 (47, 48)
172.80 (48, 49)
152.10 (49, 50)
156.42 (50, 51)
172.80 (51, 52)
172.80 (52, 53)
151.10 (53, 54)
126.00 (54, 55)
126.00 (55, 56)
126.00 (56, 57)
126.00 (57, 58)
126.00 (58, 59)
126.00 (59, 60)
126.00 (60, 61)
126.00 (61, 62)
126.00 (62, 63)
126.00 (63, 64)
126.00 (64, 65)
127.44 (65, 66)
126.00 (66, 67)
126.00 (67, 68)
156.42 (68, 69)
174.24 (69, 70)
152.10 (70, 71)
156.42 (71, 72)
172.80 (72, 73)
172.80 (73, 74)
126.00 (74, 75)
126.00 (75, 76)
126.00 (76, 77)
126.00 (77, 78)
126.00 (78, 79)
126.00 (79, 80)
126.00 (80, 81)
V
DDL
V
SSL
CE0
RDY0
DE
TCK
TDO
TDI
TMS
TRST
EMU0
EMU1
DV
DV
SS
DD
PAGE1
R/W1
STRB1
STAT0
STAT1
-- 429.48
IV
SS
STAT2
STAT3
PAGE0
R/W0
STRB0
AE
RESETLOC 1
DV
DD
RESETLOC 0
RESET
CRDY5
CSTRB5
CACK5
CREQ5
CRDY4
CSTRB4
CACK4
754.56
CREQ4
628.56
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
Table 2. SMJ320C40 Die Pad/TAB Lead Information : Rev. 5 (0,72 μm) (Continued)
DIE SIDE #2
PITCH OF LEAD
(#, #) REFERENCES WHICH DIE
BOND PADS
C40 DIE BOND
PAD LOCATIONS
DIE/TAB BOND
PAD IDENTITY
X-COORDINATE OF THE
Y-COORDINATE OF THE
DIE BOND PAD
DIE BOND PAD
82
83
CV
DV
DV
0.00
1062.00 (82, 83)
126.00 (83, 84)
126.00 (84, 85)
126.00 (85, 86)
126.00 (86, 87)
126.00 (87, 88)
126.00 (88, 89)
126.00 (89, 90)
126.00 (90, 91)
126.00 (91, 92)
126.00 (92, 93)
126.00 (93, 94)
126.00 (94, 95)
126.00 (95, 96)
126.00 (96, 97)
126.00 (97, 98)
126.00 (98, 99)
126.00 (99, 100)
126.00 (100, 101)
126.00 (101, 102)
126.00 (102, 103)
126.00 (103, 104)
126.00 (104, 105)
126.00 (105, 106)
126.00 (106, 107)
126.00 (107, 108)
126.00 (108, 109)
126.00 (109, 110)
126.00 (110, 111)
126.00 (111, 112)
126.00 (112, 113)
126.00 (113, 114)
126.00 (114, 115)
126.00 (115, 116)
126.00 (116, 117)
126.00 (117, 118)
126.00 (118, 119)
126.00 (119, 120)
126.00 (120, 121)
126.00 (121, 122)
126.00 (122, 123)
126.00 (123, 124)
SS
SS
DD
1062.00
1188.00
1314.00
1440.00
1566.00
1692.00
1818.00
1944.00
2070.00
2196.00
2322.00
2448.00
2574.00
2700.00
2813.40
2952.00
3078.00
3204.00
3330.00
3456.00
3582.00
3708.00
3834.00
3960.00
4086.00
4212.00
4338.00
4464.00
4590.00
4716.00
4842.00
4968.00
5094.00
5220.00
5346.00
5472.00
5598.00
5724.00
5850.00
5976.00
6102.00
84
85
C5D7
C5D6
C5D5
C5D4
C5D3
C5D2
C5D1
C5D0
86
87
88
89
90
91
92
93
DV
DD
94
C4D7
C4D6
C4D5
C4D4
C4D3
C4D2
C4D1
C4D0
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
CV
DV
DV
SS
SS
DD
0.00
C3D7
C3D6
C3D5
C3D4
C3D3
C3D2
C3D1
C3D0
DV
DD
SS
IV
C2D7
C2D6
C2D5
C2D4
C2D3
C2D2
C2D1
C2D0
CV
SS
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
Table 2. SMJ320C40 Die Pad/TAB Lead Information : Rev. 5 (0,72 μm) (Continued)
DIE SIDE #2 (CONTINUED)
PITCH OF LEAD
(#, #) REFERENCES WHICH DIE
BOND PADS
C40 DIE BOND
PAD LOCATIONS
DIE/TAB BOND
PAD IDENTITY
X-COORDINATE OF THE
Y-COORDINATE OF THE
DIE BOND PAD
DIE BOND PAD
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
DV
DV
6228.00
6354.00
6480.00
6606.00
6732.00
6858.00
6984.00
7110.00
7236.00
7362.00
7488.00
7614.00
7740.00
7866.00
7992.00
8118.00
8244.00
8370.00
8496.00
8622.00
8748.00
8874.00
9000.00
9126.00
9252.00
9378.00
9504.00
9630.00
9756.00
9882.00
10008.00
10134.00
10260.00
10386.00
10512.00
10638.00
10764.00
10890.00
11016.00
126.00 (124, 125)
126.00 (125, 126)
126.00 (126, 127)
126.00 (127, 128)
126.00 (128, 129)
126.00 (129, 130)
126.00 (130, 131)
126.00 (131, 132)
126.00 (132, 133)
126.00 (133, 134)
126.00 (134, 135)
126.00 (135, 136)
126.00 (136, 137)
126.00 (137, 138)
126.00 (138, 139)
126.00 (139, 140)
126.00 (140, 141)
126.00 (141, 142)
126.00 (142, 143)
126.00 (143, 144)
126.00 (144, 145)
126.00 (145, 146)
126.00 (146, 147)
126.00 (147, 148)
126.00 (148, 149)
126.00 (149, 150)
126.00 (150, 151)
126.00 (151, 152)
126.00 (152, 153)
126.00 (153, 154)
126.00 (154, 155)
126.00 (155, 156)
126.00 (156, 157)
126.00 (157, 158)
126.00 (158, 159)
126.00 (159, 160)
126.00 (160, 161)
126.00 (161, 162)
SS
DD
CRDY3
CSTRB3
CACK3
CREQ3
V
DDL
V
SSL
CRDY2
CSTRB2
CACK2
CREQ2
DV
DD
CRDY1
CSTRB1
CACK1
CREQ1
CRDY0
CSTRB0
CACK0
CREQ0
0.00
CV
DV
SS
SS
SS
IV
DV
DD
C1D7
C1D6
C1D5
C1D4
C1D3
C1D2
C1D1
C1D0
DV
DD
C0D7
C0D6
C0D5
C0D4
C0D3
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
Table 2. SMJ320C40 Die Pad/TAB Lead Information : Rev. 5 (0,72 μm) (Continued)
DIE SIDE #3
PITCH OF LEAD
(#, #) REFERENCES WHICH DIE
BOND PADS
C40 DIE BOND
PAD LOCATIONS
DIE/TAB BOND
PAD IDENTITY
X-COORDINATE OF THE
Y-COORDINATE OF THE
DIE BOND PAD
DIE BOND PAD
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
C0D2
C0D1
C0D0
810.00
936.00
126.00 (163, 164)
126.00 (164, 165)
126.00 (165, 166)
126.00 (166, 167)
156.42 (167, 168)
152.46 (168, 169)
126.00 (169, 170)
126.00 (170, 171)
126.00 (171, 172)
126.00 (172, 173)
156.42 (173, 174)
152.10 (174, 175)
126.00 (175, 176)
126.00 (176, 177)
156.42 (177, 178)
172.80 (178, 179)
152.10 (179, 180)
126.00 (180, 181)
126.00 (181, 182)
126.00 (182, 183)
126.00 (183, 184)
156.42 (184, 185)
172.80 (185, 186)
172.80 (186, 187)
152.10 (187, 188)
126.00 (188, 189)
126.00 (189, 190)
126.00 (190, 191)
156.42 (191, 192)
152.10 (192, 193)
126.00 (193, 194)
126.00 (194, 195)
126.00 (195, 196)
126.00 (196, 197)
126.00 (197, 198)
127.44 (198, 199)
126.00 (199, 200)
126.00 (200, 201)
131.94 (201, 202)
171.58 (202, 203)
168.12 (203, 204)
126.00 (204, 205)
1062.00
1188.00
1314.00
1470.42
1622.88
1748.88
1874.88
2000.88
2126.88
2283.30
2435.40
2561.40
2687.40
2843.82
3016.62
3168.72
3294.72
3420.72
3546.72
3672.72
3829.14
4001.94
4174.74
4326.84
4452.84
4578.84
4704.84
4861.26
5013.36
5139.36
5265.36
5391.36
5517.36
5643.36
5770.80
5896.80
6022.80
6154.74
6326.28
6494.40
CV
DV
SS
DD
ROMEN
IIOF0
DV
SS
IIOF1
IIOF2
IIOF3
NMI
LSTRB0
LR/W0
LPAGE0
LRDY0
LCE0
LSTRB1
LR/W1
DV
CV
DD
SS
11779.74
LPAGE1
LRDY1
LCE1
LDE
TCLK0
TCLK1
H3
H1
LAE
IV
SS
LLOCK
LSTAT0
LSTAT1
LSTAT2
LSTAT3
IACK
V
DDL
V
SSL
X1
X2/CLKIN
CV
SS
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
Table 2. SMJ320C40 Die Pad/TAB Lead Information : Rev. 5 (0,72 μm) (Continued)
DIE SIDE #3 (CONTINUED)
PITCH OF LEAD
(#, #) REFERENCES WHICH DIE
BOND PADS
C40 DIE BOND
PAD LOCATIONS
DIE/TAB BOND
PAD IDENTITY
X-COORDINATE OF THE
Y-COORDINATE OF THE
DIE BOND PAD
DIE BOND PAD
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
DV
DV
6620.40
6746.40
6873.84
6999.84
7125.84
7251.84
7377.84
7503.84
7629.84
7755.84
7881.84
8007.84
8133.84
8259.84
8385.84
8511.84
8637.84
8763.84
8889.84
9015.84
9141.84
9267.84
9393.84
9519.84
9645.84
9771.84
9897.84
10023.84
10149.84
10275.84
10401.84
10527.84
10653.84
10779.84
10905.84
11031.84
11157.84
11283.84
11489.76
126.00 (205, 206)
127.44 (206, 207)
126.00 (207, 208)
126.00 (208, 209)
126.00 (209, 210)
126.00 (210, 211)
126.00 (211, 212)
126.00 (212, 213)
126.00 (213, 214)
126.00 (214, 215)
126.00 (215, 216)
126.00 (216, 217)
126.00 (217, 218)
126.00 (218, 219)
126.00 (219, 220)
126.00 (220, 221)
126.00 (221, 222)
126.00 (222, 223)
126.00 (223, 224)
126.00 (224, 225)
126.00 (225, 226)
126.00 (226, 227)
126.00 (227, 228)
126.00 (228, 229)
126.00 (229, 230)
126.00 (230, 231)
126.00 (231, 232)
126.00 (232, 233)
126.00 (233, 234)
126.00 (234, 235)
126.00 (235, 236)
126.00 (236, 237)
126.00 (237, 238)
126.00 (238, 239)
126.00 (239, 240)
126.00 (240, 241)
126.00 (241, 242)
205.92 (242, 243)
DD
SS
LA30
LA29
LA28
LA27
LADV
DD
LA26
LA25
LA24
LA23
LA22
LA21
LA20
LA19
LA18
LA17
LA16
LADV
DD
CV
DV
11779.74
SS
SS
LA15
LA14
LA13
LA12
LA11
LA10
LA9
LA8
LA7
LA6
LA5
LA4
LADV
DD
LA3
LA2
LA1
LA0
DV
SS
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
Table 2. SMJ320C40 Die Pad/TAB Lead Information : Rev. 5 (0,72 μm) (Continued)
DIE SIDE #4
PITCH OF LEAD
(#, #) REFERENCES WHICH DIE
BOND PADS
C40 DIE BOND
PAD LOCATIONS
DIE/TAB BOND
PAD IDENTITY
X-COORDINATE OF THE
Y-COORDINATE OF THE
DIE BOND PAD
DIE BOND PAD
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
CV
10953.72
10827.72
10701.72
10575.72
10449.72
10323.72
10197.72
10071.72
9945.72
9819.72
9693.72
9567.72
9441.72
9315.72
9189.72
9063.72
8937.72
8811.72
8685.72
8559.72
8433.72
8307.72
8181.72
8055.72
7929.72
7803.72
7677.72
7551.72
7425.72
7299.72
7173.72
7047.72
6921.72
6795.72
6669.72
6543.72
6417.72
6291.72
6165.72
6038.10
5912.10
5786.10
126.00 (244, 245)
126.00 (245, 246)
126.00 (246, 247)
126.00 (247, 248)
126.00 (248, 249)
126.00 (249, 250)
126.00 (250, 251)
126.00 (251, 252)
126.00 (252, 253)
126.00 (253, 254)
126.00 (254, 255)
126.00 (255, 256)
126.00 (256, 257)
126.00 (257, 258)
126.00 (258, 259)
126.00 (259, 260)
126.00 (260, 261)
126.00 (261, 262)
126.00 (262, 263)
126.00 (263, 264)
126.00 (264, 265)
126.00 (265, 266)
126.00 (266, 267)
126.00 (267, 268)
126.00 (268, 269)
126.00 (269, 270)
126.00 (270, 271)
126.00 (271, 272)
126.00 (272, 273)
126.00 (273, 274)
126.00 (274, 275)
126.00 (275, 276)
126.00 (276, 277)
126.00 (277, 278)
126.00 (278, 279)
126.00 (279, 280)
126.00 (280, 281)
126.00 (281, 282)
127.62 (282, 283)
126.00 (283, 284)
126.00 (284, 285)
126.00 (285, 286)
SS
LD31
LD30
LD29
LD28
LDDV
DD
LD27
LD26
LD25
LD24
LD23
LD22
LD21
LD20
LD19
LD18
LD17
LDDV
DD
CV
DV
SS
SS
SS
IV
11819.88
LD16
LD15
LD14
LD13
LD12
LD11
LD10
LD9
LD8
LD7
LD6
LD5
LDDV
DD
LD4
LD3
LD2
LD1
LD0
V
DDL
V
SSL
CV
SS
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
Table 2. SMJ320C40 Die Pad/TAB Lead Information : Rev. 5 (0,72 μm) (Continued)
DIE SIDE #4 (CONTINUED)
PITCH OF LEAD
(#, #) REFERENCES WHICH DIE
BOND PADS
C40 DIE BOND
PAD LOCATIONS
DIE/TAB BOND
PAD IDENTITY
X-COORDINATE OF THE
Y-COORDINATE OF THE
DIE BOND PAD
DIE BOND PAD
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
DV
5660.10
5534.10
5408.10
5282.10
5156.10
5030.10
4904.10
4778.10
4652.10
4526.10
4400.10
4274.10
4148.10
4022.10
3896.10
3770.10
3644.10
3518.10
3392.10
3266.10
3140.10
3014.10
2888.10
2762.10
2636.10
2510.10
2384.10
2258.10
2132.10
2006.10
1880.10
1754.10
1628.10
1502.10
1376.10
1250.10
1124.10
998.10
126.00 (286, 287)
126.00 (287, 288)
126.00 (288, 289)
126.00 (289, 290)
126.00 (290, 291)
126.00 (291, 292)
126.00 (292, 293)
126.00 (293, 294)
126.00 (294, 295)
126.00 (295, 296)
126.00 (296, 297)
126.00 (297, 298)
126.00 (298, 299)
126.00 (299, 300)
126.00 (300, 301)
126.00 (301, 302)
126.00 (302, 303)
126.00 (303, 304)
126.00 (304, 305)
126.00 (305, 306)
126.00 (306, 307)
126.00 (307, 308)
126.00 (308, 309)
126.00 (309, 310)
126.00 (310, 311)
126.00 (311, 312)
126.00 (312, 313)
126.00 (313, 314)
126.00 (314, 315)
126.00 (315, 316)
126.00 (316, 317)
126.00 (317, 318)
126.00 (318, 319)
126.00 (319, 320)
126.00 (320, 321)
126.00 (321, 322)
126.00 (322, 323)
558.00 (323, 324)
630.00 (324, 325)
SS
A30
A29
A28
GADV
DD
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
GADV
DD
CV
DV
SS
SS
A16
A15
A14
A13
A12
A11
A10
A9
11819.88
A8
A7
A6
A5
A4
GADV
A3
DD
A2
A1
A0
CV
DV
SS
SS
440.10
SUBS
-- 189.90
30
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
SMJ320C40 device nomenclature
SMJ
320
C
40
HFH
M
40
PREFIX:
SMJ
SM
=
=
MIL-PRF-38535
Standard Processing
SPEED RANGE:
40 = 40 MHz
50 = 50 MHz
60 = 60 MHz
DEVICE FAMILY:
320 SMJ320 DSP Family
=
TEMPERATURE RANGE:
M = --55°C to 125°C
S = --55°C to 100°C
TECHNOLOGY:
C
=
CMOS
PACKAGE TYPE:
GF
HFH
=
=
325-Pin Ceramic Staggered PGA
352-Lead Ceramic Quad Flat Pack
(nonconductive tie-bar)
DEVICE:
40
=
320C40
SMJ
320
C
40
TAB
M
40
/10
SOLDER DIP LEAD
FINISH
PREFIX:
SMJ
SM
TMP
=
=
=
MIL-PRF-38535
Standard Processing
Commercial Level
SPEED RANGE:
40 = 40 MHz
50 = 50 MHz
60 = 60 MHz
DEVICE FAMILY:
320 SMJ320 DSP Family
=
TEMPERATURE RANGE:
M = --55°C to 125°C
S = --55°C to 100°C
L = 0°C to 70°C
TECHNOLOGY:
C
=
CMOS
PACKAGE TYPE:
TAB
=
324-Pad JEDEC Standard TAB Tape
With Polyimide Overcoat
DEVICE:
40
=
320C40
31
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -- 0.3 V to 7 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -- 0.3 V to 7 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -- 0.3 V to 7 V
Operating case temperature range, TC (M version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -- 55°C to 125°C
(S version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -- 55°C to 100°C
(C version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -- 25°C to 85°C
(L version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -- 6 5 °C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions (see Note 2)
‡
MIN NOM
MAX
5.25
5.25
5.25
UNIT
SMJ320C40-40
4.75
4.75
4.75
5
5
5
0
SMJ320C40-50
SMJ320C40-60
V
V
Supply voltages (DV , etc.)
V
V
DD
SS
DD
Supply voltages (CV , etc.)
SS
X2/CLKIN
2.6
2.2
V
V
V
+ 0.3*
DD
DD
DD
§
CSTRBx, CRDYx , CREQx, CACKx
All other pins
+ 0.3*
+ 0.3*
0.8
V
V
High-level input voltage
V
IH
IL
2
Low-level input voltage
High-level output current
Low-level output current
-- 0.3*
V
I
I
-- 300
2
μA
mA
OH
OL
M version
S version
C version
L version
-- 5 5
-- 5 5
-- 2 5
0
125
100
85
T
C
Operating case temperature (see Note 3)
°C
70
‡
§
All nominal values are at V = 5 V, T (ambient-air temperature)= 25°C.
CRDYx is 2.6 V minimum for TAB package only.
DD
A
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
NOTES: 2. All input and output voltage levels are TTL-compatible.
3.
T
C
MAX at maximum rated operating conditions at any point on case. T MIN at initial (time zero) power-up.
C
32
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
electrical characteristics over specified case temperature range (see Note 2)
†
PARAMETER
High-level output voltage
Low-level output voltage
Three-state current
Input current
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
I
V
V
V
= MIN, I = MAX
2.4
3
OH
OL
DD
DD
DD
OH
= MIN, I = MAX
0.3
0.6
20
V
OL
= MAX
-- 2 0
-- 1 0
μA
μA
μA
μA
μA
Z
I
I
I
I
V = V to V
I DD
10
I
SS
Input current (TDI, TCK, and TMS) V = V to V (See Note 4)
--400
-- 2 0
-- 5 0
20
IPU
IPD
IC
I
SS
DD
Input current (TRST)
V = V to V (See Note 4)
400
50
I
SS
DD
DD
Input current, X2/CLKIN only
V = V to V
I
SS
320C40-40
320C40-50
350
350
850
V
= MAX, T = 25°C,
A
DD
I
Supply current
mA
CC
f = MAX (See Note 5)
x
320C40-60
950
15*
15*
C
C
Input capacitance
Output capacitance
pF
pF
I
O
†
All nominal values are at V = 5 V, T = 25°C.
DD
A
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
NOTES: 2. All input and output voltage levels are TTL-compatible.
4. Pins with internal pullup devices: TDI, TCK, TMS. Pin with internal pulldown device: TRST.
5. f is the input clock frequency. The maximum value (MAX) for the 320C40-40, 320C40-50, and 320C40-60 is 40, 50, and 60 MHz,
x
respectively.
PARAMETER MEASUREMENT INFORMATION
I
OL
Output
Under
Test
Tester Pin
Electronics
V
Load
C
T
I
OH
Where: IOL
IOH
= 2 mA (all outputs)
= 300 μA (all outputs)
VLoad = 2.15 V
CT
= 80 pF typical load circuit capacitance.
Figure 5. Test Load Circuit
33
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
signal transition levels
TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V.
Output transition times are specified as follows:
For a high-to-low transition on a TTL-compatible output signal, the level at which the output is said to be no
longer high is 2 V, and the level at which the output is said to be low is 1 V. For a low-to-high transition, the level
at which the output is said to be no longer low is 1 V, and the level at which the output is said to be high is 2 V.
See Figure 6.
2.4 V
2 V
1 V
0.6 V
Figure 6. TTL-Level Outputs
Transition times for TTL-compatible inputs are specified as follows:
For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 2 V, and
the level at which the input is said to be low is 0.8 V. For a low-to-high transition on an input signal, the level at
which the input is said to be no longer low is 0.8 V, and the level at which the input is said to be high is 2 V. See
Figure 7.
†
2.4 V
2 V
0.8 V
0.4 V
X2
CLKIN
†
Exceptions:
V
= 3.12 V and CSTRBx, CRDYx, CREQx and CACKx V = 2.64 V.
IH
IH
Figure 7. TTL-Level Inputs
Timing measurements, excluding TR, TF, and T disable (output going to high impedance or an I/O output
becoming an input), are referenced from an input trip point of 1.5 V to an output trip point of 2 V. Timing
measurements from H1 and H3 are referenced from 2 V on the rising or falling edges. TR and TF times are
referenced from 20% below VOH minimum to 20% above VOL maximum. T disable times are referenced from
an input trip point of 1.5 V to 0.1 V below VOH (TPHZ) or above VOL (TPLZ). The IOL and IOH load current can
be increased to reduce the RC time constant during TPHZ and TPLZ testing.
34
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
timing parameter symbology
Timing parameter symbols used herein were created in accordance with JEDEC Standard 100-A.To shorten
the symbols, pin names that have both global and local applications generally are represented with (L)
immediately preceding the basic signal name [for example, (L)RDY represents both the global term RDY and
the local term LRDY]. Other pin names and related terminology have been abbreviated as follows, unless
otherwise noted:
A
(L)A30--(L)A0 or (L)Ax
LAE, AE, or (L)AE
H
H1/H3
AE
IACK
IIOF
LOCK
(L)RDY
P
IACK
ASYNCH
BYTE
CA
asynchronous reset signals
byte transfer
IIOF(3--0) or IIOFx
LLOCK, LOCK, or (L)LOCK
(L)RDY0, (L)RDY1, or (L)RDYx
CACK(0--5) or CACKx
C(0--5)D7--C(0--5)D0 or CxDx
(L)CE0, (L)CE1, or (L)CEx
X2/CLKIN
CD
t
c(H)
CE
PAGE
RESET
RW
(L)PAGE0, (L)PAGE1, or (L)PAGEx
CI
RESET
COMM
CONTROL
CRDY
CRQ
CS
asynchronous reset signals
control signals
(L)R/W0, (L)R/W1, or (L)R/Wx
S
(L)STRB0, (L)STRB1, or (L)STRBx
CRDY(0--5) or CRDYx
CREQ(0--5) or CREQx
CSTRB(0--5) or CSTRBx
(L)D31--(L)D0 or (L)Dx
LDE, DE, or (L)DE
ST
(L)STAT3--(L)STAT0 or (L)STATx
TCK
TDO
TMS
WORD
TCK
TDO
D
TMS/TDI
word transfer
DE
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
timing parameters for X2/CLKIN, H1, H3 (see Figure 8 and Figure 9)
320C40-40
320C40-50
320C40-60
NO.
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
1
2
3
4
5
6
7
8
9
t
t
t
t
t
t
t
t
t
Fall time, CLKIN
5*
5*
5*
ns
ns
ns
ns
ns
ns
ns
ns
ns
f(CI)
Pulse duration, CLKIN low, t
= min
c(CI)
8.5
8.5
7
7
5
5
w(CIL)
w(CIH)
r(CI)
Pulse duration, CLKIN high, t
Rise time, CLKIN
= min
c(CI)
5*
242.5
3*
5*
242.5
3*
5*
242.5
3*
Cycle time, CLKIN
25
20
16.67
c(CI)
f(H)
Fall time, H1/H3
Pulse duration, H1/H3 low
Pulse duration, H1/H3 high
Rise time, H1/H3
t
t
-- 6
-- 6
t
t
+6
+6
4*
t
t
-- 6
-- 6
t
t
+6
+6
4*
t
t
-- 6
-- 6
t
t
+6
+6
4*
w(HL)
w(HH)
r(H)
c(Cl)
c(Cl)
c(Cl)
c(Cl)
c(Cl)
c(Cl)
c(Cl)
c(Cl)
c(Cl)
c(Cl)
c(Cl)
c(Cl)
Delay time, from H1 low to H3 high or
from H3 low to H1 high
9.1
t
-- 1
50
4
-- 1
40
4
-- 1
4
ns
ns
d(HL-HH)
10
t
Cycle time, H1/H3
485
485
33.3
485
c(H)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
5
4
1
X2/CLKIN
3
2
Figure 8. X2/CLKIN Timing
10
6
9
H1
H3
8
7
9.1
9.1
8
9
6
7
10
Figure 9. H1/H3 Timings
36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
timing parameters for a memory read/write [(L)STRBx = 0] (see Note 6, Figure 10, and Figure 11)
320C40-40
320C40-50
320C40-60
NO.
UNIT
MIN
0*
0*
0*
0*
15
0
MAX
MIN
0*
0*
0*
0*
10
0
MAX
MIN
0*
0*
0*
0*
9
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, H1 low to (L)STRBx low
Delay time, H1 low to (L)STRBx high
Delay time, H1 high to (L)R/Wx low
Delay time, H1 low to (L)Ax valid
10
10
9
10
10
9
8
8
8
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(H1L-SL)
d(H1L-SH)
3
d(H1H-RWL)
d(H1L-A)
4
10
9
5
Setup time, (L)Dx valid before H1 low (read)
Hold time, (L)Dx after H1 low (read)
Setup time, (L)RDYx valid before H1 low
Hold time, (L)RDYx after H1 low
su(D-H1L)R
h(H1L-D)R
6
0
7
25
0
20
0
18*
0
su[(L)RDY-H1L]
h[H1L-(L)RDY]
d(H1L-ST)
8
8.1
9
Delay time, H1 low to (L)STAT3--(L)STAT0 valid
Delay time, H1 high to (L)R/Wx high (write)
Valid time, (L)Dx after H1 low (write)
Hold time, (L)Dx after H1 high (write)
10
9
10
9
8
8
0*
0
d(H1H-RWH)W
v(H1L-D)W
h(H1H-D)W
10
11
16
16
13
0
0
Delay time, H1 high to address valid on back-to-back
write cycles
12
t
13
13
8
ns
d(H1H-A)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
NOTE 6: For consecutive reads, (L)R/Wx stays high and (L)STRBx stays low.
H3
H1
1
4
2
(L)STRBx
(L)R/Wx
5
3
(L)Ax
(L)Dx
6
8
7
(L)RDYx
8.1
(L)STAT3--(L)STAT0
Figure 10. Memory-Read-Cycle Timing [(L)STRBx = 0]
37
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
H3
H1
(L)STRBx
(L)R/Wx
(L)Ax
1
2
3
9
12
4
10
11
(L)Dx
(L)RDYx
8
7
(L)STAT3--(L)STAT0
Figure 11. Memory-Write-Cycle Timing [(L)STRBx = 0]
38
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
(L)DE, (L)AE, and (L)CEx enable timings (see Figure 12)
320C40-40
320C40-60
320C40-50
UNIT
NO.
MIN* MAX MIN* MAX
1
2
3
4
5
6
t
t
t
t
t
t
Delay time, (L)DE high to (L)D0--(L)D31 in the high-impedance state
Delay time, (L)DE low to (L)D0--(L)D31 valid
0
0
0
0
0
0
15*
22
0
0
0
0
0
0
15*
16
ns
ns
ns
ns
ns
ns
d(DEH-DZ)
d(DEL-DV)
d(AEH-AZ)
d(AEL-AV)
Delay time, (L)AE high to (L)A0--(L)A30 in the high-impedance state
Delay time, (L)AE low to (L)A0--(L)A30 valid
15*
21
15*
16
Delay time, (L)CEx high to (L)R/W0, (L)R/W1 in the high-impedance state
Delay time, (L)CEx low to (L)R/W0, (L)R/W1 valid
15*
21
15*
16
d(CEH-RWZ)
d(CEL-RWV)
Delay time, (L)CEx high to (L)STRB0, (L)STRB1 in the high-impedance
state
7
8
t
t
t
t
0
0
0
0
15*
21
0
0
0
0
15*
16
ns
ns
ns
ns
d(CEH-SZ)
Delay time, (L)CEx low to (L)STRB0, (L)STRB1 valid
d(CEL-SV)
Delay time, (L)CEx high to (L)PAGE0, (L)PAGE1 in the high-impedance
state
9
15*
21
15*
16
d(CEH-PAGEZ)
10
Delay time, (L)CEx low to (L)PAGE0, (L)PAGE1 valid
d(CEL-PAGEV)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
(L)DE
2
1
Hi-Z
(L)D31--(L)D0
(L)AE
4
3
(L)A30--(L)A0
Hi-Z
(L)CE0, (L)CE1
6
5
7
9
Hi-Z
Hi-Z
(L)R/W0, (L)R/W1
(L)STRB0, (L)STRB1
(L)PAGE0, (L)PAGE1
8
10
Hi-Z
Figure 12. (L)DE, (L)AE, and (L)CEx Enable Timings
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
timing parameters for (L)LOCK when executing LDFI or LDII (see Figure 13)
320C40-40
MIN MAX
11
320C40-50
MIN MAX
320C40-60
MIN MAX
NO.
UNIT
1
t
Delay time, H1 low to (L)LOCK low
9
8
ns
d(H1L-LOCKL)
LDFI or LDII
External Access
H3
H1
(L)STRBx
(L)R/Wx
(L)Ax
(L)Dx
(L)RDYx
(L)LOCK
1
Figure 13. Timing for (L)LOCK When Executing LDFI or LDII
40
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
timing parameters for (L)LOCK when executing STFI or STII (see Figure 14)
320C40-40
MIN MAX
11
320C40-50
MIN MAX
320C40-60
MIN MAX
NO.
PARAMETER
UNIT
1
t
Delay time, H1 low to (L)LOCK high
9
8
ns
d(H1L-LOCKH)
STFI or STII
External Access
H3
H1
(L)STRBx
(L)R/Wx
(L)Ax
(L)Dx
(L)RDYx
(L)LOCK
1
Figure 14. Timing for (L)LOCK When Executing STFI or STII
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
timing parameters for (L)LOCK when executing SIGI (see Figure 15)
320C40-40
320C40-50
MIN MAX
320C40-60
MIN MAX
NO.
UNIT
MIN
MAX
11
1
2
t
Delay time, H1 low to (L)LOCK low
Delay time, H1 low to (L)LOCK high
9
9
8
8
ns
ns
d(H1L-LOCKL)
t
11
d(H1L-LOCKH)
H3
H1
1
2
(L)LOCK
(L)R/Wx
(L)Ax
(L)Dx
(L)RDYx
(L)STAT3--(L)STAT0
Figure 15. Timing for (L)LOCK When Executing SIGI
42
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
timing parameters for (L)PAGE0, (L)PAGE1 during memory access to a different page
(see Figure 16)
320C40-40
320C40-50
320C40-60
NO.
UNIT
MIN
0
MAX
MIN
0
MAX
1
2
t
t
Delay time, H1 low to (L)PAGEx high for access to different page
Delay time, H1 low to (L)PAGEx low for access to different page
10
10
8
8
ns
ns
d(H1L-PAGEH)
d(H1L-PAGEL)
0
0
H1
(L)R/Wx
(L)STRBx
(L)RDYx
1
2
1
2
(L)PAGEx
(L)Dx
(L)Ax
(L)STAT3--(L)STAT0
(L)STRB1 write to a different page
(L)STRB1 read from a different page
Figure 16. (L)PAGE0, (L)PAGE1 Timing Cycle, Memory Access to a Different Page
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
timing parameters for loading IIF register (IIOFx pins) when configured as an output pin
(see Figure 17)
320C40-40
320C40-50
MIN MAX
16
320C40-60
MIN MAX
14
NO.
UNIT
MIN
MAX
18
1
t
Valid time, IIOFx after H1 low
ns
v(H1L-IIOF)
Fetch Load
Instruction
Decode
Read
Execute
H3
H1
FLAG Bit
1 or 0
1
IIOFx pins
Figure 17. Timing for Loading IIF Register (IIOFx Pins) When Configured as an Output Pin
44
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
timing parameters of IIOFx changing from output to input mode (see Figure 18)
320C40-40
320C40-50
320C40-60
NO.
UNIT
MIN
MAX
14*
1
2
3
t
t
t
Hold time, IIOFx after H1 low
Setup time, IIOFx before H1 low
Hold time, IIOFx after H1 low
ns
ns
ns
h(H1L-IIOF)
su(IIOF)
11
0
h(IIOF)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
Buffers Go
Execute
from Output
Load of IIOF
to Input
Synchronizer
Delay
Value on Pin
Seen In IIOF
H3
H1
2
3
TYPE Bit
1
Output
IIOFx pins
FLAG Bit
Data
Sampled
Data
Seen
Figure 18. Change of IIOFx From Output to Input Mode
45
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
timing parameters of IIOFx changing from input to output mode (see Figure 19)
320C40-40
320C40-50
320C40-60
NO.
UNIT
MIN
MAX
MIN
MAX
14
1
t
Delay time, H1 low to IIOFx switching from input to output
16
ns
d(H1L-IFIO)
Execution of
Load of IIOF
H3
H1
TYPE Bit
1
IIOFx pins
Figure 19. Change of IIOFx From Input to Output Mode
timing parameters for RESET (see Figure 20)
320C40-40
320C40-50
320C40-60
NO.
UNIT
MIN
11
2
MAX MIN
MAX MIN MAX
1
t
t
t
Setup time, RESET before CLKIN low
Delay time, CLKIN high to H1 high
Delay time, CLKIN high to H1 low
t
11
2
t
11
2
t
ns
ns
ns
su(RESET-CIL)
d(CIH-H1H)
d(CIH-H1L)
c(CI)
12
c(Cl)*
c(Cl)*
2.1
2.2
10
10
2
12
2
10
2
10
Setup time, RESET high before H1 low and
after ten H1 clock cycles
3
t
13
13
13
ns
su(RESETH-H1L)
4.1
4.2
t
t
Delay time, CLKIN high to H3 low
Delay time, CLKIN high to H3 high
2
2
12
12
2
2
10
10
2
2
10
11
ns
ns
d(CIH-H3L)
d(CIH-H3H)
Disable time, H1 high to (L)Dx in
high-impedance state
5
6
t
t
13*
9*
13*
9*
13*
9*
ns
ns
dis(H1H-DZ)
dis(H3H-AZ)
Disable time, H3 high to (L)Ax in
high-impedance state
Delay time, H3 high to control signals high
[low for (L)PAGEx]
7
8
9
t
t
t
9*
9*
9*
9*
9*
9*
ns
ns
ns
d(H3H-CONTROLH)
d(H1H-IACKH)
Delay time, H1 high to IACK high
Disable time, RESET low to asynchronous
reset signals in the high-impedance state
21*
21*
21*
dis(RESETL-ASYNCHZ)
Delay time, RESET high to asynchronous reset
signals high
10
t
15*
15*
15*
ns
d(RESETH-COMMH)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
46
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
i g S n a l s
C o n t r o l
•
47
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
timing parameters for IIOF3--IIOF0 interrupt response [P = tc(H)] (see Figure 21, Note 7, and
Note 8)
’320C40-40
’320C40-60
’320C40-50
NO.
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
1
2
t
t
Setup time, IIOF3--IIOF0 before H1 low
11
11*
ns
ns
su(IIOF-H1L)
w(IIOF)
Interrupt pulse duration to ensure one interrupt seen
(see Note 9)
P
1.5P < 2P*
P
1.5P < 2P*
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
NOTES: 7. IIOFx is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact
sequence shown occurs; otherwise, an additional delay of one clock cycle can occur.
8. Edge-triggered interrupts require a setup of time (1) and a minimum duration of P. No maximum duration limit exists.
9. Level-triggered interrupts require interrupt pulse duration of at least 1P wide (P = one H1 period) to ensure that the interrupt is seen.
It must be less than 2P wide to ensure that it is responded to only once. Recommended pulse duration is 1.5P.
Fetch First
Instruction of
Service
Reset or
Interrupt
Vector Read
Routine
H3
H1
1 (See Note A)
2
IIOF3--IIOF0
Pins
First
Instruction
Address
IIOF3--IIOF0
Flag
ADDRESS
Vector
Address
Data
NOTE A: The ’C40 can accept an interrupt from the same source every two H1 clock cycles.
Figure 21. IIOF3--IIOF0 Interrupt Response Timing [P=tc(H)
]
48
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
timing parameters for IACK (see Note 10 and Figure 22)
’320C40-40
’320C40-60
’320C40-50
UNIT
NO.
MIN
MAX
MIN
MAX
1
2
t
t
Delay time, H1 high to IACK low
9
7
ns
ns
d(H1H-IACKL)
d(H1L-IACKH)
Delay time, H1 low to IACK high during first cycle of IACK instruction
data read
9
7
NOTE 10: The IACK output is active for the entire duration of the bus cycle and, therefore, is extended if the bus cycle utilizes wait states.
Fetch IACK
Instruction
Decode IACK
Instruction
IACK Data
Read
Execute IACK
Instruction
H3
H1
1
2
IACK
ADDRESS
DATA
Figure 22. IACK Timing
49
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
communication-port word-transfer cycle timing [P=tc(H)] (see Note 11 and Figure 23)
†
†
†
’320C40-40
’320C40-50
’320C40-60
NO.
UNIT
MIN
MAX
‡
1
2
t
t
Cycle time, word transfer (4 bytes = 1 word)
1.5P+7
1.5P+7
2.5P+17
2.5P+28
ns
ns
c(WORD)
d(CRDYL-CSL)W*
Delay time, CRDYx low to CSTRBx low between back-to-back write cycles
†
‡
For these timing values, it is assumed that the SMJ320C40 that is to receive data is ready to receive data.
max = 2.5P + 28 ns + 4(¥) + 3(© + ¨ + £), where boxed numbers refer to the max values for corresponding parameters in the
t
c(WORD)
communication-port byte timing table on the next page (for example, ¥ means the value under max for parameter 6 in the table ---- a value of
10 ns). This timing assumes that two ’C40s are connected.
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
NOTE 11: These timings apply only to two communicating ’C4xs. When a non-’C4x device communicates with a ’C40, timings can be longer. No
restriction exists in this case on how slow the transfer could be except when using early silicon (’C40 P6 1.x or 2.x). See the CSTRB
width restriction in Section 8.9.1 of the TMS320C4x User’s Guide (literature number SPRU063).
CREQx
CACKx
1
CSTRBx
CxD7--CxD0
CRDYx
B0
B1
B2
B3
Undef.
2
B0 (see Note B)
= when signal is an input (clear = when signal is an output)
NOTES: A. For correct operation during token exchange, the two communicating SMJ320C40s must have CLKIN frequencies within a factor
of 2 of each other (in other words, at most, one of the SMJ320C40s can be twice as fast as the other).
B. Begins byte 0 of the next word
Figure 23. Communication-Port Word-Transfer-Cycle Timing [P=tc(H)
]
50
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
communication-port byte timing parameters (write and read) (see Note 12 and Figure 24)
’320C40-40
’320C40-50
’320C40-60
NO.
UNIT
MIN
2
MAX
1
2
3
4
5
6
7
8
9
t
t
t
t
t
t
t
t
t
Setup time, CxDx data valid before CSTRBx low (write)
Delay time, CRDYx low to CSTRBx high (write)
Hold time, CxDx after CRDYx low (write)
ns
ns
ns
ns
ns
ns
ns
ns
ns
su(CD-CSL)W
0*
1
12
d(CRDYL-CSH)W
h(CRDYL-CD)W
d(CRDYH-CSL)W
Delay time, CRDYx high to CSTRBx low for subsequent bytes (write)
Cycle time, byte transfer
0*
12
44
10
†
c(BYTE)
Delay time, CSTRBx low to CRDYx low (read)
Setup time, CxDx valid after CSTRBx high (read)
Hold time, CxDx valid after CRDYx low (read)
Delay time, CSTRBx high to CRDYx high (read)
0*
0
d(CSL-CRDYL)R
su(CSH-CD)R
2
h(CRDYL-CD)R
d(CSH-CRDYH)R
0*
10
†
t
max = (© + £ + ¥ + ¨) where boxed numbers refer to the max values for corresponding parameters in the above table (for example,
c(BYTE)
¥ means the value under max for parameter 6 in the table — a value of 10 ns). This assumes that two ’C40s are connected.
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
NOTE 12: Communication port timing does not include line length delay.
CREQx
CACKx
5
5
7
CSTRBx
1
2
9
CxDx
Valid Data
Valid
8
3
6
CRDYx
4
(a) WRITE TIMING
(b) READ TIMING
= when signal is an input (clear = when signal is an output)
Figure 24. Communication-Port Byte Timing (Write and Read)
51
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
†
timing parameters for communication-token transfer sequence, input to an output port [P = tc(H)
]
(see Figure 25)
’320C40-40*
’320C40-50*
’320C40-60
MIN MAX
0.5P+ 6 1.5P+ 22
NO.
UNIT
*
†
1
t
t
t
t
Delay time, CACKx low to CSTRBx change from input to a high-level output
ns
ns
ns
ns
d(CAL-CS)T
Delay time, CACKx low to start of CREQx going high for token-request
acknowledge
†
2
P + 5
2P + 26
d(CAL-CRQH)T
d(CRQH-CRQ)T
d(CRQH-CA)T
3
4
Delay time, start of CREQx going high to CREQx change from output to an input 0.5P -- 5 0.5P+ 13
Delay time, start of CREQx going high to CACKx change from an input to an
0.5P -- 5 0.5P+13
output level high
Delay time, start of CREQx going high to CxD7--CxD0 change from inputs
driven to outputs driven
4.1
4.2
t
t
0.5P -- 5 0.5P+13
ns
ns
d(CRQH-CD)T
Delay time, start of CREQx going high to CRDYx change from an output to an
input
0.5P -- 5 0.5P+13
1.5P -- 8 1.5P+ 9
3.5P+12 5.5P+ 48
d(CRQH-CRDY)T
Delay time, start of CREQx going high to CSTRBx low for start of word transfer
out
5
6
t
t
ns
ns
d(CRQH-CSL)T
d(CRDYL-CSL)T
Delay time, CRDYx low at end of word input to CSTRBx low for word output
†
These timing parameters result from synchronizer delays and are referenced from the falling edge of H1. The inputs (that cause the output-signal
pins to change values) are sampled on H1 falling. The minimum delay occurs when the input condition occurs just before H1 falling, and the
maximum delay occurs when the input condition occurs just after H1 falling.
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
3
CREQx
2
4
CACKx
5
1
CSTRBx
4.1
4.2
Valid Data Out
CxD7--CxD0
CRDYx
6
= when signal is an input (clear = when signal is an output)
NOTE A: Before the token exchange, CREQx and CRDYx are output signals asserted by the SMJ320C40 that is receiving data. CACKx,
CSTRBx, and CxD7--CxD0 are input signals asserted by the device sending data to the ’C40; these are asynchronous with respect to
the H1 clock of the receiving SMJ320C40. After token exchange, CACKx, CSTRBx, and CxD7--CxD0 become output signals, and
CREQx and CRDYx become inputs.
Figure 25. Communication-Token Transfer Sequence, Input to an Output Port [P=tc(H)
]
52
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
†
timing parameters for communication-token transfer sequence, output to an input port [P = tc(H)
]
(see Figure 26)
’320C40-40*
’320C40-50
’320C40-60*
*
NO.
UNIT
MIN
MAX
MIN
MAX
Delay time, CREQx low to start of CACKx going low for
token-request acknowledge
†
1
t
t
t
t
t
t
t
t
P+5
2P+26
P+5
2P+22
2P+27
0.5P+8
0.5P+8
22
ns
ns
ns
ns
ns
ns
ns
ns
d(CRQL-CAL)T
d(CRDYL-CAL)T
d(CAL-CD)I
Delay time, start of CRDYx low at end of word transfer out to
start of CACKx going low
†
2
P+6
2P+27
P+6
Delay time, start of CACKx going low to CxD7--CxD0 change
from outputs to inputs
3
4
0.5P--8
0.5P+8 0.5P--8
0.5P+8 0.5P--8
Delay time, start of CACKx going low to CRDYx change from
an input to output, high level
0.5P--8
d(CAL-CRDY)T
d(CRQH-CRQ)T
d(CRQH-CA)T
d(CRQH-CS)T
d(CRQH-CRQL)T
Delay time, CREQx high to CREQx change from an input to
output, high level
†
5
4
4
22
22
4
4
Delay time, start of CREQx high to CACKx change from
output to an input
†
6
22
Delay time, start of CREQx high to CSTRBx change from
output to an input
†
7
4
22
4
22
Delay time, CREQx high to CREQx low for the next token
request
†
8
P--4
2P+8
P--4
2P+8
†
These timing parameters result from synchronizer delays and are referenced from the falling edge of H1. The inputs (that cause the output-signal
pins to change values) are sampled on H1 falling. The minimum delay occurs when the input condition occurs just before H1 falling, and the
maximum delay occurs when the input condition occurs just after H1 falling.
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
53
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
8
CREQx
1
5
6
CACKx
CSTRBx
3
7
CxD7--CxD0
CRDYx
Valid data
Valid data
4
2
= when signal is an input (clear = when signal is an output)
NOTE A: Before the token exchange, CACKx, CSTRBx, and CxD7--CxD0 are asserted by the ’C40 sending data. CREQx and CRDYx are input
signals asserted by the ’C40 receiving data and are asynchronous with respect to the H1 clock of the sending ’C40. After token
exchange, CREQx and CRDYx become outputs, and CSTRBx, CACKx, and CxD7--CxD0 become inputs.
Figure 26. Communication-Token Transfer Sequence, Output to an Input Port [P=tc(H)]
54
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
timing parameters for timer pin (see Note 13 and Figure 27)
’320C40-40
’320C40-50
’320C40-60
NO.
UNIT
MIN MAX
1
2
3
t
t
t
Setup time, TCLK before H1 low
Hold time, TCLK after H1 low
10
0
ns
ns
ns
su(TCLK-H1L)
h(H1L-TCLK)
d(H1H-TCLK)
Delay time, TCLK valid after H1 high
13
NOTE 13: Period and polarity of valid logic level are specified by contents of internal control registers.
H3
H1
2
3
1
3
Peripheral Pin
(TCLK)
Figure 27. Timer Pin Timing Cycle
timing for IEEE 1149.1 test-access port (see Figure 28)
’320C40-40
’320C40-50
’320C40-60
NO.
UNIT
MIN
10
5
MAX
1
2
3
t
t
t
Setup time, TMS/TDI before TCK high
Hold time, TMS/TDI after TCK high
Delay time, TCK low to TDO valid
ns
ns
ns
su(TMS-TCKH)
h(TCKH-TMS)
d(TCKL-TDOV)
0
15
TCK
1
TMS/TDI
TDO
3
2
Figure 28. JTAG Emulation Timings
55
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
PRODUCT ORDERING INFORMATION
SMJ320C40 standard package ordering information
TEMPERATURE
RANGE
OPERATING
FREQUENCY
PROCESSING
LEVEL
DEVICE
PACKAGE TYPE
SMJ320C40GFM40
SM320C40GFM40
SMJ320C40GFM50
SM320C40GFM50
SMJ320C40HFHM40
SM320C40HFHM40
SMJ320C40HFHM50
SM320C40HFHM50
SMJ320C40GFS60
SM320C40GFS60
SMJ320C40HFHS60
SM320C40HFHS60
-- 5 5 °C to 125°C
-- 5 5 °C to 125°C
-- 5 5 °C to 125°C
-- 5 5 °C to 125°C
-- 5 5 °C to 125°C
-- 5 5 °C to 125°C
-- 5 5 °C to 125°C
-- 5 5 °C to 125°C
-- 5 5 °C to 100°C
-- 5 5 °C to 100°C
-- 5 5 °C to 100°C
-- 5 5 °C to 100°C
40 MHz
40 MHz
50 MHz
50 MHz
40 MHz
40 MHz
50 MHz
50 MHz
60 MHz
60 MHz
60 MHz
60 MHz
Ceramic 325-pin staggered PGA (GF)
Ceramic 325-pin staggered PGA (GF)
Ceramic 325-pin staggered PGA
Ceramic 325-pin staggered PGA
Ceramic 352-pin quad flatpack (HFH)
Ceramic 352-pin quad flatpack (HFH)
Ceramic 352-pin quad flatpack
Ceramic 352-pin quad flatpack
Ceramic 325-pin staggered PGA
Ceramic 325-pin staggered PGA
Ceramic 352-pin quad flatpack
Ceramic 352-pin quad flatpack
QML
Standard
QML
Standard
QML
Standard
QML
Standard
QML
Standard
QML
Standard
SMJ320C40 TAB ordering information†
TEMPERATURE
RANGE
OPERATING
FREQUENCY
PROCESSING
LEVEL
DEVICE
PACKAGE TYPE
SMJ320C40TABM40/10
SM320C40TABM40/10
SMJ320C40TABM50/10
SM320C40TABM50/10
SM320C40TABS50/10
-- 5 5 °C to 125°C
-- 5 5 °C to 125°C
-- 5 5 °C to 125°C
-- 5 5 °C to 125°C
-- 5 5 °C to 100°C
40 MHz
325 ILB/OLB TAB tape (encapsulated)
325 ILB/OLB TAB tape (encapsulated)
325 ILB/OLB TAB tape (encapsulated)
325 ILB/OLB TAB tape (encapsulated)
325 ILB/OLB TAB tape (encapsulated)
QML
40 MHz
Standard
QML
50 MHz
50 MHz
Standard
Standard
50 MHz
Commercial
(No Burn-In)
TMP320C40TABL50/10
SM320C40TABC50/10
0°C to 70°C
50 MHz
50 MHz
325 ILB/OLB TAB tape (encapsulated)
325 ILB/OLB TAB tape (encapsulated)
Commercial
(No Burn-In)
-- 2 5 °C to 85°C
SMJ320C40TABS60/10
SM320C40TABS60/10
-- 5 5 °C to 100°C
-- 5 5 °C to 100°C
60 MHz
60 MHz
325 ILB/OLB TAB tape (encapsulated)
325 ILB/OLB TAB tape (encapsulated)
QML
Standard
Commercial
(No Burn-In)
TMP320C40TABL60/10
0°C to 70°C
60 MHz
325 ILB/OLB TAB tape (encapsulated)
†
/10 indicates solder-dip TAB lead frame.
56
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
MECHANICAL DATA
GF (S-CPGA-P325)
CERAMIC PIN GRID ARRAY
1.717 (43,61)
1.683 (42,75)
1.879 (47,73)
1.841 (46,76)
TYP
SQ
0.100 (2,54)
AR
AN
AL
AJ
AG
AE
AC
AA
W
U
R
N
L
J
G
E
C
A
1
3
5
7
9
11 13 15 17 19 21 23 25 27 29 31 33 35
0.050 (1,27)
0.048 (1,22) DIA 4 Places
0.190 (4,83)
0.170 (4,32)
0.080 (2,03) TYP
0.050 (1,27) TYP
0.060 (1,52)
0.040 (1,02)
0.020 (0,51)
0.016 (0,41)
0.150 (3,81)
TYP
0.026 (0,660)
0.006 (0,152)
0.165 (4,19)
0.120 (3,05)
0.200 (5,08)
0.145 (3,68)
DETAIL A
4040035-2/E 03/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
Thermal Resistance
Characteristics
C. Index mark can appear on top or bottom, depending on package vendor.
D. Pins are located within 0.010 (0,25) diameter of true position relative to
each other at maximum material condition and within
0.030 (0,76) diameter relative to the edge of the ceramic.
E. This package can be hermetically sealed with metal lids
or with ceramic lids using glass frit.
F. The pins can be gold-plated or solder-dipped.
G. Package thickness of 0.165 (4,19) / 0.120 (3,05) includes
package body and lid.
Air Flow
LFPM
Parameter
°C/W
RΘ
RΘ
1.7
N/A
JC
10.9
9.8
7.0
6.4
5.6
5.5
0
JA
RΘJA
200
400
600
800
1000
RΘ
RΘ
RΘ
RΘ
JA
JA
JA
JA
H. Falls within JEDEC MO-128AK
57
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
MECHANICAL DATA
HFH (R-CQFP-F352)
CERAMIC QUAD FLATPACK WITH NCTB
76,40
74,85
75,40
74,60
57,00
55,60
48,48
5,50
SQ
Tie Bar Width
4,50
47,52
1,55
Dia
43,50
BSC
1,45
4 Places
352
1
265
264
DETAIL ”C”
70,00 BSC
3,60
3,50
177
176
88
89
DETAIL ”B”
2,60
2,50
2,60
2,50
Dia 2 Places
DETAIL ”A”
0,50 MAX
0,25
352 X
0,18
3,34 MAX
2,79 MAX
1,05
0,75
0,20
0,10
0,35
0,05
0,50
DETAIL ”C”
DETAIL ”B”
DETAIL ”A”
4040232-5/F 12/98
NOTES: A. All linear dimensions are in millimeters.
THERMAL RESISTANCE
CHARACTERISTICS
B. This drawing is subject to change without notice.
C. This package is hermetically sealed with a metal lid.
D. The terminals are gold-plated.
E. Leads not shown for clarity purposes
F. Falls within JEDEC MO-134AE
Parameter
° C/W
1.28
RΘ
RΘ
JC
JA
28.70
58
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001
MECHANICAL DATA
TAB (48 mm WITH PROTECTIVE FILM)
SMJ320C40 324-PIN TAB FRAME SOCKET (PG 5.x)
325 OLB/ILB 0.25 mm OLB PITCH
0,26
0,24
20,025
19,075
× 81 =
325
244
243
1
Tab Leads Up
Die Face Up
81
163
162
82
0,26
0,24
20,025
19,075
× 80 =
2,25
(4 Places)
24,00
(2 Places)
4073433
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. The OLB lead width is 0,10 ± 0,02 mm.
D. The ILB lead width is 0,05 ± 0,01 mm.
E. The tape width is 48 mm.
F. The TAB is encapsulated die with polyimide overcoat.
59
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
5962-9466902QXA
ACTIVE
CPGA
CPGA
CFP
GF
325
325
352
1
TBD
TBD
TBD
Call TI
Call TI
Call TI
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
5962-9466902QX
A
SMJ320C40GFM40
5962-9466902QXC
5962-9466902QYC
ACTIVE
ACTIVE
GF
1
1
-55 to 125
-55 to 125
5962-9466902QX
C
SMJ320C40GFM40
HFH
5962-9466902QY
C
SMJ320C40HFHM4
0
5962-9466903QXA
5962-9466903QXC
5962-9466903QYC
ACTIVE
ACTIVE
ACTIVE
CPGA
CPGA
CFP
GF
GF
325
325
352
1
1
1
TBD
TBD
TBD
Call TI
Call TI
Call TI
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
5962-9466903QX
A
SMJ320C40GFM50
5962-9466903QX
C
SMJ320C40GFM50
HFH
5962-9466903QY
C
SMJ320C40HFHM5
0
5962-9466904QXA
5962-9466904QYC
ACTIVE
ACTIVE
CPGA
CFP
GF
325
352
1
1
TBD
TBD
Call TI
Call TI
N / A for Pkg Type
N / A for Pkg Type
-55 to 100
-55 to 100
5962-9466904QX
A
SMJ320C40GFS60
HFH
5962-9466904QY
C
SMJ320C40HFHS6
0
SM320C40GFM40
SM320C40GFM50
SM320C40GFS60
SM320C40HFHM40
SM320C40HFHM50
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CPGA
CPGA
CPGA
CFP
GF
GF
325
325
325
352
352
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 100
-55 to 125
-55 to 125
SM320C40GFM40
SM320C40GFM50
SM320C40GFS60
SM320C40HFHM40
SM320C40HFHM50
GF
HFH
HFH
CFP
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
SM320C40HFHS60
SM320C40KGDS50D
SMJ320C40GFM40
ACTIVE
CFP
HFH
352
0
1
TBD
TBD
TBD
Call TI
Call TI
Call TI
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 100
-55 to 100
-55 to 125
SM320C40HFHS60
ACTIVE
ACTIVE
XCEPT
CPGA
KGD
GF
1
1
325
5962-9466902QX
A
SMJ320C40GFM40
SMJ320C40GFM50
SMJ320C40GFS60
SMJ320C40HFHM40
ACTIVE
ACTIVE
ACTIVE
CPGA
CPGA
CFP
GF
GF
325
325
352
1
1
1
TBD
TBD
TBD
Call TI
Call TI
Call TI
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 100
-55 to 125
5962-9466903QX
A
SMJ320C40GFM50
5962-9466904QX
A
SMJ320C40GFS60
HFH
5962-9466902QY
C
SMJ320C40HFHM4
0
SMJ320C40HFHM50
SMJ320C40HFHS60
ACTIVE
ACTIVE
CFP
CFP
HFH
HFH
352
352
1
1
TBD
TBD
Call TI
Call TI
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 100
5962-9466903QY
C
SMJ320C40HFHM5
0
5962-9466904QY
C
SMJ320C40HFHS6
0
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SM320C40, SMJ320C40 :
Catalog: TMS320C40, TMS320C40
•
Military: SMJ320C40
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 3
MECHANICAL DATA
MCFP029B – JANUARY 1995 – REVISED JUNE 1999
HFH (R-CQFP-F352)
CERAMIC QUAD FLATPACK WITH NCTB
76,40
74,85
75,40
74,60
57,00
55,60
48,48
5,50
SQ
Tie Bar Width
4,50
47,52
43,50
BSC
1,55
Dia
1,45
4 Places
352
1
265
264
DETAIL ”C”
70,00 BSC
3,60
3,50
177
88
89
176
DETAIL ”B”
2,60
2,50
2,60
Dia 2 Places
DETAIL ”A”
2,50
0,50 MAX
0,25
352 X
0,18
3,34 MAX
2,79 MAX
1,05
0,20
0,10
0,75
0,35
0,05
0,50
DETAIL ”C”
DETAIL ”B”
DETAIL ”A”
4040232-5/F 12/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. This package is hermetically sealed with a metal lid.
D. The terminals are gold-plated.
E. Leads not shown for clarity purposes
F. Falls within JEDEC MO-134AE
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCPG013F – JANUARY 1995 – REVISED DECEMBER 2001
GF (S-CPGA-P325)
CERAMIC PIN GRID ARRAY
1.717 (43,61)
1.683 (42,75)
1.879 (47,73)
TYP
SQ
1.841 (46,76)
0.100 (2,54)
AR
AN
AL
AJ
AG
AE
AC
AA
W
U
A1 Corner
R
N
L
J
G
E
C
A
1 3
5
7
9 11 13 15 17 19 2123 25 27 29 3133 35
Bottom View
0.050 (1,27)
0.048 (1,22) DIA 4 Places
0.190 (4,83)
0.170 (4,32)
0.080 (2,03) TYP
0.050 (1,27) TYP
0.060 (1,52)
0.040 (1,02)
0.020 (0,51)
0.016 (0,41)
0.150 (3,81)
TYP
0.026 (0,660)
0.006 (0,152)
0.165 (4,19)
0.120 (3,05)
0.200 (5,08)
0.145 (3,68)
DETAIL A
4040035-2/F 11/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Index mark can appear on top or bottom, depending on package vendor.
D. Pins are located within 0.010 (0,25) diameter of true position relative to
each other at maximum material condition and within 0.030 (0,76) diameter
relative to the edge of the ceramic.
E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit.
F. The pins can be gold-plated or solder-dipped.
G. Package thickness of 0.165 (4,19) / 0.120 (3,05) includes package body and lid.
H. Falls within JEDEC MO-128AK
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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