SMJ55161 [TI]
262144 BY 16-BIT MULTIPORT VIDEO RAM; 262144除以16位的多端口视频RAM
| 型号： | SMJ55161 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 262144 BY 16-BIT MULTIPORT VIDEO RAM |
| 文件： | 总64页 (文件大小：1539K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
HKC PACKAGE
(TOP VIEW)
Organization:
– DRAM: 262 144 by 16 Bits
– SAM: 256 by 16 Bits
V
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
SC
SE
V
CC
TRG
Dual-Port Accessibility – Simultaneous and
Asynchronous Access From the DRAM and
SAM Ports
V
SS
SS
SQ0
DQ0
SQ1
DQ1
SQ15
DQ15
SQ14
DQ14
Data-Transfer Function From the DRAM to
the Serial-Data Register
V
V
CC
CC
SQ2
SQ13
DQ13
SQ12
DQ12
9
10
11
DQ2
SQ3
DQ3
(4 × 4) × 4 Block-Write Feature for Fast
Area-Fill Operations; as Many as Four
Memory-Address Locations Written Per
Cycle From the 16-Bit On-Chip Color
Register
54
53
52
51
50
49
12
13
V
V
SS
SS
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SQ4
DQ4
SQ5
SQ11
DQ11
SQ10
DQ5
V
DQ10
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Write-Per-Bit Feature for Selective Write to
Each RAM I/O; Two Write-Per-Bit Modes to
Simplify System Design
V
CC
CC
SQ6
DQ6
SQ7
DQ7
SQ9
DQ9
SQ8
DQ8
Byte-Write Control (CASL, CASU) Provides
Flexibility
V
V
SS
SS
CASL
DSF
NC / GND
CASU
QSF
A0
WE
RAS
A8
Extended Data Output for Faster System
Cycle Time
A7
Enhanced Page-Mode Operation for Faster
Access
A6
29
30
31
A1
A5
A4
A2
A3
CAS-Before-RAS (CBR) and
Hidden-Refresh Modes
V
32
V
CC
SS
Long Refresh Period
Programmable Split-Register Stop Point
Every 8 ms (Maximum)
3-State Serial Outputs Allow Easy
Multiplexing of Video-Data Streams
Up to 45-MHz Uninterrupted Serial-Data
Streams
All Inputs/Outputs and Clocks TTL
Compatible
256 Selectable Serial-Register Starting
Locations
Compatible With JEDEC Standards
SE-Controlled Register-Status QSF
Designed to Work With the Texas
Instruments Graphics Family
Split-Register-Transfer Read for Simplified
Real-Time Register Load
Performance Ranges:
OPERATING CURRENT
OPERATING CURRENT
ACCESS TIME ACCESS TIME
DRAM
DRAM
SERIAL
ROW ENABLE
SERIAL DATA CYCLE TIME PAGE MODE CYCLE TIME
SERIAL PORT STAND- SERIAL PORT AC-
t
t
t
t
t
I
I
CC1A
BY
TIVE
a(R)
a(SQ)
c(W)
c(P)
c(SC)
CC1
(MAX)
(MAX)
(MIN)
(MIN)
(MIN)
(MAX)
(MAX)
SMJ55161-75
SMJ55161-80
75 ns
80 ns
23 ns
25 ns
140 ns
150 ns
48 ns
50 ns
24 ns
30 ns
165 mA
160 mA
210 mA
195 mA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
PIN NOMENCLATURE
A0–A8
Address Inputs
CASL, CASU
DQ0 –DQ15
DSF
Column-Address Strobe/Byte Selects
DRAM Data I/O, Write Mask Data
Special-Function Select
NC/GND
No Connect/Ground (Important: Not
connected internally to V
Special-Function Output
Row-Address Strobe
Serial Clock
)
SS
QSF
RAS
SC
SE
Serial Enable
SQ0–SQ15
TRG
Serial-Data Output
Output Enable, Transfer Select
5-V Supply (TYP)
Ground
DRAM Write-Enable Select
V
CC
V
SS
WE
GB PACKAGE
(BOTTOM VIEW)
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
GB Package Pin Assignments – By Location
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
NO.
J1
NO.
J2
NO.
J3
NO.
J4
NO.
J5
NO.
J6
NO.
J7
NO.
J8
NO.
J9
DQ1
DQ0
SQ0
TRG
SC
SQ3
SQ2
SQ1
DQ3
DQ2
DQ4
SQ4
DQ5
SQ5
DQ6
SQ6
SQ7
DQ7
CASL
WE
A8
A7
H1
G1
F1
E1
D1
C1
B1
A1
H2
G2
F2
E2
D2
C2
B2
A2
H3
G3
F3
H4
G4
H5
H6
G6
H7
G7
F7
H8
G8
F8
E8
D8
H9
G9
F9
E9
D9
V
DD2
V
SS2
V
DD2
V
SS2
RAS
A6
V
SS1
V
DD1
V
DD1
V
DD1
A5
V
DD1
V
SS1
A3
A4
SE
V
D3
C3
B3
A3
V
V
D7
C7
B7
A7
V
V
A2
SS1
SS1
DD1
SS1
SQ15
DQ15
SQ14
V
C4
B4
A4
V
SS2
C6
B6
A6
V
DD2
C8 CASU C9
A1
DD2
SS2
DQ14
SQ13
DQ13
SQ12
DQ12
SQ11
B5
A5
DQ11
SQ10
DQ10
SQ9
SQ8
DQ9
B8
A8
DSF
DQ8
B9
A9
A0
QSF
GB Package Pin Assignments – By Signal
PIN
PIN
PIN
PIN
PIN
PIN
NAME
NO.
NAME
NO.
J1
NAME
DQ12
DQ13
DQ14
DQ15
DSF
QSF
RAS
SC
NO.
B4
B3
B2
B1
B8
A9
G8
E1
D1
G1
G2
NAME
SQ2
SQ3
SQ4
SQ5
SQ6
SQ7
SQ8
SQ9
SQ10
SQ11
SQ12
NO.
H2
J2
NAME
NO.
A2
A1
C1
F1
E2
F3
D3
F7
F8
G3
C3
NAME
NO.
G6
C6
F2
A0
A1
B9
C9
D9
D8
E9
F9
G9
H9
J9
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
SQ13
SQ14
SQ15
TRG
V
V
DD2
H3
J3
DD2
A2
H4
H5
H6
J7
V
SS1
V
SS1
V
SS1
V
SS1
V
SS1
V
SS2
V
SS2
V
SS2
V
SS2
A3
J4
D2
C2
D7
E8
G4
C4
G7
C7
H8
A4
J5
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD2
V
DD2
A5
J6
A6
H7
A8
A7
B6
B5
B7
A6
A5
A4
A3
A7
A8
SE
CASL
CASU
DQ0
J8
SQ0
SQ1
C8
H1
WE
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
description
The SMJ55161 multiport-video random-access memory (RAM) is a high-speed, dual-port memory device. It
consists of a dynamic RAM (DRAM) module organized as 262 144 words of 16 bits each interfaced to a
serial-data register (serial-access memory [SAM]) organized as 256 words of 16 bits each. The SMJ55161
supports three basic types of operation: random access to and from the DRAM, serial access from the serial
register, and transfer of data from any row in the DRAM to the serial register. Except during transfer operations,
the SMJ55161 can be accessed simultaneously and asynchronously from the DRAM and SAM ports.
The SMJ55161 is equipped with several features designed to provide higher system-level bandwidth and to
simplify design integration on both the DRAM and SAM ports. On the DRAM port, greater pixel-draw rates are
achieved by the device’s (4 × 4) × 4 block-write feature. The block-write mode allows 16 bits of data (present
in an on-chip color-data register) to be written to any combination of four adjacent column-address locations.
As many as 64 bits of data can be written to memory during each CAS cycle time. Also, on the DRAM port, a
write mask or a write-per-bit feature allows masking of any combination of the 16 inputs/outputs on any write
cycle. The persistent write-per-bit feature uses a mask register that, once loaded, can be used on subsequent
write cycles without reloading. The SMJ55161 also offers byte control which can be applied in read cycles, write
cycles, block-write cycles, load-write-mask-register cycles, and load-color-register cycles. The SMJ55161 also
offers extended-data-output (EDO) mode. The EDO mode is effective in both the page-mode and standard
DRAM cycles.
The SMJ55161 offers a split-register-transfer read (DRAM-to-SAM) feature for the serial register (SAM port)
that enables real-time-register-load implementation for continuous serial-data streams without critical timing
requirements. The register is divided into a high half and a low half. While one half is being read out of the SAM
port, the other half can be loaded from the memory array. For applications not requiring real-time register load
(for example, loads done during CRT-retrace periods), the full-register mode of operation is retained to simplify
system design.
The SAM port is designed for maximum performance. Data can be accessed from the SAM at serial rates up
to 45 MHz. During the split-register-transfer read operations, internal circuitry detects when the last bit position
is accessed from the active half of the register and immediately transfers control to the opposite half. A separate
output, QSF, is included to indicate which half of the serial register is active.
All inputs, outputs, and clock signals on the SMJ55161 are compatible with Series 74 TTL. All address lines and
data-in lines are latched on-chip to simplify system design. All data-out lines are unlatched to allow greater
system flexibility.
The SMJ55161 is offered in a 68-pin ceramic pin-grid-array package (GB suffix) and a 64-pin ceramic flatpack
(HKC suffix).
The SMJ55161 and other TI multiport-video RAMs are supported by a broad line of graphic processors and
control devices from TI. See Table 2 and Table 4 for additional information.
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
functional block diagram
1 of 4 Subblocks
(see next page)
Input
DSF
Buffer
DRAM
Input
Buffer
Special-
Function
Logic
Column
Buffer
9
1 of 4 Subblocks
(see next page)
16
DQ0–
DQ15
A0–A8
Row
Buffer
DRAM
Output
Buffer
SC
1 of 4 Subblocks
(see next page)
Serial-
Address
Refresh
Counter
Counter
Split-
Register
Status
Serial-
Output
Buffer
16
SQ0–
SQ15
QSF
SE
1 of 4 Subblocks
(see next page)
SE
RAS
CASx
TRG
WE
Timing
Generator
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
functional block diagram (continued)
Special-
Function
Logic
DSF
Input
Buffer
Color
Register
W/B
Unlatch
W/B
Latch
DRAM
Input
Address
Mask
MUX
Buffer
DQi
Write-
Per-Bit
Control
DQi+1
DQi+2
DQi+3
DRAM
Output
Buffer
Column DEC
Column
Buffer
Sense AMP
9
RAS
CASx
TRG
WE
Timing
Generator
A0–A8
512 × 512
Memory
Array
Row
Buffer
Row
Decoder
Serial-Data
Register
SC
Serial-Data
Pointer
SQi
SQi + 1
SQi +2
SQi + 3
Serial-
Address
Counter
Serial-
Output
Buffer
Refresh
Counter
Split-
Register
Status
1 of 4 Subblocks
SE
QSF
SE
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
functional operation description
Table 1 lists the DRAM and SAM functions, summarizing Table 3 and Table 4.
Table 1. DRAM and SAM Functions
CASx
FALL
†
DQ0–DQ15
RAS FALL
ADDRESS
MNE
CODE
FUNCTION
CASL
CASU
WE
‡
§
CASx
TRG
WE
DSF
DSF
RAS
CASx
RAS
Reserved (do not use)
CBR refresh (no reset) and stop-point
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
—
Stop
Point
X
H
CBRS
¶
#
set
||
CBR refresh (option reset)
CBR refresh (no reset)
L
L
X
X
H
H
L
X
X
X
X
X
X
X
X
X
CBR
H
X
CBRN
Row
Address
Tap
Point
Full-register-transfer read
H
H
H
L
L
H
H
L
L
H
L
X
X
L
X
X
X
X
RT
Row
Address
Tap
Point
Split-register-transfer read
DRAM write
SRT
RWM
Row
Column
Write
Mask
Valid
Data
H
(nonpersistent write-per-bit)
Address Address
Block
Row
DRAM block write
(nonpersistent write-per-bit)
Write
Mask
Column
Mask
Address
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
H
L
BWM
RWM
BWM
RW
Address
A2–A8
DRAM write
(persistent write-per-bit)
Row
Column
Valid
Data
X
X
X
X
Address Address
Block
Row
DRAM block write
(persistent write-per-bit)
Column
Mask
Address
A2–A8
L
H
L
Address
Row
Column
Valid
Data
DRAM write (nonmasked)
DRAM block write (nonmasked)
Load write-mask register
H
H
Address Address
Block
Row
Column
Mask
Address
A2–A8
H
BW
Address
Refresh
X
Write
Mask
H
H
H
H
H
H
H
H
L
X
X
LMR
LCR
Address
Refresh
X
Color
Data
Load color register
Legend:
H
Address
Col Mask
Write Mask
X
=
=
=
H: Write to address/column enabled
H: Write to I/O enabled
Don’t care
†
‡
§
¶
#
||
DQ0–DQ15 are latched on either the first falling edge of CASx or the falling edge of WE, whichever occurs later.
Logic L is selected when either or both CASL and CASU are low.
The column address and block address are latched on the first falling edge of CASx.
CBRS cycle should be performed immediately after the powerup initialization cycle.
A0–A3, A8: don’t care; A4–A7: stop-point code
CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode.
CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode.
Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option reset)
cycle.
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
pin definitions
Table 2. Pin Description Versus Operational Mode
PIN
DRAM
TRANSFER
SAM
A0 – A8
Row, column address
Row address, tap point
CASL
CASU
Column-address strobe, DQ output enable
DRAM data I/O, write mask
Tap-address strobe
DQ
DSF
Split-register-transferenable
Block-write enable
Write-mask-register load enable
Color-register load enable
CBR (option reset)
RAS
SE
Row-address strobe
Row-address strobe
Transfer enable
SQ output enable,
QSF output enable
SC
Serial clock
SQ
Serial-data output
TRG
WE
DQ output enable
Write enable, write-per-bit enable
QSF
NC/GND
Special-function output
Serial-register status
Either make no external connection or tie to system GND (V
)
SS
†
V
5-V supply
Ground
CC
†
V
SS
†
For proper device operation, all V
pins must be connected to a 5-V supply, and all V
pins must be tied to ground.
SS
CC
address (A0–A8)
Eighteen address bits are required to decode each one of the 262 144 storage cell locations. Nine row-address
bits are set up on pins A0–A8 and latched onto the chip on the falling edge of RAS. Nine column-address bits
are set up on pins A0–A8 and latched onto the chip on the first falling edge of CASx. All addresses must be
stable on or before the falling edge of RAS and the first falling edge of CASx.
During the full-register-transfer read operation, the states of A0–A8 are latched on the falling edge of RAS to
select one of the 512 rows where the transfer occurs. At the first falling edge of CASx, the column-address bits
A0–A8 are latched. The most significant column-address bit (A8) selects which half of the row is transferred
to the SAM. The appropriate 8-bit column address (A0–A7) selects one of 256 tap points (starting positions)
for the serial-data output.
Duringthesplit-register-transferreadoperation, addressbitA7isignoredatthefallingedgeofCASx. Aninternal
counter selects which half of the register is used. If the high half of the SAM is currently in use, the low half of
theSAMisloadedwiththelowhalfoftheDRAMhalfrowandviceversa. Columnaddress(A8)selectstheDRAM
half row. The remaining seven address bits (A0–A6) are used to select one of 127 possible starting locations
within the SAM. Locations 127 and 255 are not valid tap points.
row-address strobe (RAS)
RAS is similar to a chip enable so that all DRAM cycles and transfer cycles are initiated by the falling edge of
RAS. RAS is a control input that latches the states of the row address, WE, TRG, CASL, CASU, and DSF onto
the chip to invoke DRAM and transfer-read functions of the SMJ55161.
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
column-address strobe (CASL, CASU)
CASL and CASU are control inputs that latch the states of the column address and DSF to control DRAM and
transfer functions of the SMJ55161. CASx also acts as output enable for the DRAM output pins DQ0–DQ15.
In DRAM operation, CASL enables data to be written to or read from the lower byte (DQ0–DQ7), and CASU
enables data to be written to or from the upper byte (DQ8–DQ15). In transfer operations, address bits A0–A8
are latched at the first falling edge of CASx as the start position (tap) for the serial-data output (SQ0–SQ15).
output enable/transfer select (TRG)
TRG selects either DRAM or transfer operation as RAS falls. For DRAM operation, TRG must be held high as
RAS falls. During DRAM operation, TRG functions as an output enable for the DRAM output pins DQ0–DQ15.
For transfer operation, TRG must be brought low before RAS falls.
write-mask select, write enable (WE)
In DRAM operation, WE enables data to be written to the DRAM. WE is also used to select the DRAM
write-per-bit mode. Holding WE low on the falling edge of RAS invokes the write-per-bit operation. The
SMJ55161 supports both the nonpersistent write-per-bit mode and the persistent write-per-bit mode.
special-function select (DSF)
The DSF input is latched on the falling edge of RAS or the first falling edge of CASx, similar to an address. DSF
determines which of the following functions are invoked on a particular cycle:
CBR refresh with reset (CBR)
CBR refresh with no reset (CBRN)
CBR refresh with no reset and stop-point set (CBRS)
Block write
Loading write-mask register for the persistent write-per-bit mode (LMR)
Loading color register for the block-write mode
Split-register-transfer read
DRAM data I/O, write mask data (DQ0–DQ15)
DRAM data is written or read through the common I/O DQ pins. The 3-state DQ-output buffers provide direct
TTL compatibility (no pullup resistors) with a fanout of one Series 54 TTL load. Data out is the same polarity
as data in. During a normal access cycle, the outputs remain in the high-impedance state until TRG is brought
low. Data appears at the outputs until TRGreturnshigh, CASx returns high following RAS returning high, or RAS
returns high following CASx returning high. The write mask is latched into the device through the random DQ
pins by the falling edge of RAS and is used on all write-per-bit cycles. In a transfer operation, the DQ outputs
remain in the high-impedance state for the entire cycle.
serial-data outputs (SQ0 –SQ15)
Serial data is read from the SQ pins. The SQ output buffers provide direct TTL compatibility (no pullup resistors)
with a fanout of one Series 54 TTL load. The serial outputs are in the high-impedance (floating) state as long
as the serial-enable pin, SE, is high. The serial outputs are enabled when SE is brought low.
serial clock (SC)
Serial data is accessed out of the data register during the rising edge of SC. The SMJ55161 is designed to work
with a wide range of clock duty cycles to simplify system design. There is no refresh requirement because the
data registers that comprise the SAM are static. There is also no minimum SC-clock operating frequency.
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
serial enable (SE)
During serial-access operations, SE is used as an enable/disable for the SQ outputs. SE low enables the
serial-data output while SE high disables the serial-data output. SE is also used as an enable/disable for output
pin QSF.
IMPORTANT: While SE is held high, the serial clock is not disabled. External SC pulses increment the internal
serial-address counter regardless of the state of SE. This ungated serial-clock scheme minimizes access time
of serial output from SElowbecausetheserial-clockinputbufferandtheserial-addresscounterarenotdisabled
by SE.
special-function output (QSF)
QSFisanoutputpinthatindicateswhichhalfoftheSAMisbeingaccessed. WhenQSFislow, theserial-address
pointer is accessing the lower (least significant) 128 bits of the serial register (SAM). When QSF is high, the
pointer is accessing the higher (most significant) 128 bits of the SAM.
During full-register-transfer operations, QSF can change state upon completing the cycle. This state is
determined by the tap point loaded during the transfer cycle. QSF is enabled by SE; therefore, if SE is high, the
QSF output is in the high-impedance state.
no connect / ground (NC/GND)
NC/GND must be tied to system ground or left floating for proper device operation.
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
random access operation
Table 3 lists the DRAM functions.
Table 3. DRAM Functions
CASx
†
DQ0–DQ15
RAS FALL
FALL
ADDRESS
MNE
CODE
FUNCTION
CASx
CASL
CASU
WE
‡
§
TRG
WE
DSF
DSF
RAS
CASx
RAS
Reserved (do not use)
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
—
CBR refresh (no reset) and stop-point
Stop
Point
X
H
CBRS
¶
set
#
||
CBR refresh (option reset)
CBR refresh (no reset)
DRAM write
L
L
X
X
H
H
L
X
X
X
X
X
X
X
X
X
CBR
H
X
CBRN
Row
Column
Write
Mask
Valid
Data
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
H
L
RWM
BWM
RWM
BWM
RW
(nonpersistent write-per-bit)
Address Address
Block
Row
Address
DRAM block write
Write
Mask
Column
Mask
Address
A2–A8
(nonpersistent write-per-bit)
DRAM write
(persistent write-per-bit)
Row
Column
Valid
Data
L
X
X
X
X
Address Address
Block
Row
Address
DRAM block write
(persistent write-per-bit)
Column
Mask
Address
A2–A8
L
H
L
Row
Column
Valid
Data
DRAM write (nonmasked)
DRAM block write (nonmasked)
Load write-mask register
H
H
Address Address
Block
Row
Address
Column
Mask
Address
A2–A8
H
BW
Refresh
X
Write
Mask
H
H
H
H
H
H
H
H
L
X
X
LMR
LCR
Address
Refresh
X
Color
Data
Load color register
Legend:
H
Address
Col Mask
Write Mask
X
=
=
=
H: Write to address/column enabled
H: Write to I/O enabled
Don’t care
†
‡
§
¶
#
||
DQ0–DQ15 are latched on either the first falling edge of CASx or the falling edge of WE, whichever occurs later.
Logic L is selected when either or both CASL and CASU are low.
The column address and block address are latched on the first falling edge of CASx.
CBRS cycle should be performed immediately after the power-up initialization cycle.
A0–A3, A8: don’t care; A4–A7: stop-point code
CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode.
CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode.
Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option reset)
cycle.
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enhanced page mode
Enhancedpage-modeoperationallowsfastermemoryaccessbykeepingthesamerowaddresswhileselecting
random column addresses. This mode eliminates the time required for row-address setup, row-address hold,
and address multiplex. The maximum RAS low time and CAS page cycle time used determine the number of
columns that can be accessed.
Unlike conventional page-mode operations, the enhanced page mode allows the SMJ55161 to operate at a
higher data bandwidth. Data retrieval begins as soon as the column address is valid rather than when CASx
transitions low. A valid column address can be presented immediately after the row-address hold time has been
satisfied, usually well in advance of the falling edge of CASx. In this case, data is obtained after t
MAX
a(C)
(access time from CASx low) if t
MAX (access time from column address) has been satisfied.
a(CA)
refresh
CAS-before-RAS (CBR) refresh
CBR refreshes are accomplished by bringing either or both CASL and CASU low earlier than RAS. The external
row address is ignored, and the refresh row address is generated internally. Three types of CBR refresh cycles
are available. The CBR refresh (option reset) ends the persistent write-per-bit mode and the stop-point mode.
The CBRN and CBRS refreshes (no reset) do not end the persistent write-per-bit mode or the stop-point mode.
The 512 rows of the DRAM do not necessarily need to be refreshed consecutively as long as the entire refresh
is completed within the required time period, t
during the CBR refresh cycles regardless of the state of TRG.
. The output buffers remain in the high-impedance state
rf(MA)
hidden refresh
A hidden refresh is accomplished by holding both CASL and CASU low in the DRAM read cycle and cycling
RAS. The output data of the DRAM read cycle remains valid while the refresh is carried out. Like the CBR
refresh, the refreshed row addresses are generated internally during the hidden refresh.
RAS-only refresh
A RAS-only refresh is accomplished by cycling RAS at every row address. Unless CASx and TRG are low, the
output buffers remain in the high-impedance state to conserve power. Externally-generated addresses must
be supplied during RAS-only refresh. Strobing each of the 512 row addresses with RAS causes all bits in each
row to be refreshed.
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extended data output
The SMJ55161 features EDO during DRAM accesses. While RAS and TRG are low, the DRAM output remains
valid. The output remains valid even when CASx returns high until WE is low, TRG is high, or both CASx and
RASare high (see Figure 1 and Figure 2). The EDO mode functions during all read cycles including DRAM read,
page-mode read, and read-modify-write cycles (see Figure 3).
RAS
CASx
t
dis(RH)
DQ0–DQ15
Valid Output
t
dis(G)
TRG
Figure 1. DRAM Read Cycle With RAS-Controlled Output
RAS
CASx
t
dis(CH)
DQ0–DQ15
Valid Output
t
dis(G)
TRG
Figure 2. DRAM Read Cycle With CASx-Controlled Output
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extended-data output (continued)
RAS
CASx
Row
Column
Column
A0–A8
t
t
t
a(CP)
t
a(CA)
a(C)
a(C)
t
t
h(CLQ)
a(CA)
Valid Output
Valid Output
DQ0–DQ15
TRG
Figure 3. DRAM Page-Read Cycle With Extended Output
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byte operation
Byte operation can be applied in DRAM-read cycles, write cycles, block-write cycles, load-write-mask-register
cycles, and load-color-register cycles. In byte operation, the column address (A0–A8) is latched at the first
falling edge of CASx. In read cycles, CASL enables the lower byte (DQ0–DQ7) and CASU enables the upper
byte (DQ8–DQ15) (see Figure 4).
RAS
CASL
CASU
t
su(CA)
t
h(CLCA)
A0–A8
Row
Column
t
a(C)
DQ0–DQ7
Lower Byte Output
t
a(C)
Upper Byte
Output
DQ8–DQ15
t
a(G)
TRG
Figure 4. Example of a Byte-Read Cycle
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byte operation (continued)
In byte-write operation, CASL enables data to be written to the lower byte (DQ0–DQ7), and CASU enables data
to be written to the upper byte (DQ8–DQ15). In an early write cycle, WE is brought low prior to both CASx
signals, and data setup and hold times for DQ0 –DQ15 are referenced to the first falling edge of CASx
(see Figure 5).
RAS
WE
CASL
t
su(CA)
CASU
t
h(CLCA)
Row
Column
A0–A8
t
su(DCL)
t
h(CLD)
Valid Input
DQ0–DQ15
Figure 5. Example of an Early-Write Cycle
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byte operation (continued)
For late-write or read-modify-write cycles, WE is brought low after either or both CASL and CASU fall. The data
is strobed in with data setup and hold times for DQ0 –DQ15 referenced to WE (see Figure 6).
RAS
CASL
CASU
WE
t
su(DWL)
t
h(WLD)
DQ0–DQ15
Valid Input
Figure 6. Example of a Late-Write Cycle
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write-per-bit
The write-per-bit feature allows masking any combination of the 16 DQs on any write cycle. The write-per-bit
operation is invoked when WE is held low on the falling edge of RAS. If WE is held high on the falling edge of
RAS, the write operation is performed without any masking. The SMJ55161 offers two write-per-bit modes:
nonpersistent write-per-bit and persistent write-per-bit.
nonpersistent write-per-bit
When WE is low on the falling edge of RAS, the write mask is reloaded. A 16-bit binary code (the write-per-bit
mask) is input to the device through the DQ pins and latched on the falling edge of RAS. The write-per-bit mask
selects which of the 16 I/Os are to be written and which are not. After RAS has latched the on-chip write-per-bit
mask, input data is driven onto the DQ pins and is latched on either the first falling edge of CASx or the falling
edge of WE, whichever occurs later. CASL enables the lower byte (DQ0–DQ7) to be written through the mask
and CASU enables the upper byte (DQ8–DQ15) to be written through the mask. If a data low (write mask = 0)
is strobed into a particular I/O pin on the falling edge of RAS, data is not written to that I/O. If a data high
(write mask = 1) is strobed into a particular I/O pin on the falling edge of RAS, data is written to that I/O
(see Figure 7).
RAS
CASL
CASU
WE
t
su(DQR)
t
h(WLD)
t
h(RDQ)
t
su(DWL)
DQ0–DQ15
Write Mask
Valid Input
Figure 7. Example of a Nonpersistent Write-Per-Bit (Late-Write) Operation
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persistent write-per-bit
The persistent write-per-bit mode is initiated by performing a load-write-mask-register (LMR) cycle. In the
persistent write-per-bit mode, the write-per-bit mask is overwritten but remains valid over an arbitrary number
of write cycles until another LMR cycle is performed or power is removed.
The LMR cycle is performed using DRAM write-cycle timing with DSF held high on the falling edge of RAS and
held low on the first falling edge of CASx. A binary code is input to the write-mask register via the random I/O
pins and latched on either the first falling edge of CASx or the falling edge of WE, whichever occurs later. Byte
write control can be applied to the write mask during the LMR cycle. The persistent write-per-bit mode can then
be used in exactly the same way as the nonpersistent write-per-bit mode except that the input data on the falling
edge of RAS is ignored. When the device is set to the persistent write-per-bit mode, it remains in this mode and
is reset only by a CBR refresh (option-reset) cycle (see Figure 8).
Load-Write-Mask Register
Persistent Write-Per-Bit
CBR Refresh (option reset)
RAS
CASx
A0–A8
Refresh
Address
Row
Column
DSF
WE
DQ0–
DQ15
Write-Mask
Data
Valid
Input
Mask Data = 1: Write to I/O enabled
= 0: Write to I/O disabled
Figure 8. Example of a Persistent Write-Per-Bit Operation
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block write
The block-write feature allows up to 64 bits of data to be written simultaneously to one row of the memory array.
This function is implemented as four columns by four DQs and repeated in four quadrants. In this manner, each
of the four 1M-bit quadrants can have up to four consecutive columns written at a time with up to four DQs per
column (see Figure 9).
DQ15
DQ14
4th Quadrant
DQ13
DQ12
DQ11
DQ10
3rd Quadrant
DQ9
DQ8
One Row of 0–511
DQ7
DQ6
2nd Quadrant
DQ5
DQ4
DQ3
DQ2
1st Quadrant
DQ1
DQ0
Four Consecutive Columns of 0–511
Figure 9. Block-Write Operation
Each 1M-bit quadrant has a 4-bit column mask to mask off and prevent any or all of the four columns from being
written with data. Nonpersistent write-per-bit or persistent write-per-bit functions can be applied to the
block-write operation to provide write-masking options. The DQ data is provided by 4 bits from the on-chip color
register. Bits 0–3 from the 16-bit write-mask register, bits 0 –3 from the 16-bit column-mask register, and bits
0 –3 from the 16-bit color-data register configure the block write for the first quadrant, while bits 4 –7, 8 –11,
and 12 –15 of the corresponding registers control the other quadrants in a similar fashion (see Figure 10).
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block write (continued)
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
12
13
14
15
DQ9
DQ8
One Row of 0–511
DQ7
DQ6
8
9
DQ5
10
11
DQ4
DQ3
DQ2
4
5
6
7
DQ1
DQ0
0
1
2
3
3
7
11
15
2
6
10
14
1
1
5
9
13
0
4
8
12
0
2
3
4
5
6
7
8
9
10 11
12 13 14 15
Color Register
Figure 10. Block Write With Masks
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block write (continued)
A set of four columns makes a block, resulting in 128 blocks along one row. Block 0 comprises columns 0 –3,
block 1 comprises columns 4 –7, block 2 comprises columns 8 –11, etc., as shown in Figure 11.
Block 0
Block 1 . . . . . . . . . . . . . . . . . . . . . . Block 127
One Row of 0–511
0
1
2
3
4
5
6
7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
Columns
Figure 11. Block Columns Organization
During block-write cycles, only the seven most significant column addresses (A2–A8) are latched on the first
falling edge of CASx to decode one of the 128 blocks. Address bits A0–A1 are ignored. Each 1M-bit quadrant
has the same block selected.
A block-write cycle is entered in a manner similar to a DRAM write cycle except DSF is held high on the first
fallingedgeofCASx. AsinaDRAMwriteoperation, CASLandCASUenablethecorrespondinglowerandupper
DRAM DQ bytes to be written. The column-mask data is input via the DQs and is latched on either the first falling
edge of CASx or the falling edge of WE, whichever occurs later. The 16-bit color-data register must be loaded
prior to performing a block write as described below. Refer to the write-per-bit section for details on use of the
write-mask capability, allowing additional performance options.
Example of block write:
Block-write column address = 110000000 (A0–A8 from left to right)
bit 0
bit 15
0111
1011
1010
Color-data register = 1011
Write-mask register = 1110
Column-mask register = 1111
1011
1111
0000
1100
1111
0111
1st
2nd
3rd
4th
Quad
Quad
Quad
Quad
Column-address bits A0 and A1 are ignored. Block 0 (columns 0 –3) is selected for each 1M-bit quadrant. The
first quadrant has DQ0–DQ2 written with bits 0–2 from the color-data register (101) to all four columns of block
0. DQ3 is not written and retains its previous data due to write-mask-register-bit 3 being 0.
The second quadrant (DQ4–DQ7) has all four columns masked off due to column-mask bits 4–7 being 0 so
that no data is written.
The third quadrant (DQ8–DQ11 ) has its four DQs written with bits 8 –11 from the color-data register (1100) to
columns 1–3 of its block 0. Column 0 is not written and retains its previous data on all four DQs due to
column-mask-register-bit 8 being 0.
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block write (continued)
The fourth quadrant (DQ12–DQ15 ) has DQ12, DQ14, and DQ15 written with bits 12, 14, and 15 from the
color-data register to column 0 and column 2 of its block 0. DQ13 retains its previous data on all columns due
to the write mask. Columns 1 and 3 retain their previous data on all DQs due to the column mask. If the previous
data for the quadrant is all 0s, the fourth quadrant contains the data pattern shown in Figure 12 after the
block-write operation shown in the previous example.
DQ15
1
1
0
0
1
0
DQ14
1
0
0
0
4th Quadrant
DQ13
0
0
0
0
DQ12
0
0
Columns
0
1
2
3
Figure 12. Example of Fourth Quadrant After a Block-Write Operation
load color register
The load-color-register cycle is performed using normal DRAM write-cycle timing except that DSF is held high
on the falling edges of RAS, CASL, and CASU. The color register is loaded from pins DQ0 –DQ15, which are
latched on either the first falling edge of CASx or the falling edge of WE, whichever occurs later. If only one CASx
is low, only the corresponding byte of the color register is loaded. When the color register is loaded, it retains
data until power is lost or until another load-color-register cycle is performed (see Figure 13 and Figure 14).
Load-Color-Register Cycle
Block-Write Cycle
(no write mask)
Block-Write Cycle
(load and use write mask)
RAS
CASx
A0–A8
WE
1
2
3
2
3
TRG
DSF
DQ0–DQ15
4
6
5
6
Legend:
1. Refresh address
2. Row address
3. Block address (A2–A8) is latched on the first falling edge of CASx.
4. Color-register data
5. Write-mask data: DQ0–DQ15 are latched on the falling edge of RAS.
6. Column-mask data: DQi–DQi+3 (i = 0, 4, 8, 12) are latched on either the first falling edge of CASx or the falling edge of WE, whichever
occurs later.
= don’t care
Figure 13. Example of Block Writes
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load color register (continued)
Load-Write-Mask-Register Cycle
Load-Color-Register Cycle
Persistent Block-Write Cycle
(use loaded write mask)
RAS
CASx
A0–A8
WE
1
1
2
3
TRG
DSF
DQ0–DQ15
5
4
6
Legend:
1. Refresh address
2. Row address
3. Block address (A2–A8) is latched on the first falling edge of CASx.
4. Color-register data
5. Write-mask data: DQ0–DQ15 are latched on the falling edge of RAS.
6. Column-mask data: DQi–DQi+3 (i = 0, 4, 8, 12) are latched on either the first falling edge of CASx or the falling edge of WE, whichever
occurs later.
= don’t care
Figure 14. Example of a Persistent Block Write
DRAM-to-SAM transfer operation
During the DRAM-to-SAM transfer operation, one half of a row (256 columns) in the DRAM array is selected
to be transferred to the 256-bit serial-data register. The transfer operation is invoked by TRG being brought low
and WE being held high on the falling edge of RAS. The state of DSF, which is latched on the falling edge of
RAS, determines whether the full-register-transfer read operation or the split-register-transfer read operation
is performed (see Table 4).
Table 4. SAM Function Table
CASx
FALL
RAS FALL
ADDRESS
DQ0–DQ15
CASx
MNE
CODE
FUNCTION
†
CASx
TRG
WE
DSF
L
DSF
RAS
CASx
RAS
WE
Row
Addr
Tap
Point
Full-register-transfer read
Split-register-transfer read
H
H
L
L
H
H
X
X
X
X
X
RT
Row
Addr
Tap
Point
H
X
SRT
†
Logic L is selected when either CASL or CASU are low.
don’t care
X
=
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full-register-transfer read
A full-register-transfer read operation loads data from a selected half of a row in the DRAM into the SAM. TRG
is brought low and latched at the falling edge of RAS. Nine row-address bits (A0–A8) are also latched at the
falling edge of RAS to select one of the 512 rows available for the transfer. The nine column-address bits
(A0– A8) are latched at the first falling edge of CASx, where address bit A8 selects which half of the row is
transferred. Address bits A0–A7 select one of the SAM’s 256 available tap points from which the serial data
is read out (see Figure 15).
A8 = 0
A8 = 1
0
255 256
511
512 × 512
Memory Array
256-Bit
Data Register
0
255
Figure 15. Full-Register-Transfer Read
A full-register-transfer read can be performed in three ways: early load, real-time load (or midline load), or late
load. Each of these offers the flexibility of controlling the TRG trailing edge in the full-register-transfer read cycle
(see Figure 16).
Early Load
Real-Time Load
Late Load
RAS
CASx
A0–A8
Row
Tap
Row
Tap
Row
Tap
Point
Point
Point
TRG
WE
SC
Old
Data
Tap
Bit
Old
Data
Old
Data
Tap
Bit
Old
Data
Old
Data
Tap
Bit
Figure 16. Example of Full-Register-Transfer Read Operations
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split-register-transfer read
In the split-register-transfer-read operation, the serial-data register is split into halves. The low half contains bits
0–127, and the high half contains bits 128– 255. While one half is being read out of the SAM port, the other
half can be loaded from the memory array.
A8 = 0
A8 = 1
0
255 256
511
512 × 512
Memory Array
256-Bit
Data Register
0
255
Figure 17. Split-Register-Transfer Read
To invoke a split-register-transfer-read cycle, DSF is brought high, TRG is brought low, and both are latched
at the falling edge of RAS. Nine row-address bits (A0–A8) are also latched at the falling edge of RAS to select
one of the 512 rows available for the transfer. Eight of the nine column-address bits (A0–A6 and A8) are latched
at the first falling edge of CASx. Column-address bit A8 selects which half of the row is to be transferred.
Column-address bits A0–A6 selects one of the 127 tap points in the specified half of the SAM. Column-address
bit A7 is ignored, and the split-register transfer is controlled internally to select the inactive register half.
Full XFER
Split XFER
A8 = 1
Split XFER
A8 = 1
Split XFER
RAS
A8 = 0
A8 = 0
†
†
†
0
511
0
A7 = 0 511
0
A7 = 1 511
0
A7 = 0
A
511
A
B
A
A
B
C
A
B
C
D
B
C
D
D
E
DRAM
SAM
0
255
0
255
B
0
255
0
255
B
C
C
D
E
SQ
A7 shown as internally controlled.
SQ
SQ
SQ
†
Figure 18. Example of a Split-Register-Transfer Read Operation
A full-register-transfer-read cycle must precede the first split-register-transfer-read cycle to ensure proper
operation. After the full-register-transfer-read cycle, the first split-register-transfer-read cycle can follow
immediately without any minimum SC-clock requirement.
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split-register-transfer read (continued)
QSF indicates which half of the register is being accessed during serial-access operation. When QSF is low,
the serial-address pointer is accessing the lower (least significant) 128 bits of the SAM. When QSF is high, the
pointer is accessing the higher (most significant) 128 bits of the SAM. QSF changes state upon completing a
full-register-transfer-read cycle. The tap point loaded during the current transfer cycle determines the state of
QSF. QSF also changes state when a boundary between two register halves is reached.
Full-Register-Transfer Read
With Tap Point N
Split-Register-
Transfer Read
RAS
CASx
TRG
DSF
SC
Tap
Point N
t
d(CLQSF)
t
d(GHQSF)
QSF
Figure 19. Example of a Split-Register-Transfer Read After a Full-Register-Transfer Read
Split-Register-
Transfer Read
With Tap Point N
Split-Register-
Transfer Read
RAS
CASx
TRG
DSF
t
d(MSRL)
t
d(RHMS)
SC
127
Tap
or 255
Point N
t
d(SCQSF)
QSF
Figure 20. Example of Successive Split-Register-Transfer-Read Operations
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serial-read operation
The serial-read operation can be performed through the SAM port simultaneously and asynchronously with
DRAM operations except during transfer operations. Serial data can be read from the SAM by clocking SC
starting at the tap point loaded by the preceding transfer cycle, proceeding sequentially to the most significant
bit (bit 255), and then wrapping around to the least significant bit (bit 0), as shown in Figure 21.
0
1
2
Tap
254
255
Figure 21. Serial-Pointer Direction for Serial Read
For split-register-transfer-read operation, serial data can be read out from the active half of the SAM by clocking
SCstartingatthetappointloadedbytheprecedingsplit-register-transfercycle. Theserialpointerthenproceeds
sequentially to the most significant bit of the half, bit 127 or bit 255. If there is a split-register-transfer read to
the inactive half during this period, the serial pointer points next to the tap point location loaded by that
split-register transfer (see Figure 22).
0
Tap
126
127
128
Tap
254
255
Figure 22. Serial Pointer for Split-Register Read – Case I
If there is no split-register-transfer read to the inactive half during this period, the serial pointer points next to
bit 128 or bit 0, respectively (see Figure 23).
0
Tap
126
127
128
Tap
254
255
Figure 23. Serial Pointer for Split-Register Read – Case II
split-register programmable stop point
The SMJ55161 offers a programmable stop-point mode for split-register-transfer read operations. This mode
can be used to improve two-dimensional drawing performance in a nonscanline data format.
For a split-register-transfer-read operation, the stop point is defined as a register location at which the serial
output stops coming from one half of the SAM and switches to the opposite half of the SAM. While in stop-point
mode, the SAM is divided into partitions whose length is programmed via row addresses A4–A7 in a CBR set
(CBRS) cycle. The last serial-address location of each partition is the stop point (see Figure 24).
127
128
255
0
Partition
Length
Stop
Points
Figure 24. Example of the SAM With Partitions
28
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SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
split-register programmable stop point (continued)
Stop-point mode is not active until the CBRS cycle is initiated. The CBRS operation is enabled by holding CASx
and WE low and DSF high on the falling edge of RAS. The falling edge of RAS also latches row addresses
A4–A7 which are used to define the SAM’s partition length. The other row-address inputs are don’t cares.
Stop-point mode should be initiated after the initialization cycles are performed (see Table 5).
Table 5. Programming Code for Stop-Point Mode
MAXIMUM
PARTITION
LENGTH
ADDRESS AT RAS IN CBRS CYCLE
NUMBER OF
PARTITIONS
STOP-POINT LOCATIONS
A8
A7
A6
A5
A4
A0–A3
15, 31, 47, 63, 79, 95, 111, 127, 143, 159, 175,
191, 207, 223, 239, 255
16
X
L
L
L
L
X
16
32
64
X
X
L
L
L
L
L
H
H
X
X
8
4
31, 63, 95, 127, 159, 191, 223, 255
63, 127, 191, 255
H
128
(default)
X
L
H
H
H
X
2
127, 255
In stop-point mode, the tap point loaded during the split-register-transfer read cycle determines the SAM
partition in which the serial output begins and at which stop point the serial output stops coming from one half
of the SAM and switches to the opposite half of the SAM (see Figure 25).
Full
Split
Split
Split
Read XFER
Read XFER
Read XFER
Read XFER
RAS
SC
Tap = H1
Tap = L1
Tap = H2
Tap = L2
H1
191 L1
63 H2
255 L2
SAM Low Half
63
SAM High Half
191
0
L1
L2
127
128
H1
H2
255
Figure 25. Example of Split-Register Operation With Programmable Stop Points
29
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SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
256-/512-bit compatibility of split-register programmable stop point
The stop-point mode is designed to be compatible with both 256-bit SAM and 512-bit SAM devices. After the
CBRS cycle is initiated, the stop-point mode becomes active. In stop-point mode only, column-address bits AY7
and AY8 are internally swapped to assure compatibility (see Figure 26). This address-bit swap applies to the
column address and is effective for all DRAM and transfer cycles. For example, during the split-register-transfer
cycle with stop point, column-address bit AY8 is a don’t care and AY7 decodes the DRAM half-row for the
split-register transfer. During stop-point mode, a CBR (option reset) cycle is not recommended because this
ends the stop-point mode and restores address bits AY7 and AY8 to their normal functions. Consistent use of
CBR cycles ensures that the SMJ55161 remains in normal mode.
NONSTOP-POINT MODE
AY8 = 0 AY8 = 1
AY7 = 0 AY7 = 1 AY7 = 0 AY7 = 1
STOP-POINT MODE
AY8 = 0
AY8 = 1
AY7 = 0 AY7 = 1 AY7 = 0 AY7 = 1
512 × 512
Memory Array
512 × 512
Memory Array
256-Bit
Data Register
256-Bit
Data Register
0
255
0
255
Figure 26. DRAM-to-SAM Mapping, Nonstop-Point Versus Stop Point
IMPORTANT: For proper device operation, a stop-point-mode (CBRS) cycle should be initiated immediately
after the power-up initialization cycles are performed.
power up
To achieve proper device operation, an initial pause of 200 µs is required after power up followed by a minimum
of eight RAS cycles or eight CBR cycles to initialize the DRAM port. A full-register-transfer-read cycle and two
SC cycles are required to initialize the SAM port.
After initialization, the internal state of the SMJ55161 is as shown in Table 6.
Table 6. Internal State of SMJ55161
STATE AFTER INITIALIZATION
QSF
Write mode
Defined by the transfer cycle during initialization
Nonpersistent mode
Write-mask register
Color register
Serial-register tap point
SAM port
Undefined
Undefined
Defined by the transfer cycle during initialization
Output mode
30
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SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 V to 7 V
CC
Voltage range on any pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
V
V
Supply voltage
4.5
5
0
5.5
CC
SS
IH
Supply voltage
V
High-level input voltage
Low-level input voltage (see Note 2)
Operating free-air temperature
2.4
–1
6.5
0.8
V
V
IL
T
A
– 55
125
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’55161-75
’55161-80
SAM
PORT
‡
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
V
V
High-level output voltage
Low-level output voltage
I
I
= –1 mA
= 2 mA
2.4
2.4
V
V
OH
OH
0.4
0.4
OL
OL
V
= 5.5 V,
CC
I
I
Input current (leakage)
V = 0 V to 5.8 V,
I
All other pins at 0 V to V
±10
±10
µA
CC
I
I
I
I
I
I
I
I
I
I
I
I
I
Output current (leakage) (see Note 3)
V
= 5.5 V, V = 0 V to V
CC
±10
165
210
12
±10
160
195
12
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
O
CC
See Note 4
= MIN
O
§
§
Operating current
Operating current
Standby current
Standby current
Standby
Active
CC1
t
CC1A
CC2
c(SC)
All clocks = V
Standby
Active
CC
t
= MIN
70
65
CC2A
CC3
c(SC)
See Note 4
RAS-only refresh current
RAS-only refresh current
Standby
Active
165
215
100
145
165
210
180
225
160
195
95
t
t
t
= MIN, (See Note 5)
CC3A
CC4
c(SC)
§
§
Page-mode current
Page-mode current
CBR current
= MIN,
(See Note 5)
Standby
Active
c(P)
= MIN, (See Note 5)
130
160
195
170
200
CC4A
CC5
c(SC)
See Note 4
t = MIN, (See Note 5)
Standby
Active
CBR current
CC5A
CC6
c(SC)
See Note 4
= MIN
Data-transfer current
Data-transfer current
Standby
Active
t
CC6A
c(SC)
‡
§
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
NOTES: 3. SE is disabled for SQ output leakage tests.
4. Measured with one address change while RAS = V ; t
5. Measured with one address change while CASx = V
, t
, t
= MIN
IL c(rd) c(W) c(TRD)
IH
31
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SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 6)
PARAMETER
Input capacitance, address inputs
MIN
TYP
5
MAX
10
10
10
10
10
10
10
15
12
UNIT
pF
pF
pF
pF
pF
pF
pF
pF
pF
C
C
C
C
C
C
C
C
C
i(A)
Input capacitance, address-strobe inputs
Input capacitance, write-enable input
Input capacitance, serial clock
8
i(RC)
i(W)
7
6
i(SC)
i(SE)
i(DSF)
i(TRG)
o(O)
Input capacitance, serial enable
Input capacitance, special function
Input capacitance, transfer-register input
Output capacitance, SQ and DQ
Output capacitance, QSF
7
7
7
12
10
o(QSF)
NOTE 6:
V
CC
= 5 V ± 0.5 V, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 7)
’55161-75
MIN MAX
20
’55161-80
MIN MAX
20
TEST
CONDITIONS
ALT.
SYMBOL
PARAMETER
Access time from CASx
UNIT
†
t
t
t
t
t
t
t
t
t
t
t
= MAX
= MAX
= MAX
= MAX
t
ns
ns
ns
ns
ns
ns
ns
a(C)
d(RLCL)
d(RLCL)
d(RLCL)
d(RLCL)
CAC
Access time from column address
Access time from CASx high
Access time from RAS
t
38
43
75
20
23
18
40
45
80
20
25
20
a(CA)
a(CP)
a(R)
AA
t
CPA
RAC
OEA
t
t
Access time of DQ from TRG low
Access time of SQ from SC high
Access time of SQ from SE low
a(G)
C
C
= 30 pF
t
SCA
a(SQ)
a(SE)
L
L
= 30 pF
= 50 pF
t
SEA
OFF
Disable time, random output from CASx high
(see Note 8)
t
t
t
t
t
C
C
C
C
C
t
0
0
0
0
0
20
20
20
25
18
0
0
0
0
0
20
20
20
25
20
ns
ns
ns
ns
ns
dis(CH)
dis(RH)
dis(G)
L
L
L
L
L
Disable time, random output from RAS high
(see Note 8)
= 50 pF
= 50 pF
= 50 pF
= 30 pF
Disable time, random output from TRG high
(see Note 8)
t
OEZ
Disable time, random output from WE low
(see Note 8)
t
dis(WL)
dis(SE)
WEZ
Disable time, serial output from SE high
(see Note 8)
t
SEZ
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
NOTES: 7. Switching times for RAM-port output are measured with a load equivalent to one TTL load and 50 pF. Data-out reference level:
/ V = 2 V/0.8 V. Switching times for SAM-port output are measured with a load equivalent to one TTL load and 30 pF.
V
OH
OL
Serial-data out reference level: V
/ V
OH OL
= 2 V/0.8 V.
are specified when the output is no longer driven.
8.
t
t
, t
, t
, and t
dis(CH), dis(RH) dis(G) dis(WL)
dis(SE)
32
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
timing requirements over recommended ranges of supply voltage and operating free-air
†
temperature
’55161-75
MIN MAX
’55161-80
MIN MAX
ALT.
SYMBOL
UNIT
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, read
t
140
140
188
48
88
140
24
10
20
55
75
13
20
9
150
150
200
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c(rd)
RC
Cycle time, write
t
WC
c(W)
Cycle time, read-modify-write
t
RMW
c(rdW)
c(P)
Cycle time, page-mode read, write
Cycle time, page-mode read-modify-write
Cycle time, transfer read
t
PC
t
90
c(RDWP)
c(TRD)
c(SC)
PRMW
t
150
30
RC
Cycle time, serial clock (see Note 9)
Pulse duration, CASx high
t
t
SCC
10
w(CH)
CPN
Pulse duration, CASx low (see Note 10)
Pulse duration, RAS high
t
10 000
10 000
20
10 000
10 000
w(CL)
CAS
t
60
w(RH)
RP
Pulse duration, RAS low (see Note 11)
Pulse duration, WE low
t
80
w(RL)
RAS
t
15
w(WL)
WP
Pulse duration, TRG low
20
w(TRG)
w(SCH)
w(SCL)
w(GH)
Pulse duration, SC high
t
10
SC
Pulse duration, SC low
t
9
10
SCP
Pulse duration, TRG high
t
20
20
TP
Pulse duration, RAS low (page mode)
Setup time, column address before CASx low
Setup time, DSF before CASx low
Setup time, row address before RAS low
Setup time, WE before RAS low
Setup time, DQ before RAS low
Setup time, TRG high before RAS low
Setup time, DSF low before RAS low
Setup time, data valid before CASx low
Setup time, data valid before WE low
Setup time, read command, WE high before CASx low
Setup time, early-write command, WE low before CASx low
Setup time, WE low before CASx high, write
Setup time, WE low before RAS high, write
Hold time, column address after CASx low
Hold time, DSF after CASx low
t
75 100 000
80 100 000
w(RL)P
su(CA)
su(SFC)
su(RA)
su(WMR)
su(DQR)
su(TRG)
su(SFR)
su(DCL)
su(DWL)
su(rd)
RASP
t
0
0
0
0
ASC
t
FSC
ASR
t
0
0
t
0
0
WSR
t
0
0
MS
t
0
0
THS
FSR
DSC
t
0
0
t
0
0
t
0
0
DSW
t
0
0
RCS
t
0
0
su(WCL)
su(WCH)
su(WRH)
h(CLCA)
h(SFC)
h(RA)
WCS
t
18
20
13
15
10
20
20
15
15
10
CWL
RWL
t
t
CAH
t
CFH
RAH
Hold time, row address after RAS low
t
†
Timing measurements are referenced to V MAX and V MIN.
IL
IH
NOTES: 9. Cycle time assumes t = 3 ns.
t
10. Inaread-modify-writecycle,t
andt
andt
mustbeobserved.Dependingonthetransitiontimes,thiscanrequireadditional
mustbeobserved.Dependingonthetransitiontimes,thiscanrequireadditional
d(CLWL)
su(WCH)
su(WRH)
CASx low time [t
].
w(CL)
11. Inaread-modify-writecycle,t
RAS low time [t ].
d(RLWL)
w(RL)
33
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
timing requirements over recommended ranges of supply voltage and operating free-air
†
temperature (continued)
’55161-75
’55161-80
ALT.
SYMBOL
UNIT
MIN MAX
MIN MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Hold time, TRG after RAS low
t
15
15
15
10
33
15
35
15
0
15
15
15
10
35
15
35
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
h(TRG)
h(RWM)
h(RDQ)
h(SFR)
h(RLCA)
h(CLD)
h(RLD)
h(WLD)
h(CHrd)
h(RHrd)
h(CLW)
h(RLW)
h(WLG)
h(SHSQ)
h(RSF)
h(CLQ)
THH
Hold time, write mask after RAS low
t
RWH
Hold time, DQ after RAS low (write-mask operation)
Hold time, DSF after RAS low
t
MH
t
RFH
Hold time, column address valid after RAS low (see Note 12)
Hold time, data valid after CASx low
t
AR
t
DH
Hold time, data valid after RAS low (see Note 12)
Hold time, data valid after WE low
t
DHR
t
DH
Hold time, read, WE high after CASx high (see Note 13)
Hold time, read, WE high after RAS high (see Note 13)
Hold time, write, WE low after CASx low
Hold time, write, WE low after RAS low (see Note 12)
Hold time, TRG high after WE low (see Note 14)
Hold time, SQ valid after SC high
t
t
RCH
0
0
RRH
t
t
15
35
10
2
15
35
10
2
WCH
WCR
t
OEH
t
SOH
Hold time, DSF after RAS low
t
35
0
35
0
FHR
Hold time, output valid after CASx low
t
DHC
t
75
13
0
80
15
0
CSH
t
ns
Delay time, RAS low to CASx high
d(RLCH)
(See Note 15)
t
CHR
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, CASx high to RAS low
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(CHRL)
d(CLRH)
d(CLWL)
d(RLCL)
d(CARH)
d(CACH)
d(RLWL)
d(CAWL)
d(CLRL)
d(RHCL)
d(CLGH)
d(GHD)
CRP
Delay time, CASx low to RAS high
20
48
20
50
RSH
Delay time, CASx low to WE low (see Notes 16 and 17)
Delay time, RAS low to CASx low (see Note 18)
Delay time, column address valid to RAS high
Delay time, column address valid to CASx high
Delay time, RAS low to WE low (see Note 16)
Delay time, column address valid to WE low (see Note 16)
Delay time, CASx low to RAS low (see Note 15)
Delay time, RAS high to CASx low (see Note 15)
Delay time, CASx low to TRG high for DRAM read cycles
Delay time, TRG high before data applied at DQ
t
CWD
t
20
38
38
100
63
0
50
20
40
40
105
65
0
60
RCD
t
RAL
t
CAL
t
RWD
t
AWD
t
CSR
RPC
t
0
0
20
15
20
15
t
OED
†
Timing measurements are referenced to V MAX and V MIN.
IL
NOTES: 12. The minimum value is measured when t
IH
is set to t
must be satisfied for a read cycle.
MIN as a reference.
d(RLCL)
d(RLCL)
13. Either t
or t
h(RHrd)
d(CHrd)
14. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle.
15. CBR refresh operation only
16. Read-modify-write operation only
17. TRG must disable the output buffers prior to applying data to the DQ pins.
18. The maximum value is specified only to assure RAS access time.
34
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
timing requirements over recommended ranges of supply voltage and operating free-air
†
temperature (continued)
’55161-75
’55161-80
ALT.
SYMBOL
UNIT
MIN
58
75
15
20
23
5
MAX
MIN
60
80
15
20
25
5
MAX
t
t
t
t
t
t
t
t
t
Delay time, RAS low to TRG high (see Note 19)
Delay time, RAS low to first SC high after TRG high (see Note 20)
Delay time, RAS low to column address valid
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(RLTH)
d(RLSH)
d(RLCA)
d(GLRH)
d(CLSH)
d(SCTR)
d(THRH)
d(THRL)
d(THSC)
RTH
RSD
RAD
ROH
t
t
35
40
Delay time, TRG low to RAS high
t
Delay time, CASx low to first SC high after TRG high (see Note 20)
Delay time, SC high to TRG high (see Notes 19 and 20)
Delay time, TRG high to RAS high (see Note 19)
Delay time, TRG high to RAS low (see Note 21)
Delay time, TRG high to SC high (see Note 19)
t
CSD
t
TSL
t
–10
55
18
–10
60
20
TRD
t
TRP
TSD
t
Delay time, RAS high to last (most significant) rising edge of SC before
boundary switch during split-register-transfer read cycles
t
20
20
ns
d(RHMS)
t
t
Delay time, CASx low to TRG high in real-time-transfer read cycles
Delay time, column address to first SC in early-load-transfer read cycles
t
t
15
28
15
30
ns
ns
d(CLTH)
CTH
d(CASH)
ASD
Delay time, column address to TRG high in real-time-transfer read
cycles
t
t
20
20
ns
d(CAGH)
ATH
t
t
Delay time, data to CASx low
Delay time, data to TRG low
t
0
0
0
0
ns
ns
d(DCL)
DZC
t
d(DGL)
DZO
Delay time, last (most significant) rising edge of SC to RAS low before
boundary switch during split-register-transfer read cycles
t
t
t
t
t
20
20
ns
ns
ns
ns
ns
d(MSRL)
Delay time, last (127 or 255) rising edge of SC to QSF switching at the
boundary during split-register-transfer read cycles (see Note 22)
t
28
33
28
73
30
35
30
75
d(SCQSF)
d(CLQSF)
d(GHQSF)
d(RLQSF)
SQD
Delay time, CASx low to QSF switching in transfer-read cycles
(see Note 22)
t
CQD
Delay time, TRG high to QSF switching in transfer-read cycles
(see Note 22)
t
TQD
Delay time, RAS low to QSF switching in transfer-read cycles
(see Note 22)
t
RQD
t
t
Refresh time interval, memory
Transition time
t
8
8
ms
ns
rf(MA)
REF
t
T
3
50
3
50
t
†
Timing measurements are referenced to V MAX and V MIN.
IL IH
NOTES: 19. Real-time-load transfer read or late-load-transfer read cycle only
20. Early-load-transfer read cycle only
21. Full-register-(read) transfer cycles only
22. Switching times for QSF output are measured with a load equivalent to one TTL load and 30 pF, and the output reference level is
/ V = 2 V/0.8 V.
V
OH OL
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
t
c(rd)
t
w(RL)
t
d(RLCH)
RAS
t
w(RH)
t
t
t
d(CLRH)
t
d(RLCL)
d(CHRL)
t
t
w(CL)
CASx
t
w(CH)
t
d(RLCA)
t
d(CARH)
t
h(RA)
t
h(RLCA)
t
t
d(CACH)
su(RA)
t
h(CLCA)
t
su(CA)
A0–A8
Row
Column
t
h(SFR)
t
su(SFR)
DSF
t
d(CLGH)
t
su(TRG)
t
d(GLRH)
t
t
w(TRG)
h(TRG)
TRG
t
h(RHrd)
t
su(rd)
t
h(CHrd)
WE
t
t
dis(CH)
t
dis(G)
d(DGL)
Data In
t
a(G)
Data Out
DQ0–DQ15
t
a(C)
t
a(CA)
t
a(R)
Figure 27. Read-Cycle Timing With CASx-Controlled Output
36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
t
c(rd)
t
w(RL)
d(RLCH)
t
RAS
t
w(RH)
t
t
t
d(CLRH)
t
d(RLCL)
t
t
w(CL)
d(CHRL)
CASx
t
w(CH)
t
d(RLCA)
t
d(CARH)
t
h(RA)
t
h(RLCA)
t
d(CACH)
t
su(RA)
t
h(CLCA)
t
su(CA)
A0–A8
Row
Column
t
h(SFR)
t
su(SFR)
DSF
t
d(CLGH)
t
t
d(GLRH)
su(TRG)
t
t
h(TRG)
w(TRG)
TRG
t
h(RHrd)
t
su(rd)
t
h(CHrd)
WE
t
t
dis(G)
d(DGL)
Data In
t
dis(RH)
t
a(G)
Data Out
DQ0–DQ15
t
a(C)
t
a(CA)
t
a(R)
Figure 28. Read-Cycle Timing With RAS-Controlled Output
37
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262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
t
c(W)
t
w(RL)
RAS
t
w(RH)
t
d(RLCH)
t
t
t
t
t
d(CLRH)
t
d(RLCL)
t
d(CHRL)
t
d(CHRL)
t
w(CL)
CASx
t
w(CH)
t
h(RLCA)
t
h(RA)
t
su(CA)
t
t
d(CACH)
h(CLCA)
t
t
d(RLCA)
su(RA)
t
d(CARH)
Row
Column
A0–A8
t
t
su(SFC)
su(SFR)
t
h(RSF)
t
t
h(SFC)
h(SFR)
DSF
t
h(TRG)
t
su(TRG)
TRG
t
t
su(WCH)
t
su(WMR)
su(WRH)
t
h(RLW)
t
h(CLW)
t
h(RWM)
t
su(WCL)
t
w(WL)
1
WE
t
su(DCL)
t
su(DQR)
t
h(CLD)
t
h(RDQ)
t
h(RLD)
2
3
DQ0–DQ15
Figure 29. Early-Write-Cycle Timing
Table 7. Early-Write-Cycle State Table
STATE
2
CYCLE
1
H
L
3
Write operation (nonmasked)
Don’t care
Write mask
Don’t care
Valid data
Valid data
Valid data
Write operation with nonpersistent write-per-bit
Write operation with persistent write-per-bit
L
38
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
t
c(W)
t
w(RL)
RAS
t
w(RH)
t
d(RLCH)
t
t
t
d(CLRH)
t
t
d(CHRL)
d(CHRL)
t
d(RLCL)
t
t
t
w(CL)
CASx
t
d(RLCA)
t
h(RLCA)
t
w(CH)
t
su(CA)
t
d(CACH)
t
h(RA)
t
h(CLCA)
t
su(RA)
t
d(CARH)
Row
Column
h(RSF)
A0–A8
t
t
t
su(SFR)
t
su(SFC)
t
h(SFC)
h(SFR)
DSF
TRG
t
su(rd)
t
su(WRH)
su(WCH)
h(CLW)
t
su(TRG)
t
t
t
d(GHD)
t
h(RLW)
t
su(WMR)
t
h(WLG)
t
h(RWM)
t
w(WL)
WE
1
t
su(DWL)
t
su(DQR)
t
h(WLD)
t
h(RDQ)
t
h(RLD)
2
3
DQ0–DQ15
Figure 30. Late-Write-Cycle Timing (Output-Enable-Controlled Write)
Table 8. Late-Write-Cycle State Table
STATE
CYCLE
1
H
L
2
3
Write operation (nonmasked)
Don’t care
Write mask
Don’t care
Valid data
Valid data
Valid data
Write operation with nonpersistent write-per-bit
Write operation with persistent write-per-bit
L
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
t
c(W)
t
w(RL)
RAS
t
w(RH)
t
d(RLCH)
t
t
t
d(CLRH)
t
t
t
d(RLCL)
t
d(CHRL)
t
d(CHRL)
t
w(CL)
CASx
t
w(CH)
t
h(RA)
Refresh Row
t
su(RA)
A0–A8
t
su(SFC)
t
su(SFR)
t
h(RSF)
t
h(SFR)
t
h(SFC)
DSF
TRG
t
h(TRG)
t
su(TRG)
t
su(WCH)
t
su(WMR)
t
su(WRH)
t
h(RLW)
t
t
h(CLW)
h(RWM)
t
su(WCL)
t
w(WL)
WE
t
su(DCL)
t
h(CLD)
t
h(RLD)
Write Mask
†
DQ0–DQ15
†
Load-write-mask-register cycle puts the device into the persistent write-per-bit mode.
Figure 31. Load-Write-Mask-Register-Cycle Timing (Early-Write Load)
40
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262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
t
c(W)
t
w(RL)
RAS
t
w(RH)
t
d(RLCH)
t
t
t
d(CLRH)
t
d(CHRL)
t
d(CHRL)
t
d(RLCL)
t
t
t
w(CL)
CASx
t
w(CH)
t
h(RA)
Refresh Row
t
su(RA)
A0–A8
t
h(RSF)
t
su(SFR)
t
t
su(SFC)
t
h(SFR)
h(SFC)
DSF
TRG
t
su(WRH)
su(WCH)
h(CLW)
t
t
su(TRG)
t
t
d(GHD)
t
h(RLW)
t
su(WMR)
t
h(WLG)
t
h(RWM)
t
w(WL)
WE
t
su(DWL)
t
h(WLD)
t
h(RLD)
†
Write Mask
DQ0–DQ15
†
Load-write-mask-register cycle puts the device into the persistent write-per-bit mode.
Figure 32. Load-Write-Mask-Register-Cycle Timing (Late-Write Load)
41
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262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
t
c(rdW)
w(RL)
t
t
d(RLCH)
RAS
t
w(RH)
t
d(CHRL)
t
t
d(CLRH)
t
d(RLCL)
d(CHRL)
t
w(CL)
CASx
t
h(RA)
t
w(CH)
t
su(CA)
t
h(CLCA)
t
h(RLCA)
t
t
d(CACH)
d(CARH)
su(RA)
t
t
d(RLCA)
A0–A8
Row
t
Column
t
h(RSF)
t
h(SFC)
su(SFR)
t
t
h(SFR)
su(SFC)
DSF
TRG
t
t
su(rd)
su(WCH)
t
h(TRG)
t
su(WRH)
t
d(CAWL)
t
w(TRG)
t
h(WLG)
t
h(RLW)
t
t
h(CLW)
su(TRG)
t
d(CLWL)
t
su(WMR)
t
d(DCL)
t
h(RWM)
t
d(CLGH)
t
w(WL)
1
2
WE
t
a(CA)
t
d(RLWL)
t
t
h(WLD)
t
d(GHD)
a(R)
t
t
d(DGL)
su(DQR)
t
t
t
a(C)
su(DWL)
h(RDQ)
Valid
Out
3
DQ0–DQ15
t
dis(G)
t
a(G)
Figure 33. Read-Write-/Read-Modify-Write-Cycle Timing
Table 9. Read-Write-/Read-Modify-Write-Cycle State Table
STATE
CYCLE
1
H
L
2
3
Write operation (nonmasked)
Don’t care
Write mask
Don’t care
Valid data
Valid data
Valid data
Write operation with nonpersistent write-per-bit
Write operation with persistent write-per-bit
L
42
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
t
w(RH)
t
w(RL)P
RAS
t
t
d(CLRH)
d(RLCL)
t
t
w(CH)
d(CHRL)
t
t
t
w(CL)
t
CASx
d(RLCA)
t
d(RLCH)
t
c(P)
t
t
su(RA)
t
su(CA)
d(CACH)
t
t
h(CLCA)
h(RA)
t
d(CARH)
t
h(RLCA)
Row
Column
Column
A0–A8
DSF
t
t
h(SFR)
d(CLGH)
t
su(SFR)
t
h(TRG)
t
su(TRG)
TRG
WE
t
su(WMR)
t
t
h(RHrd)
su(rd)
t
t
a(C)
h(CLQ)
t
t
dis(WL)
a(CA)
t
t
a(CA)
d(DGL)
t
t
a(G)
dis(RH)
(see Note A)
t
t
a(R)
(see Note B)
a(CP)
(see Note A)
t
dis(G)
Data Out
DQ0–
DQ15
Data Out
Data In
t
d(DCL)
or t
NOTES: A. Access time is t
dependent.
a(CA)
a(CP)
B. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
C. A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated and the proper polarity of DSF is selected on the falling edge of RAS and CASx to select the desired
write mode (normal, block write, etc.).
Figure 34. Enhanced-Page-Mode Read-Cycle Timing
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
t
w(RL)P
RAS
t
d(RLCH)
d(RLCL)
t
w(RH)
t
d(CLRH)
t
c(P)
t
t
w(CH)
t
w(CL)
t
t
d(CHRL)
d(CHRL)
t
CASx
t
d(RLCA)
t
su(CA)
t
h(CLCA)
su(RA)
t
t
h(RA)
d(CACH)
t
t
h(RLCA)
d(CARH)
Row
Column
Column
A0–
A8
t
su(SFR)
t
d(RSF)
t
h(SFC)
t
t
h(SFR)
h(SFC)
t
t
su(SFC)
su(SFC)
1
2
2
DSF
TRG
t
su(TRG)
t
h(TRG)
See Note A
t
su(WMR)
t
su(WCH)
t
su(WCH)
t
h(RWM)
t
su(WRH)
t
w(WL)
WE
3
t
(see Note B)
su(DWL)
t
su(DQR)
t
(see Note B)
t
h(CLD)
su(DCL)
(see Note B)
t
(see Note B)
h(WLD)
t
h(RDQ)
t
h(RLD)
DQ0–
DQ15
4
5
5
NOTES: A. Referenced to the first falling edge of CASx or the falling edge of WE, whichever occurs later
B. A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing
specifications. To ensure page-mode cycle time, TRG must remain high throughout the entire page-mode operation if the late write
featureisused. Iftheearlywrite-cycletimingisused, thestateofTRGisadon’tcareaftertheminimumperiodt
edge of RAS.
fromthefalling
h(TRG)
Figure 35. Enhanced-Page-Mode Write-Cycle Timing
Table 10. Enhanced-Page-Mode Write-Cycle State Table
STATE
CYCLE
1
L
L
L
2
L
L
L
3
H
L
4
5
Write operation (nonmasked)
Don’t care
Write mask
Don’t care
Valid data
Valid data
Valid data
Write operation with nonpersistent write-per-bit
Write operation with persistent write-per-bit
Load-writemaskoneitherthefirstfallingedgeofCASxorthe
L
H
L
H
Don’t care
Write mask
†
falling edge of WE, whichever occurs later.
†
Load-write-mask-register cycle puts the device in the persistent write-per-bit mode. Column address at the falling edge of CASx is a don’t care
during this cycle.
44
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
t
w(RL)P
RAS
t
w(RH
t
d(RLCH)
t
d(CLRH)
t
t
d(CHRL)
c(RDWP)
t
t
t
d(RLCL)
w(CH)
d(CHRL)
t
t
w(CL)
CASx
h(RA)
t
d(RLCA)
t
d(CARH)
d(CACH)
t
su(CA)
h(RLCA)
Column
t
t
t
su(RA)
h(CLCA)
t
Row
Column
A0–A8
DSF
t
h(SFR)
su(SFR)
t
h(SFC)
t
t
h(SFC)
t
su(SFC)
t
su(SFC)
1
2
2
t
su(rd)
t
t
su(WCH)
d(CLWL)
t
d(DCL)
t
d(CAWL)
t
d(CLGH)
t
d(RLWL)
t
t
t
h(TRG)
d(CLGH)
w(TRG)
su(WRH)
t
su(TRG)
t
TRG
WE
t
t
t
su(WCH)
t
w(TRG)
su(WMR)
t
w(WL)
h(RWM)
t
(see Note A)
3
a(C)
t
(see Note A)
t
a(CA)
su(DWL)
t
t
h(WLD)
su(DQR)
t
h(WLD)
t
d(DCL)
t
t
d(GHD)
5
t
su(DWL)
t
(see Note A)
h(RDQ)
a(CP)
DQ0–DQ15
4
Valid Out
5
t
(see Note A)
a(G)
t
Valid Out
d(DGL)
t
d(DGL)
t
dis(G)
(see Note A)
t
d(GHD)
(see Note A)
t
t
a(C)
a(R)
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are
not violated.
Figure 36. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing
Table 11. Enhanced-Page-Mode Read-Modify-Write-Cycle State Table
STATE
CYCLE
1
L
L
L
2
L
L
L
3
H
L
4
5
Write operation (nonmasked)
Don’t care
Write mask
Don’t care
Valid data
Valid data
Valid data
Write operation with nonpersistent write-per-bit
Write operation with persistent write-per-bit
Load write-mask register on either the first falling edge of
L
H
L
H
Don’t care
Write mask
†
CASx or the falling edge of WE, whichever occurs later.
†
Load-write-mask-register cycle puts the device in the persistent write-per-bit mode. Column address at the falling edge of CASx is a don’t care
during this cycle.
45
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
t
w(RH)
t
w(RL)P
RAS
t
t
d(CLRH)
d(RLCL)
t
t
w(CH)
t
t
t
d(CHRL)
w(CL)
t
d(RLCA)
CASx
t
d(RLCH)
t
c(P)
t
su(RA)
t
su(CA)
t
d(CACH)
t
t
h(CLCA)
h(RA)
t
t
d(CARH)
h(RLCA)
Row
Column
Column
A0–A8
DSF
t
t
h(SFR)
d(CLGH)
t
su(SFR)
t
su(WCL)
t
h(TRG)
t
t
su(TRG)
h(CLW)
TRG
WE
t
su(WMR)
t
su(rd)
t
w(WL)
t
a(C)
See Note A
t
a(CA)
t
t
h(CLD)
t
dis(WL)
d(DGL)
t
a(G)
t
a(R)
(see Note B)
t
su(DCL)
DQ0–
DQ15
Data Out
Data In
Data In
t
d(DCL)
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated and the proper polarity of DSF is selected on the falling edge of RAS and CASx to select the desired
write mode (normal, block write, etc.).
Figure 37. Enhanced-Page-Mode Read-/Write-Cycle Timing
46
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
t
c(W)
t
w(RL)
RAS
t
w(RH)
t
d(RLCH)
t
t
t
t
t
d(CLRH)
t
d(RLCL)
t
d(CHRL)
t
d(CHRL)
t
w(CL)
CASx
t
h(RA)
t
w(CH)
t
su(RA)
Refresh Row
A0–A8
t
h(SFC)
t
h(RSF)
t
t
su(SFR)
su(SFC)
t
h(SFR)
DSF
TRG
t
t
su(TRG)
t
h(TRG)
t
su(WCH)
su(WMR)
t
su(WRH)
t
h(RLW)
t
t
h(RWM)
h(CLW)
t
su(WCL)
WE
t
t
w(WL)
t
su(DCL)
h(CLD)
t
h(RLD)
DQ0–
DQ15
Valid Color Input
Figure 38. Load-Color-Register-Cycle Timing (Early-Write Load)
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PARAMETER MEASUREMENT INFORMATION
t
c(W)
t
w(RL)
RAS
t
w(RH)
t
d(RLCH)
t
t
t
t
t
d(CLRH)
t
t
d(RLCL)
d(CHRL)
t
d(CHRL)
t
w(CL)
CASx
t
t
h(RSF)
w(CH)
t
h(RA)
su(RA)
Refresh Row
t
A0–A8
t
t
su(SFR)
h(SFC)
t
su(SFC)
t
h(SFR)
DSF
TRG
t
su(TRG)
t
h(CLW)
t
su(WRH)
t
t
d(GHD)
su(WCH)
t
h(RLW)
t
su(WMR)
t
h(WLG)
t
w(WL)
WE
t
su(DWL)
t
h(WLD)
t
h(RLD)
DQ0–DQ15
Valid Color Input
Figure 39. Load-Color-Register-Cycle Timing (Late-Write Load)
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PARAMETER MEASUREMENT INFORMATION
t
c(W)
t
w(RL)
RAS
t
t
w(RH)
t
d(RLCH)
t
t
t
t
d(CLRH)
t
d(RLCL)
t
d(CHRL)
t
d(CHRL)
t
w(CL)
CASx
t
t
w(CH)
d(RLCA)
t
h(RLCA)
t
d(RLCA)
t
d(CARH)
t
t
su(RA)
d(CACH)
t
t
h(CLCA)
h(RA)
t
su(CA)
Row
A0–A8
t
t
h(RSF)
Block Address
A2–A8
su(SFR)
t
su(SFC)
t
h(SFR)
t
h(SFC)
DSF
t
t
h(TRG)
su(TRG)
TRG
t
su(WCH)
t
h(RWM)
t
su(WRH)
t
su(WMR)
t
su(WCL)
t
h(CLW)
t
h(RLW)
t
w(WL)
1
2
WE
t
h(RLD)
t
su(DCL)
t
su(DQR)
t
h(CLD)
t
h(RDQ)
3
DQ0–DQ15
Figure 40. Block-Write-Cycle Timing (Early Write)
Table 12. Block-Write-Cycle State Table
STATE
2
CYCLE
1
3
Block-write operation (nonmasked)
H
Don’t care
Write mask
Don’t care
Column mask
Column mask
Column mask
Block-write operation with nonpersistent write-per-bit
Block-write operation with persistent write-per-bit
L
L
Write-mask data 0: I/O write disable
1: I/O write enable
Example:
DQ0 — column 0 (address A1 = 0, A0 = 0)
DQ1 — column 1 (address A1 = 0, A0 = 1)
DQ2 — column 2 (address A1 = 1, A0 = 0)
DQ3 — column 3 (address A1 = 1, A0 = 1)
Column-mask data DQi – DQi + 3
0: column-write disable
(i = 0, 4, 8, 12) 1: column-write enable
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PARAMETER MEASUREMENT INFORMATION
t
c(W)
t
w(RL)
RAS
t
w(RH)
t
d(RLCH)
t
t
t
t
t
d(CLRH)
t
d(RLCL)
t
d(CHRL)
t
d(CHRL)
t
t
w(CL)
CASx
t
d(RLCA)
d(CACH)
t
w(CH)
t
h(RLCA)
t
d(CARH)
t
h(RA)
t
su(CA)
t
t
h(CLCA)
su(RA)
Row
A0–A8
t
h(RSF)
Block Address
A2–A8
t
h(SFC)
t
su(SFR)
t
su(SFC)
t
h(SFR)
DSF
TRG
t
su(TRG)
t
h(CLW)
t
su(WCH)
t
d(GHD)
t
h(RLW)
t
su(WRH)
t
su(WMR)
t
h(WLG)
t
h(RWM)
t
w(WL)
1
WE
t
su(DQR)
t
su(DWL)
t
t
h(RDQ)
h(WLD)
t
h(RLD)
3
2
DQ0–DQ15
Figure 41. Block-Write-Cycle Timing (Late Write)
Table 13. Block-Write-Cycle State Table
STATE
CYCLE
1
2
3
Block-write operation (nonmasked)
H
Don’t care
Write mask
Don’t care
Column mask
Column mask
Column mask
Block-write operation with nonpersistent write-per-bit
Block-write operation with persistent write-per-bit
L
L
Write-mask data 0: I/O write disable
1: I/O write enable
Example:
DQ0 — column 0 (address A1 = 0, A0 = 0)
DQ1 — column 1 (address A1 = 0, A0 = 1)
DQ2 — column 2 (address A1 = 1, A0 = 0)
DQ3 — column 3 (address A1 = 1, A0 = 1)
Column-mask data DQi – DQi + 3
0: column-write disable
(i = 0, 4, 8, 12) 1: column-write enable
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PARAMETER MEASUREMENT INFORMATION
t
w(RL)P
RAS
t
t
c(P)
t
d(RLCH)
d(RLCL)
w(RH)
t
t
d(CLRH)
t
w(CH)
t
t
t
d(CHRL)
d(CHRL)
t
w(CL)
CASx
t
d(RLCA)
t
t
d(CACH)
su(CA)
t
h(CLCA)
t
h(RA)
t
h(RLCA)
t
d(CARH)
su(RA)
Block Address
Block Address
A2–A8
Row
A0–A8
A2–A8
t
t
h(SFR)
t
h(SFC)
h(SFC)
t
t
su(SFC)
t
su(SFC)
su(SFR)
DSF
TRG
t
h(TRG)
su(TRG)
t
See Note A
su(WCH)
t
t
su(WMR)
su(WCH)
t
t
w(WL)
t
t
h(RWM)
su(WRH)
WE
1
t
(see Note A)
su(DWL)
t
(see Note A)
h(CLD)
t
su(DQR)
t
(see Note A)
h(WLD)
t
h(RDQ)
2
t
(see Note A)
su(DCL)
t
h(RLD)
DQ0–
DQ15
3
3
NOTES: A. Referenced to the first falling edge of CASx or the falling edge of WE, whichever occurs later
B. To ensure page-mode cycle time, TRG must remain high throughout the entire page-mode operation if the late-write feature is used.
If the early-write cycle timing is used, the state of TRG is a don’t care after the minimum period t
from the falling edge of RAS.
h(TRG)
Figure 42. Enhanced-Page-Mode Block-Write-Cycle Timing
Table 14. Enhanced-Page-Mode Block-Write-Cycle State Table
STATE
CYCLE
1
H
L
2
3
Block-write operation (nonmasked)
Don’t care
Write mask
Don’t care
Column mask
Column mask
Column mask
Block-write operation with nonpersistent write-per-bit
Block-write operation with persistent write-per-bit
L
Write-mask data
0: I/O write disable
1: I/O write enable
0: column-write disable
(i = 0, 4, 8, 12) 1: column-write enable
Example:
DQ0 — column 0 (address A1 = 0, A0 = 0)
DQ1 — column 1 (address A1 = 0, A0 = 1)
DQ2 — column 2 (address A1 = 1, A0 = 0)
DQ3 — column 3 (address A1 = 1, A0 = 1)
Column-mask data DQi – DQi + 3
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PARAMETER MEASUREMENT INFORMATION
t
c(rd)
t
w(RL)
RAS
t
t
t
w(RH)
t
t
d(RHCL)
t
d(CHRL)
d(CHRL)
CASx
t
h(RA)
t
su(RA)
Row
A0–A8
DSF
TRG
t
h(TRG)
t
su(TRG)
WE
DQ0–
DQ15
Figure 43. RAS-Only Refresh-Cycle Timing
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PARAMETER MEASUREMENT INFORMATION
t
c(rd)
t
t
w(RH)
w(RL)
RAS
t
d(RHCL)
t
t
t
d(CLRL)
t
d(RLCH)
CASx
t
d(CHRL)
t
t
t
t
su(RA)
h(RA)
1
2
A0–A8
su(SFR)
h(SFR)
DSF
TRG
t
t
h(RWM)
su(WMR)
3
WE
DQ0–DQ15
Figure 44. CBR-Refresh-Cycle Timing
Table 15. CBR-Cycle State Table
STATE
CYCLE
1
2
L
3
H
H
L
CBR refresh with option reset
CBR refresh with no reset
Don’t care
Don’t care
Stop address
H
H
CBR refresh with stop-point set and no reset
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PARAMETER MEASUREMENT INFORMATION
Memory Read Cycle
Refresh Cycle
Refresh Cycle
t
c(rd)
t
c(rd)
t
c(rd)
t
w(RH)
t
w(RH)
t
t
w(RL)
w(RL)
RAS
t
d(CARH)
t
d(RLCH)
t
d(CHRL)
t
t
t
w(CL)
CASx
t
d(RLCA)
t
su(RA)
t
su(RA)
t
h(CLCA)
t
t
su(CA)
h(RA)
t
h(RA)
t
h(RA)
t
t
su(RA)
t
t
h(RA)
su(RA)
Col
Row
1
1
2
1
2
A0–A8
DSF
t
su(SFR)
t
su(SFR)
su(SFR)
t
t
h(SFR)
t
h(SFR)
h(SFR)
2
t
h(RHrd)
t
dis(CH)
t
su(TRG)
t
t
dis(G)
h(TRG)
t
d(GLRH)
TRG
t
su(WMR)
t
t
su(WMR)
t
su(WMR)
su(rd)
t
h(RWM)
t
t
h(RWM)
h(RWM)
t
a(G)
WE
3
3
3
t
a(C)
t
a(R)
DQ0–DQ15
Data Out
Figure 45. Hidden-Refresh-Cycle Timing
Table 16. Hidden-Refresh-Cycle State Table
STATE
CYCLE
1
2
L
3
CBR refresh with option reset
CBR refresh with no reset
Don’t care
Don’t care
Stop address
H
H
L
H
H
CBR refresh with stop-point set and no option reset
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PARAMETER MEASUREMENT INFORMATION
t
c(TRD)
t
w(RL)
t
d(RLCL)
RAS
t
w(RH)
t
d(RLCH)
t
d(CHRL)
t
d(CARH)
t
w(CL)
t
CASx
d(RLCA)
t
h(RA)
t
su(CA)
t
h(CLCA)
t
su(RA)
t
h(RLCA)
Tap Point
A0–A8
Row
A0–A8
DSF
t
su(SFR)
t
h(SFR)
t
su(TRG)
t
h(TRG)
TRG
t
w(GH)
t
h(RWM)
t
t
su(WMR)
d(CASH)
WE
DQ0–DQ15
Hi-Z
t
d(SCTR)
t
d(CLSH)
t
t
w(SCL)
w(SCH)
t
d(RLSH)
SC
SQ
t
w(SCH)
t
t
c(SC)
a(SQ)
t
a(SQ)
t
t
h(SHSQ)
h(SHSQ)
Old Data
Old Data
New Data
t
d(GHQSF)
Tap Point Bit A7
QSF
SE
t
d(CLQSF)
H
L
t
d(RLQSF)
NOTES: A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register
transfer cycle is used to load the data registers in parallel from the memory array. The 256 locations in each data register are written
to from the 256 corresponding columns of the selected row.
B. Once data is transferred into the data registers, the SAM is in the serial-read mode, that is, the SQ is enabled, allowing data to be
shifted out of the registers. Also, the first bit to read from the data register after TRG has gone high must be activated by a positive
transition of SC.
C. A0 – A7: register tap point; A8: identifies the DRAM row half
D. Early-load operation is defined as t
h(TRG)
MIN < t
< t MIN.
h(TRG) d(RLTH)
Figure 46. Full-Register Transfer-Read Timing, Early-Load Operations
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PARAMETER MEASUREMENT INFORMATION
t
c(TRD)
t
w(RL)
t
d(RLCL)
RAS
t
w(RH)
t
d(RLCH)
t
d(CHRL)
t
w(CL)
CASx
t
d(RLCA)
t
h(RA)
t
su(CA)
t
su(RA)
t
h(RLCA)
t
h(CLCA)
Tap Point
A0–A8
Row
A0–A8
DSF
t
t
su(SFR)
h(SFR)
t
d(CLTH)
t
d(THRL)
d(THRH)
t
su(TRG)
t
t
d(CAGH)
t
d(RLTH)
TRG
WE
t
w(GH)
t
h(RWM)
t
su(WMR)
t
d(SCTR)
t
d(THSC)
DQ0–DQ15
SC
Hi-Z
t
w(SCH)
t
t
c(SC)
a(SQ)
t
w(SCL)
t
a(SQ)
t
t
h(SHSQ)
h(SHSQ)
Old Data
Old Data
Old Data
New Data
SQ
t
d(GHQSF)
QSF
SE
Tap Point Bit A7
t
H
L
d(CLQSF)
t
d(RLQSF)
NOTES: A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register
transfer cycle is used to load the data registers in parallel from the memory array. The 256 locations in each data register are written
to from the 256 corresponding columns of the selected row.
B. Once data is transferred into the data registers, the SAM is in the serial-read mode, that is, the SQ is enabled, allowing data to be
shifted out of the registers. Also, the first bit to read from the data register after TRG has gone high must be activated by a positive
transition of SC.
C. A0–A7: register tap point; A8: identifies the DRAM row half
D. Late load operation is defined as t
< 0 ns.
d(THRH)
Figure 47. Full-Register Transfer Read-Timing, Real-Time Load Operation/Late-Load Operation
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PARAMETER MEASUREMENT INFORMATION
t
c(TRD)
t
w(RL)
t
w(RH)
t
d(RLCL)
RAS
CASx
t
t
d(CHRL)
t
t
w(CH)
d(RLCH)
t
t
d(RLCA)
w(CL)
t
su(CA)
t
h(RA)
t
su(RA)
h(CLCA)
A0–A8
Tap Point A0–A8
See Note A
Row
t
su(TRG)
t
h(TRG)
TRG
DSF
t
h(SFR)
t
su(SFR)
t
h(RWM)
t
su(WMR)
WE
DQ0–
DQ15
HI-Z
t
d(MSRL)
t
d(RHMS)
t
c(SC)
t
t
c(SC)
w(SCH)
t
w(SCL)
Bit 127
or 255
Tap
Point M
Bit 255
or 127
Tap
Point N
SC
SQ
t
t
a(SQ)
t
t
a(SQ)
t
a(SQ)
w(SCL)
h(SHSQ)
Bit 127 or
Bit 255
Bit 127 or
Bit 255
Bit 126 or
Bit 254
Tap
Point N
Tap Point M
t
t
a(SQ)
d(SCQSF)
t
d(SCQSF)
New MSB
MSB Old
QSF
SE
H
L
NOTE A: A0–A6: tap point of the given half; A7: don’t care; A8: identifies the DRAM row half
Figure 48. Split-Register-Transfer-Read Timing
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PARAMETER MEASUREMENT INFORMATION
RAS
TRG
t
su(TRG)
t
h(TRG)
t
c(SC)
t
t
w(SCH)
c(SC)
t
w(SCH)
t
w(SCH)
t
w(SCL)
t
w(SCL)
SC
t
a(SQ)
t
a(SQ)
t
a(SQ)
t
h(SHSQ)
t
h(SHSQ)
t
h(SHSQ)
SQ
SE
Valid Out
Valid Out
Valid Out
t
a(SE)
NOTES: A. Whilethe data is being read through the serial-data register, TRG is a don’t care; however, TRG must be held high when RAS goes
low. This is to avoid the initiation of a register-data transfer operation.
B. The serial data-out cycle is used to read data out of the data registers. Before data can be read via SQ, the device must be put
into the read mode by performing a transfer-read cycle.
Figure 49. Serial-Read-Cycle Timing (SE = V )
IL
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SGMS056D – MAY 1995 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
RAS
TRG
t
su(TRG)
t
h(TRG)
t
c(SC)
t
c(SC)
t
w(SCH)
t
w(SCH)
t
w(SCH)
t
w(SCL)
t
w(SCL)
SC
t
a(SQ)
t
a(SQ)
t
a(SQ)
t
h(SHSQ)
t
a(SE)
t
h(SHSQ)
SQ
SE
Valid Out
Valid Out
Valid Out
Valid Out
t
dis(SE)
NOTES: A. While the data is being read through the serial-data register, TRG is a don’t care; however, TRG must be held high when RAS goes
low. This is to avoid the initiation of a register-data transfer operation.
B. The serial data-out cycle is used to read data out of the data registers. Before data can be read via SQ, the device must be put into
the read mode by performing a transfer-read cycle.
Figure 50. Serial-Read Timing (SE-Controlled Read)
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PARAMETER MEASUREMENT INFORMATION
RAS
CAS
ADDR
Row Tap1
(low)
RowTap1
(high)
Row Tap2
(low)
Row Tap2
(high)
TRG
DSF
CASE I
SC
Tap1
(low)
Bit Tap1
127 (high)
Bit
255
Tap2
(low)
Bit
127
QSF
CASE II
SC
Tap1
(high)
Tap1
(low)
Bit
127
Bit
255
Tap2
(low)
Bit
127
QSF
CASE III
SC
Tap1
(low)
Bit
Tap1
Bit
255
Tap2
(low)
Bit
127
127 (high)
QSF
Split Register to the
High Half of the
Data Register
Split Register to the
Low Half of the
Data Register
Split Register to the
High Half of the
Data Register
Full-Register-Transfer Read
NOTES: A. To achieve proper split-register operation, a full-register-transfer read must be performed before the first split-register-transfer
cycle. This is necessary to initialize the data register and the starting tap location. First serial access can begin either after the
full-register-transfer-read cycle (CASE I), during the first split-register-transfer cycle (CASE II), or even after the first
split-register-transfer cycle (CASE III). There is no minimum requirement of SC clock between the full-register transfer-read cycle
and the first split-register cycle.
B. A split-register transfer into the inactive half is not allowed until t
is met. t
is the minimum delay time between the
d(MSRL)
d(MSRL)
rising edge of the serial clock of the last bit (bit 127 or 255) and the falling edge of RAS of the split-register-transfer cycle into the
inactive half. After the t requirement is met, the split-register transfer into the inactive half must also satisfy the minimum
d(MSRL)
requirement. t
t
istheminimumdelaytimebetweentherisingedgeofRASofthesplit-register-transfercycleinto
d(RHMS)
d(RHMS)
the inactive half and the rising edge of the serial clock of the last bit (bit 127 or 255).
Figure 51. Split-Register Operating Sequence
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MECHANICAL DATA
GB (S-CPGA-P68)
CERAMIC PIN GRID ARRAY PACKAGE
0.970 (24,63)
0.950 (24,13)
0.536 (13,61)
0.524 (13,31)
0.800 (20,32) TYP
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
0.088 (2,23)
0.072 (1,83)
0.100 (2,54)
0.194 (4,98)
0.166 (4,16)
0.055 (1,39)
0.045 (1,14)
0.050 (1,27) DIA
4 Places
0.018 (0,46) DIA TYP
4040114-14/A 2/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Index mark may appear on top or bottom depending on package vendor.
D. Pins are located within 0.005 (0,13) radius of true position relative to each other at maximum material condition and within
0.015 (0,38) radius relative to the center of the ceramic.
E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit.
F. The pins can be gold plated or solder dipped.
G. Falls within MIL-STD-1835 CMGA1-PN and CMGA13-PN and JEDEC MO-067AA and MO-066AA, respectively
61
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
MECHANICAL DATA
HKC (R-CDFP-F64)
CERAMIC DUAL FLATPACK WITH TIE BAR
1.620 (41,14)
SQ
1.580 (40,13)
1.020 (25,91)
0.980 (24,89)
0.765 (19,43)
0.730 (18,54)
0.026 (0,66) MIN
0.150 (3,81)
0.100 (2,54)
0.070 (1,78)
0.055 (1,40)
33
64
0.445 (11,30)
0.420 (10,67)
32
1
0.320 (8,13)
0.295 (7,49)
0.0098 (0,250)
0.0060 (0,150)
0.185 (4,70)
0.145 (3,68)
0.0079 (0,200)
0.0043 (0,110)
0.0196 (0,500)
0.040 (1,02)
0.030 (0,76)
4073160/B 10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. All leads not shown for clarity purposes.
device symbolization
-SS
Speed (-70, -80)
SMJ55161 HKC M
Temperature Range
Package Code
F
R
A
XXX LLL
Lot Traceability Code
Date Code
Assembly Site Code
Die Revision Code
Wafer Fab Code
62
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
63
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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