SN54ABT162500_08 [TI]
18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS;型号: | SN54ABT162500_08 |
厂家: | TEXAS INSTRUMENTS |
描述: | 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 输出元件 |
文件: | 总9页 (文件大小:138K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN54ABT162500, SN74ABT162500
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999
SN54ABT162500 . . . WD PACKAGE
SN74ABT162500 . . . DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
B-Port Outputs Have Equivalent 25-Ω
Series Resistors, So No External Resistors
Are Required
OEAB
LEAB
A1
GND
A2
GND
CLKAB
B1
GND
B2
1
2
3
4
5
6
7
8
9
56
55
54
53
52
51
50
49
48
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
UBT (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
A3
B3
V
V
CC
CC
A4
A5
B4
B5
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
A6 10
47 B6
= 5 V, T = 25°C
CC
A
GND
A7
GND
B7
11
12
46
45
High-Impedance State During Power Up
and Power Down
A8 13
A9 14
44 B8
Flow-Through Architecture Optimizes PCB
Layout
43 B9
A10 15
A11 16
A12 17
GND 18
A13 19
42 B10
41 B11
40 B12
39 GND
38 B13
Latch-Up Performance Exceeds 500 mA
Per JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
A14
A15 21
22
20
37
B14
36 B15
35
Package Options Include Plastic Shrink
Small-Outline (DL) Package and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
V
V
CC
CC
A16 23
A17 24
34 B16
33 B17
GND 25
A18 26
32 GND
31 B18
description
OEBA 27
LEBA 28
30 CLKBA
29 GND
These 18-bit universal bus transceivers combine
D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs.
For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the
A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the
latch/flip-flop on the high-to-low transition of CLKAB. Output-enable OEAB is active high. When OEAB is high,
the outputs are active. When OEAB is low, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors
to reduce overshoot and undershoot.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162500, SN74ABT162500
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999
description (continued)
When V
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V
through a pullup resistor
CC
and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by
the current-sinking/current-sourcing capability of the driver.
The SN54ABT162500 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT162500 is characterized for operation from –40°C to 85°C.
†
FUNCTION TABLE
INPUTS
OUTPUT
B
OEAB
LEAB
CLKAB
A
X
L
L
X
H
H
L
X
X
X
↓
Z
L
H
H
H
H
H
H
H
L
H
L
L
↓
H
X
X
H
‡
B
0
§
B
0
L
H
L
L
†
‡
§
A-to-B data flow is shown: B-to-A flow is similar but
uses OEBA, LEBA, and CLKBA.
Output level before the indicated steady-state input
conditions were established
Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was low before LEAB went low
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162500, SN74ABT162500
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999
†
logic symbol
1
OEAB
CLKAB
LEAB
EN1
2C3
55
2
C3
G2
27
30
28
EN4
OEBA
CLKBA
LEBA
5C6
C6
G5
3
54
A1
3D
4
1
1
1
B1
6D
5
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
A2
A3
B2
6
B3
8
A4
B4
9
A5
B5
10
12
13
14
15
16
17
19
20
21
23
24
26
A6
B6
A7
B7
A8
B8
A9
B9
A10
A11
A12
A13
A14
A15
A16
A17
A18
B10
B11
B12
B13
B14
B15
B16
B17
B18
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162500, SN74ABT162500
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999
logic diagram (positive logic)
1
OEAB
55
CLKAB
2
LEAB
28
LEBA
30
CLKBA
27
OEBA
3
A1
1D
C1
54
B1
CLK
1D
C1
CLK
To 17 Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABT162500 (A port) . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABT162500 (A port) . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162500, SN74ABT162500
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999
recommended operating conditions (see Note 3)
SN54ABT162500 SN74ABT162500
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
CC
V
IH
V
IL
V
I
Supply voltage
5.5
5.5
V
V
V
V
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
0
V
CC
0
V
CC
A port
–24
–12
48
–32
–12
64
I
High-level output current
Low-level output current
mA
mA
OH
OL
B port
A port
I
B port
12
12
∆t/∆v
∆t/∆V
Input transition rise or fall rate
Power-up ramp rate
Outputs enabled
10
10
ns/V
µs/V
°C
200
–55
200
–40
CC
T
A
Operating free-air temperature
125
85
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162500, SN74ABT162500
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT162500 SN74ABT162500
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
I
I
I
I
I
I
I
I
I
I
I
= –3 mA
= –3 mA
= –24 mA
= –32 mA
= –1 mA
= –1 mA
= –3 mA
= –12 mA
= 48 mA
= 64 mA
= 12 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OH
OH
OH
OH
OL
OL
OL
A port
2
2
V
CC
= 4.5 V
2*
2
3.35
3.85
3.1
V
OH
V
V
V
= 4.5 V,
= 5 V,
3.35
3.85
3.1
2.6
3.3
3.8
3
CC
CC
B port
V
CC
= 4.5 V
2.6
0.55
0.55*
0.8
0.55
0.8
A port
B port
V
V
= 4.5 V
= 4.5 V,
CC
V
V
0.55
0.8
V
OL
CC
100
mV
µA
hys
Control inputs
A or B ports
V
V
= 0 to 5.5 V, V = V
I
or GND
CC
±1
±1
±1
CC
I
I
= 2.1 V to 5.5 V,
CC
±20
±20
±20
V = V
I
or GND
CC
V
V
= 0 to 2.1 V,
= 0.5 V to 2.7 V, OE or OE = X
CC
O
±50
±50
10
±50
±50
10
±50
±50
10
µA
µA
µA
I
I
I
OZPU
§
§
V
V
= 2.1 V to 0,
= 0.5 V to 2.7 V, OE or OE = X
CC
O
OZPD
V
V
= 2.1 V to 5.5 V,
= 2.7 V, OE ≥ 2 V or OE ≤ 0.8 V
CC
O
‡
OZH
V
V
= 2.1 V to 5.5 V,
= 0.5 V, OE ≥ 2 V or OE ≤ 0.8 V
CC
O
‡
–10
±100
50
–10
–10
±100
50
µA
µA
µA
I
I
I
OZL
V
CC
= 0,
V or V ≤ 4.5 V
I O
off
V
V
= 5.5 V,
= 5.5 V
CC
O
Outputs high
50
CEX
A port
B port
–50
–25
–110
–55
–180
–90
3
–50
–25
–180
–90
3
–50
–25
–180
–90
3
¶
V
= 5.5 V,
V
= 2.5 V
mA
I
CC
O
O
Outputs high
Outputs low
V
I
= 5.5 V,
= 0,
CC
O
I
A or B ports
36
3
36
3
36
3
mA
CC
V = V
or GND
I
CC
Outputs disabled
V
= 5.5 V, One input at 3.4 V,
CC
Other inputs at V
#
50
50
50
µA
∆I
CC
or GND
CC
Control inputs V = 2.5 V or 0.5 V
C
C
3
9
pF
pF
i
I
A or B ports
V
O
= 2.5 V or 0.5 V
io
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
‡
§
¶
#
All typical values are at V
= 5 V.
CC
and I
The parameters I
include the input leakage current.
OZH
OZL
For V
between 2.1 V and 4 V, OE should be less than or equal to 0.5 V to ensure a low state.
CC
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162500, SN74ABT162500
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABT162500 SN74ABT162500
UNIT
MIN
MAX
MIN
MAX
f
t
Clock frequency
Pulse duration
150
150
MHz
ns
clock
LEAB or LEBA high
CLKAB or CLKBA high or low
A before CLKAB↓
2.5
3
2.5
3
w
3.3
3.3
1
3.3
3.3
1
B before CLKBA↓
t
t
Setup time
Hold time
ns
ns
su
CLK high
CLK low
A before LEAB↓ or B before LEBA↓
2.5
0
2.5
0
A after CLKAB↓ or B after CLKBA↓
A after LEAB↓ or B after LEBA↓
h
2
2
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
V
T
= 5 V,
= 25°C
CC
A
SN54ABT162500 SN74ABT162500
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
150
1.5
2
TYP
200
2.6
3.4
3.3
3.8
3.7
3.8
3.4
3.8
4.5
3.8
MAX
MIN
150
1.5
2
MAX
MIN
150
1.5
2
MAX
f
t
t
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
4
5.2
4.8
5.2
4.9
5.2
4.6
4.7
5.7
5.3
5.1
6.1
6.1
6.4
6.4
6.4
5.6
5.6
6.9
6.3
4.8
5.7
5.6
5.9
5.9
6
A or B
B or A
B or A
B or A
B or A
B or A
2
2
2
LEAB or LEBA
CLKAB or CLKBA
OEAB or OEBA
OEAB or OEBA
ns
ns
ns
ns
2
2
2
1.5
1.5
1.5
2
1.5
1.5
1.5
2
1.5
1.5
1.5
2
5.3
5.4
6.5
5.8
2
2
2
1.5
1.5
1.5
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162500, SN74ABT162500
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS242E – JUNE 1992 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
7 V
PLH PHL
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
Open
L
PHZ PZH
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
t
t
t
PLZ
PLH
PHL
PZL
Output
Waveform 1
S1 at 7 V
3.5 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
t
t
PLH
PZH
PHZ
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright 1999, Texas Instruments Incorporated
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