SN54ABT162823 [TI]
18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS; 18位总线接口触发器具有三态输出
| 型号： | SN54ABT162823 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS |
| 文件： | 总8页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ABT162823, SN74ABT162823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS473B – JUNE 1994 – REVISED JANUARY 1997
SN54ABT162823 . . . WD PACKAGE
SN74ABT162823 . . . DL PACKAGE
(TOP VIEW)
Output Ports Have Equivalent 25-Ω Series
Resistors So No External Resistors Are
Required
Members of the Texas Instruments
Widebus Family
1CLR
1OE
1Q1
GND
1Q2
1Q3
1CLK
1CLKEN
1D1
GND
1D2
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
3
4
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
5
1D3
6
V
V
7
CC
CC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
8
Typical V
(Output Ground Bounce) < 1 V
OLP
9
at V
= 5 V, T = 25°C
CC
A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
Flow-Through Architecture Optimizes PCB
Layout
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center
Spacings
description
V
V
These 18-bit bus-interface flip-flops feature
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads. They are particularly suitable for
implementing wider buffer registers, I/O ports,
bidirectional bus drivers with parity, and working
registers.
CC
CC
2Q7
2Q8
GND
2Q9
2OE
2CLR
2D7
2D8
GND
2D9
2CLKEN
2CLK
The ’ABT162823 can be used as two 9-bit
flip-flops or one 18-bit flip-flop. With the
clock-enable (CLKEN) input low, the D-type
flip-flops enter data on the low-to-high transitions
of the clock. Taking CLKEN high disables the
clock buffer, thus latching the outputs. Taking the
clear (CLR) input low causes the Q outputs to go
low independently of the clock.
A buffered output-enable (OE) input places the nine outputs in either a normal logic state (high or low logic level)
or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be
retained or new data can be entered while the outputs are in the high-impedance state.
The outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors to
reduce overshoot and undershoot.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162823, SN74ABT162823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS473B – JUNE 1994 – REVISED JANUARY 1997
description (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT162823 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT162823 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 9-bit flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLR CLKEN CLK
D
X
H
L
L
H
H
H
H
X
X
L
X
↑
L
H
L
L
L
L
↑
L
L
L
X
X
X
X
X
Q
Q
0
0
L
H
X
H
Z
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162823, SN74ABT162823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS473B – JUNE 1994 – REVISED JANUARY 1997
†
logic symbol
2
EN1
R2
1OE
1CLR
1
55
56
27
28
30
29
G3
1CLKEN
1CLK
3C4
EN5
R6
2OE
2CLR
2CLKEN
2CLK
G7
7C8
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
3
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
4D
1Q1
5
1, 2
1Q2
6
1Q3
8
1Q4
9
1Q5
10
1Q6
12
1Q7
13
1Q8
14
1Q9
15
8D
2Q1
16
5, 6
2Q2
17
2Q3
19
2Q4
20
2Q5
21
2Q6
23
2Q7
24
2Q8
26
2Q9
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162823, SN74ABT162823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS473B – JUNE 1994 – REVISED JANUARY 1997
logic diagram (positive logic)
2
1OE
1
1CLR
55
1CLKEN
CE
R
56
3
1CLK
C1
1Q1
54
1D1
1D
To Eight Other Channels
27
2OE
28
2CLR
30
2CLKEN
CE
R
29
15
2CLK
C1
2Q1
42
2D1
1D
To Eight Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Package thermal impedance,
Storage temperature range, T
(see Note 2): DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
JA
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162823, SN74ABT162823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS473B – JUNE 1994 – REVISED JANUARY 1997
recommended operating conditions (see Note 3)
SN54ABT162823 SN74ABT162823
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
CC
0
V
CC
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–12
12
–12
12
mA
mA
ns/V
°C
OH
OL
∆t/∆v
Outputs enabled
10
10
T
–55
125
–40
85
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT162823 SN74ABT162823
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
I
I
I
I
I
I
= – 1 mA
= – 1 mA
= – 3 mA
= – 12 mA
= 8 mA
3.35
3.85
3.1
3.35
3.85
3.1
3.35
3.85
3.1
OH
OH
OH
OH
OL
OL
V
OH
V
V
= 4.5 V
= 4.5 V
CC
CC
2.6*
2.6
0.4
0.8
0.8
0.65
0.8
V
V
V
V
OL
= 12 mA
100
mV
µA
µA
µA
µA
µA
mA
hys
I
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 0,
V = V or GND
I CC
±1
10
±1
10
±1
10
I
V
V
= 2.7 V
= 0.5 V
OZH
OZL
off
O
–10
±100
50
–10
–10
±100
50
O
V or V ≤ 4.5 V
I
O
= 5.5 V,
= 5.5 V,
V
= 5.5 V
Outputs high
50
–100
2
CEX
O
O
‡
V
= 2.5 V
–25
–55 –100
–25
–25
–100
2
O
Outputs high
Outputs low
2
80
2
V
= 5.5 V, I = 0,
O
CC
I
80
80
mA
CC
V = V
I
or GND
CC
Outputs disabled
2
2
V
= 5.5 V, One input at 3.4 V,
CC
Other inputs at V
§
∆I
CC
1.5
1.5
1.5
mA
or GND
CC
V = 2.5 V or 0.5 V
C
C
3
8
pF
pF
i
I
V
O
= 2.5 V or 0.5 V
o
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
‡
§
All typical values are at V
= 5 V.
CC
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL-voltage level rather than V or GND.
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162823, SN74ABT162823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS473B – JUNE 1994 – REVISED JANUARY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
V
T
= 5 V,
= 25°C
CC
A
SN54ABT162823 SN74ABT162823
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
t
Clock frequency
Pulse duration
150
150
150
MHz
ns
clock
CLR low
3.3
3.3
1.6
1.7
2.8
1.2
0.6
3.3
3.3
2
3.3
3.3
1.6
1.7
2.8
1.2
0.6
w
CLK high or low
CLR inactive
Data
t
1.7
2.8
1.2
0.6
ns
ns
Setup time before CLK↑
Hold time after CLK↑
su
h
CLKEN low
Data
t
CLKEN low
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
V
T
= 5 V,
= 25°C
CC
A
SN54ABT162823 SN74ABT162823
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
150
2.3
2.8
2.8
1.7
3
TYP
MAX
MIN
150
2.3
2.8
2.8
1.7
3
MAX
MIN
150
2.3
2.8
2.8
1.7
3
MAX
f
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PHL
PZH
PZL
PHZ
PLZ
4.6
4.6
5
6.2
6.1
6.2
4.9
6.1
6.1
6.7
8.4
7.1
7.5
6.7
7
CLK
CLR
OE
Q
Q
Q
7.2
ns
3.8
5
5.8
5.6
7
ns
7.2
2.7
1.9
4.8
4.6
2.7
1.9
7.3
2.7
1.9
6.6
9
Q
ns
OE
10.2
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162823, SN74ABT162823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS473B – JUNE 1994 – REVISED JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
7 V
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
7 V
PLH PHL
/t
C
= 50 pF
L
t
500 Ω
PLZ PZL
/t
(see Note A)
Open
PHZ PZH
LOAD CIRCUIT
3 V
0 V
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
Input
1.5 V
1.5 V
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
S1 at 7 V
V
V
3.5 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
– 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
t
PZH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明