SN54ABT16260WD [TI]
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES WITH 3-STATE OUTPUTS; 12位至24位复用D型锁存器与三态输出
| 型号： | SN54ABT16260WD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| 文件： | 总8页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ABT16260, SN74ABTH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS204C – JUNE 1992 – REVISED MAY 1997
SN54ABT16260 . . . WD PACKAGE
SN74ABTH16260 . . . DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
OEA
LE1B
2B3
GND
2B2
OE2B
LEA2B
2B4
GND
2B5
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
2
3
4
5
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
2B1
2B6
6
V
V
7
CC
CC
Typical V
(Output Ground Bounce) < 1 V
OLP
A1
A2
A3
GND
A4
A5
A6
A7
A8
2B7
2B8
2B9
8
at V
= 5 V, T = 25°C
CC
A
9
High-Impedance State During Power Up
and Power Down
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
Flow-Through Architecture Optimizes PCB
Layout
High-Drive Outputs (–32-mA I , 64-mA I
)
OH
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
OL
A9
GND
A10
A11
A12
1B8
1B7
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center
Spacings
V
V
CC
CC
1B1
1B2
GND
1B3
LE2B
SEL
1B6
1B5
GND
1B4
LEA1B
OE1B
description
The SN54ABT16260 and SN74ABTH16260 are
12-bit to 24-bit multiplexed D-type latches used in
applications in which two separate data paths
must be multiplexed onto, or demultiplexed from,
a single data path. Typical applications include
multiplexing and/or demultiplexing of address and
data
information
in
microprocessor
or
bus-interface applications. This device is also
useful in memory-interleaving applications.
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are available for address and/or data transfer. The
output-enable (OE1B, OE2B, and OEA) inputs control the bus-transceiver functions. The OE1B and OE2B
control signals also allow bank control in the A-to-B direction.
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B,
LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the
latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains
latched until the latch-enable input is returned high.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16260, SN74ABTH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS204C – JUNE 1992 – REVISED MAY 1997
description (continued)
When V
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ABT16260 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABTH16260 is characterized for operation from –40°C to 85°C.
Function Tables
B TO A (OEB = H)
INPUTS
OUTPUT
A
1B
H
L
2B
X
SEL LE1B LE2B OEA
H
H
H
L
H
H
L
X
X
X
H
H
L
L
L
L
L
L
L
H
H
L
X
X
X
A
0
X
H
L
X
X
X
X
H
X
L
L
X
X
L
A
0
X
X
X
X
Z
A TO B (OEA = H)
INPUTS
LEA1B LEA2B OE1B OE2B
OUTPUTS
A
H
L
1B
2B
H
H
H
H
H
L
H
H
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
L
L
H
L
L
H
L
H
L
2B
2B
H
0
L
0
H
L
H
H
L
1B
0
1B
0
1B
0
Z
L
L
X
X
X
X
X
L
2B
Z
0
X
X
X
X
X
X
X
X
Active
Z
Z
Active
Active
Active
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16260, SN74ABTH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS204C – JUNE 1992 – REVISED MAY 1997
logic diagram (positive logic)
2
LE1B
27
LE2B
30
LEA1B
55
LEA2B
56
OE2B
29
OE1B
1
OEA
28
SEL
C1
1D
G1
1
8
23
A1
1B1
1
C1
6
2B1
1D
C1
1D
C1
1D
To 11 Other Channels
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16260, SN74ABTH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS204C – JUNE 1992 – REVISED MAY 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABT16260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABTH16260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABT16260 SN74ABTH16260
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
0
V
CC
V
I
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
–24
48
–32
64
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
–55
200
–40
CC
T
Operating free-air temperature
125
85
A
NOTE 3: Unused control inputs must be held high or low to prevent them from floating.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16260, SN74ABTH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS204C – JUNE 1992 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT16260 SN74ABTH16260
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
= 4.5 V,
= 5 V,
I
I
I
I
I
I
= –3 mA
= –3 mA
= –24 mA
= –32 mA
= 48 mA
= 64 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
2
2
V
= 4.5 V
= 4.5 V
CC
CC
2*
2
0.36
100
0.5
V
V
V
V
OL
0.55*
0.55
mV
hys
Control
inputs
V
= 0 to 5.5 V,
CC
±1
±1
±1
V = V
I
or GND
CC
I
µA
µA
I
V
= 2.1 V to 5.5 V,
or GND
CC
CC
V = V
A or B ports
A or B ports
±20
±100
±20
I
V = 0.8 V
100
100
I
I
V
CC
= 4.5 V
I(hold)
V = 2 V
I
–100
–100
V
V
= 0 to 2.1 V,
= 0.5 V to 2.7 V, OE = X
CC
O
‡
±50
±50
10
±50
±50
10
±50
±50
10
µA
µA
µA
I
I
I
OZPU
V
V
= 2.1 V to 0,
= 0.5 V to 2.7 V, OE = X
CC
O
‡
OZPD
V
V
= 2.1 V to 5.5 V,
= 2.7 V, OE ≥ 2 V
CC
O
§
OZH
V
V
= 2.1 V to 5.5 V,
= 0.5 V, OE ≥ 2 V
CC
O
§
I
I
I
I
–10
±100
50
–10
–10
±100
50
µA
µA
µA
mA
OZL
V
CC
= 0,
V or V ≤ 4.5 V
I O
off
V
V
= 5.5 V,
= 5.5 V
CC
O
Outputs high
= 2.5 V
50
CEX
¶
V
CC
= 5.5 V,
V
O
–50
–100
–225
1.5
63
–50
–225
1.5
63
–50
–225
1.5
63
O
Outputs high
Outputs low
V
I
= 5.5 V,
= 0,
CC
O
I
mA
CC
V = V
I
or GND
CC
Outputs disabled
1
1
1
V
= 5.5 V, One input at 3.4 V,
CC
Other inputs at V
#
1.5
1.5
1.5
mA
∆I
CC
or GND
CC
V = 2.5 V or 0.5 V
C
C
3
pF
pF
i
I
V
O
= 2.5 V or 0.5 V
11.5
io
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
‡
§
¶
#
All typical values are at V
= 5 V.
CC
This parameter is characterized, but not production tested.
The parameters I and I include the input leakage current.
OZH
OZL
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16260, SN74ABTH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS204C – JUNE 1992 – REVISED MAY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
V
T
A
= 5 V,
CC
= 25°C
SN54ABT16260 SN74ABTH16260
†
UNIT
MIN
3.3
1.5
1
MAX
MIN
3.3
2
MAX
MIN
3.3
1.5
1
MAX
t
w
t
su
t
h
Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high
Setup time, data before LE1B, LE2B, LEA1B, or LEA2B↓
Hold time, data after LE1B, LE2B, LEA1B, or LEA2B↓
ns
ns
ns
1.5
†
These values apply only to the SN74ABTH16260.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
SN54ABT16260
= 5 V,
FROM
(INPUT)
TO
(OUTPUT)
V
CC
A
PARAMETER
UNIT
T
= 25°C
TYP
3.1
MIN
MAX
MIN
1
MAX
5.3
5.4
5.4
5.3
5.1
5.4
4.6
5.3
5.6
5.9
5.9
5
t
t
t
t
1
1
5.9
6.3
6.6
5.9
5.4
6.3
5
PLH
PHL
PLH
PHL
A or B
LE
B or A
A or B
ns
ns
1
3.4
1.1
1.1
1.3
1.1
1.5
1.6
1
3.2
1.1
1.1
1.3
1.1
1.5
1.6
1
3.3
SEL (B1)
SEL (B2)
SEL (B1)
SEL (B2)
3.2
t
PLH
PHL
3.4
A
ns
3.1
t
3.6
6.2
6.4
6.5
7.5
5.4
t
t
t
t
3.3
PZH
PZL
PHZ
PLZ
A or B
A or B
ns
ns
OE
OE
1.6
2.2
1.3
3.8
1.6
2.2
1.3
4.1
3.2
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
SN74ABTH16260
= 5 V,
FROM
(INPUT)
TO
(OUTPUT)
V
CC
A
PARAMETER
UNIT
T
= 25°C
TYP
3.1
MIN
MAX
MIN
1
MAX
4.8
5
t
t
t
t
1
1
5.6
5.9
5.8
5.3
5.3
6
PLH
PHL
PLH
PHL
A or B
LE
B or A
A or B
ns
ns
1
3.4
1.1
1.1
1.3
1.1
1.5
1.6
1
3.2
4.9
4.9
4.6
4.9
4.4
5.1
4.7
5.1
5.4
4.4
1.1
1.1
1.3
1.1
1.5
1.6
1
3.3
SEL (B1)
SEL (B2)
SEL (B1)
SEL (B2)
3.2
t
PLH
PHL
3.4
A
ns
3.1
4.4
5.9
5.7
5.8
6.4
4.8
t
3.6
t
t
t
t
3.3
PZH
PZL
PHZ
PLZ
A or B
A or B
ns
ns
OE
OE
1.6
2.2
1.3
3.8
1.6
2.2
1.3
4.1
3.2
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16260, SN74ABTH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS204C – JUNE 1992 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
7 V
PLH PHL
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
Open
L
PHZ PZH
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
t
PHL
PLH
PHL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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