SN54ABT162827 [TI]
20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS; 20位缓冲器/驱动器，具有三态输出
| 型号： | SN54ABT162827 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
| 文件： | 总10页 (文件大小：188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCBS248B − JULY 1993 − REVISED DECEMBER 1994
SN54ABT162827 . . . WD PACKAGE
SN74ABT162827 . . . DGG OR DL PACKAGE
(TOP VIEW)
• Output Ports Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are
Required
• Members of the Texas Instruments
1OE1
1Y1
1Y2
GND
1Y3
1Y4
1OE2
1A1
1A2
GND
1A3
A14
1
2
3
4
5
6
7
8
9
56
55
54
53
52
51
50
49
48
Widebus Family
• State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
• Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
V
V
• Typical V
(Output Ground Bounce)
CC
CC
OLP
CC
1Y5
1Y6
1A5
1A6
< 1 V at V
= 5 V, T = 25°C
A
• Distributed V
and GND Pin Configuration
Minimizes High-Speed Switching Noise
CC
1Y7 10
GND
1Y8
47 1A7
GND
1A8
11
12
46
45
• Flow-Through Architecture Optimizes
PCB Layout
1Y9 13
1Y10 14
2Y1 15
2Y2 16
2Y3 17
GND 18
2Y4 19
2Y5 20
2Y6 21
44 1A9
43 1A10
42 2A1
41 2A2
40 2A3
39 GND
38 2A4
37 2A5
36 2A6
• Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ′ABT162827 are noninverting 20-bit buffers
composed of two 10-bit buffers with separate
output-enable signals. For either 10-bit buffer, the
two output-enable (1OE1 and 1OE2 or 2OE1 and
2OE2) inputs must both be low for the
corresponding Y outputs to be active. If either
output-enable input is high, the outputs of that
10-bit buffer are in the high-impedance state.
V
22
35
V
CC
CC
2Y7 23
34 2A7
33 2A8
32 GND
31 2A9
30 2A10
29 2OE2
2Y8 24
GND 25
2Y9 26
2Y10 27
2OE1 28
The outputs, which are designed to source or sink
up to 12 mA, include 25-Ω series resistors to
reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE inputs should be tied to V
a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through
CC
The SN74ABT162827 is available in TI’s shrink small-outline package (DL), which provides twice the I/O pin
count and functionality of standard small-outline packages in the same printed-circuit-board area.
The SN54ABT162827 is characterized for operation over the full military temperature range of −55°C to 125°C.
The SN74ABT162827 is characterized for operation from −40°C to 85°C.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright 1994, Texas Instruments Incorporated
ꢑ ꢁꢝ ꢓꢀꢀ ꢛ ꢆꢙ ꢓꢔꢘ ꢐꢀ ꢓ ꢁ ꢛꢆꢓ ꢖ ꢞꢟ ꢠꢡ ꢢꢣꢤ ꢥꢦ ꢧꢨꢞ ꢤꢣ ꢨꢞꢩ ꢠꢨꢡ ꢜꢔ ꢛ ꢖ ꢑ ꢪꢆ ꢐꢛ ꢁ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢈꢉ ꢊ ꢉꢋ ꢌ ꢍ ꢀ ꢁꢋ ꢃ ꢄꢅꢆ ꢇ ꢈ ꢉ ꢊ ꢉ ꢋ
ꢉ ꢎꢏ ꢅꢐ ꢆ ꢍ ꢅ ꢑꢒ ꢒꢓ ꢔꢀ ꢕ ꢖꢔꢐ ꢗꢓ ꢔꢀ
ꢘꢐ ꢆ ꢙ ꢍꢚ ꢏꢀ ꢆꢄꢆꢓ ꢍ ꢛ ꢑꢆ ꢜꢑꢆ ꢀ
SCBS248B − JULY 1993 − REVISED DECEMBER 1994
FUNCTION TABLE
(each 10-bit buffer)
INPUTS
OUTPUT
Y
OE1
L
OE2
L
A
L
L
H
Z
Z
L
L
H
X
X
H
X
X
H
†
logic symbol
logic diagram (positive logic)
1
1OE1
56
1
&
&
1OE1
1OE2
1OE2
EN1
EN2
56
28
29
2OE1
2OE2
55
2
1Y1
1A1
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
2
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
1A10
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2A9
2A10
1Y1
3
1
1
To Nine Other Channels
1Y2
5
1Y3
6
28
29
2OE1
2OE2
1Y4
8
1Y5
9
1Y6
10
42
15
1Y7
12
2A1
2Y1
1Y8
13
1Y9
14
To Nine Other Channels
1Y10
15
2Y1
16
1
2
2Y2
17
2Y3
19
2Y4
20
2Y5
21
2Y6
23
2Y7
24
2Y8
26
2Y9
27
2Y10
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SCBS248B − JULY 1993 − REVISED DECEMBER 1994
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high state or power-off state, V
. . . . . . . . . . . . . −0.5 V to 5.5 V
O
Current into any output in the low state, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Maximum power dissipation at T = 55°C (in still air) (see Note 2): DGG package . . . . . . . . . . . . . . . . . . 1 W
A
DL package . . . . . . . . . . . . . . . . . . 1.4 W
Operating free-air temperature range, T : SN54ABT162827 . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
A
SN74ABT162827 . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.
recommended operating conditions (see Note 3)
SN54ABT162827 SN74ABT162827
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
CC
0
V
CC
V
I
I
High-level output current
Low-level output current
−12
12
9
−12
12
9
mA
mA
OH
OL
I
Control inputs
Data inputs
∆t/∆V
∆t/∆V
Input transition rise or fall rate
ns/V
10
10
Power-up ramp rate
200
−55
200
−40
µs/V
°C
CC
T
Operating free-air temperature
125
85
A
NOTE 3: Unused or floating inputs must be held high or low.
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3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢈꢉ ꢊ ꢉꢋ ꢌ ꢍ ꢀ ꢁꢋ ꢃ ꢄꢅꢆ ꢇ ꢈ ꢉ ꢊ ꢉ ꢋ
ꢉ ꢎꢏ ꢅꢐ ꢆ ꢍ ꢅ ꢑꢒ ꢒꢓ ꢔꢀ ꢕ ꢖꢔꢐ ꢗꢓ ꢔꢀ
ꢘꢐ ꢆ ꢙ ꢍꢚ ꢏꢀ ꢆꢄꢆꢓ ꢍ ꢛ ꢑꢆ ꢜꢑꢆ ꢀ
SCBS248B − JULY 1993 − REVISED DECEMBER 1994
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT162827 SN74ABT162827
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
I = −18 mA
−1.2
−1.2
−1.2
V
IK
CC
CC
CC
I
I
I
I
I
I
I
= − 1 mA
= − 1 mA
= − 3 mA
= − 12 mA
= 8 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
2.4
2
2.4
2
2.4
2
V
CC
= 4.5 V
0.4
0.8
0.8
0.65
0.8
V
OL
V
V
= 4.5 V
V
CC
= 12 mA
= 0 to 5.5 V,
CC
I
I
I
I
I
1
50
1
50
1
50
µA
µA
µA
µA
µA
I
V = V
I
or GND
CC
V
V
= 0 to 2.1 V,
= 0.5 V to 2.7 V, OE = X
CC
O
OZPU
OZPD
V
V
= 2.1 V to 0,
= 0.5 V to 2.7 V, OE = X
CC
O
50
50
50
V
V
= 2.1 V to 5.5 V,
= 2.7 V,
CC
O
‡
10
10
10
OZH
OE ≥ 2 V
OE ≥ 2 V
V
V
= 2.1 V to 5.5 V,
= 0.5 V,
CC
O
‡
−10
−10
−10
OZL
I
I
V
CC
V
CC
V
CC
= 0,
V or V ≤ 4.5 V
100
50
100
50
µA
µA
off
I
O
Outputs high
= 5.5 V,
= 5.5 V,
V
= 5.5 V
50
CEX
O
O
§
V
= 2.5 V
−25
−75 −100
−25 −100
−25 −100
mA
I
O
Outputs high
Outputs low
2
2
2
32
32
32
V
= 5.5 V,
I
= 0,
CC
O
I
mA
mA
CC
V = V
I
or GND
CC
Outputs
disabled
2
1
2
2
V
CC
= 5.5 V,
Outputs enabled
1.5
1
One input at
3.4 V,
Data inputs
Other inputs at
¶
∆I
CC
Outputs disabled
One input at 3.4 V,
0.05
1.5
1
0.05
1.5
V
CC
or GND
V
CC
= 5.5 V,
Control inputs
1.5
Other inputs at V
CC
or GND
C
C
V = 2.5 V or 0.5 V
3.5
8
pF
pF
i
I
V
O
= 2.5 V or 0.5 V
o
†
‡
§
¶
All typical values are at V
= 5 V.
CC
The parameters I
and I include the input leakage current.
OZH
OZL
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
CC
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ꢵ
ꢧ
ꢡ
ꢞ
ꢟ
ꢧ
ꢬ
ꢠ
ꢴ
ꢟ
ꢞ
ꢞ
ꢣ
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢊ
ꢉ
ꢋ
ꢌ
ꢍ
ꢀ
ꢁ
ꢋ
ꢃ
ꢉ ꢎ ꢏꢅꢐ ꢆꢍ ꢅꢑꢒ ꢒ ꢓꢔꢀ ꢕꢖ ꢔ ꢐꢗ ꢓꢔ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢊ
ꢉ
ꢋ
ꢀ
ꢀ
ꢘ ꢐꢆ ꢙꢍ ꢚ ꢏꢀꢆꢄꢆ ꢓꢍ ꢛ ꢑꢆ ꢜꢑ ꢆ
SCBS248B − JULY 1993 − REVISED DECEMBER 1994
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
V
T
= 5 V,
= 25°C
CC
A
SN54ABT162827 SN74ABT162827
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
†
MIN TYP
MAX
3.6
4.2
6.3
7.3
6.5
5.9
MIN
1
MAX
4.1
5
MIN
1
MAX
3.9
4.7
6.9
6.3
6.6
6.3
t
t
t
t
t
t
1
1.1
1.5
1.6
2.1
1.5
2.1
2.8
3.4
3.5
4.1
3.5
PLH
PHL
PZH
PZL
PHZ
PLZ
A
Y
Y
Y
ns
ns
ns
1.1
1.5
1.6
2.1
1.5
1.1
1.5
1.6
2.1
1.5
7.2
6.6
6.8
7.3
OE
OE
†
All typical values are at V
CC
= 5 V.
ꢜ
ꢔ
ꢛ
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ꢪ
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ꢜ
ꢔ
ꢓ
ꢗ
ꢐ
ꢓ
ꢘ
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ꢨ
ꢫ
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ꢠ
ꢣ
ꢨ
ꢤ
ꢣ
ꢨ
ꢤ
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ꢭ
ꢬ
ꢣ
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ꢞ
ꢡ
ꢢꢧ ꢡ ꢠ ꢴꢨ ꢭꢟ ꢩ ꢡ ꢧ ꢣꢫ ꢢꢧ ꢵ ꢧ ꢯꢣ ꢭꢦꢧ ꢨꢞꢰ ꢪ ꢟꢩ ꢬꢩ ꢤꢞ ꢧꢬ ꢠꢡ ꢞꢠ ꢤ ꢢꢩ ꢞꢩ ꢩꢨ ꢢ ꢣꢞ ꢟꢧꢬ
ꢠ
ꢨ
ꢞ
ꢟ
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ꢫ
ꢣ
ꢬ
ꢦ
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ꢠ
ꢵ
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ꢡ
ꢭ
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ꢤ ꢟꢩ ꢨ ꢴꢧ ꢣꢬ ꢢꢠ ꢡ ꢤ ꢣꢨ ꢞꢠ ꢨꢥꢧ ꢞ ꢟꢧ ꢡ ꢧ ꢭꢬ ꢣꢢ ꢥꢤꢞ ꢡ ꢲ ꢠꢞꢟ ꢣꢥꢞ ꢨꢣꢞ ꢠꢤꢧ ꢰ
ꢧ
ꢡ
ꢧꢬ
ꢵ
ꢧꢡ
ꢞꢟ
ꢧ
ꢬ
ꢠꢴ
ꢟ
ꢞ
ꢞꢣ
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢈꢉ ꢊ ꢉꢋ ꢌ ꢍ ꢀ ꢁꢋ ꢃ ꢄꢅꢆ ꢇ ꢈ ꢉ ꢊ ꢉ ꢋ
ꢉ ꢎꢏ ꢅꢐ ꢆ ꢍ ꢅ ꢑꢒ ꢒꢓ ꢔꢀ ꢕ ꢖꢔꢐ ꢗꢓ ꢔꢀ
ꢘꢐ ꢆ ꢙ ꢍꢚ ꢏꢀ ꢆꢄꢆꢓ ꢍ ꢛ ꢑꢆ ꢜꢑꢆ ꢀ
SCBS248B − JULY 1993 − REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
7 V
S1
500 Ω
Open
GND
From Output
Under Test
TEST
S1
t
t
/t
Open
7 V
PLH PHL
/t
C
= 50 pF
L
t
500 Ω
PLZ PZL
/t
(see Note A)
Open
PHZ PZH
LOAD CIRCUIT FOR OUTPUTS
3 V
0 V
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
S1 at 7 V
V
V
3.5 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
− 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
t
PZH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
OH
1.5 V
1.5 V
Output
[ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
DGG
DL
SN74ABT162827DGGR
SN74ABT162827DL
SN74ABT162827DLR
OBSOLETE TSSOP
56
56
56
TBD
TBD
TBD
Call TI
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OBSOLETE
OBSOLETE
SSOP
SSOP
DL
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
SN54ABT16373WD
ABT SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, CDFP48, 0.380 INCH, CERAMIC, FINE PITCH, DFP-48
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