SN54LV594AW [TI]
8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS; 8位的移位寄存器与输出寄存器
| 型号： | SN54LV594AW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS |
| 文件： | 总11页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LV594A, SN74LV594A
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS413B – APRIL 1998 – REVISED SEPTEMBER 1999
SN54LV594A . . . J OR W PACKAGE
SN74LV594A . . . D, DB, NS, OR PW PACKAGE
(TOP VIEW)
EPIC (Enhanced-Performance
Implanted CMOS) Process
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
Q
Q
V
CC
A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B
Q
Typical V
(Output V
Undershoot)
C
D
A
OHV
OH
>2 V at V
= 3.3 V, T = 25°C
Q
SER
CC
A
Q
RCLR
RCLK
SRCLK
SRCLR
8-Bit Serial-In, Parallel-Out Shift
Registers With Storage
E
Q
F
Q
G
Independent Direct Overriding Clears
on Shift and Storage Registers
Q
H
GND
Q
H′
Independent Clocks for Shift and
Storage Registers
SN54LV594A . . . FK PACKAGE
(TOP VIEW)
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
3
2
1
20 19
18
SER
RCLR
NC
Q
4
5
6
7
8
D
– 1000-V Charged-Device Model (C101)
Q
17
16
E
Package Options Include Plastic
Small-Outline (D, NS), Shrink
Small-Outline (DB), and Thin Shrink
Small-Outline (PW) Packages, Ceramic
Flat (W) Packages, Chip Carriers (FK),
and DIPs (J)
NC
15 RCLK
14
9 10 11 12 13
Q
F
SRCLK
Q
G
description
NC – No internal connection
The ’LV594A devices are 8-bit shift registers
designed for 2-V to 5.5-V V operation.
CC
These devices contain an 8-bit serial-in, parallel-
out shift register that feeds an 8-bit D-type storage
register. Separate clocks (RCLK, SRCLK) and
direct overriding clear (RCLR, SRCLR) inputs are provided on the shift and storage registers. A serial output
(Q ) is provided for cascading purposes.
H′
The shift-register (SRCLK) and storage-register (RCLK) clocks are positive-edge triggered. If the clocks are tied
together, the shift register always is one clock pulse ahead of the storage register.
The SN54LV594A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LV594A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV594A, SN74LV594A
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS413B – APRIL 1998 – REVISED SEPTEMBER 1999
FUNCTION TABLE
INPUTS
FUNCTION
Shift register is cleared.
SER
SRCLK SRCLR RCLK
RCLR
X
X
L
X
X
First stage of shift register goes low. Other stages
store the data of previous stage, respectively.
L
↑
H
X
X
First stage of shift register goes high. Other stages
store the data of previous stage, respectively.
H
↑
H
X
X
L
X
X
X
H
X
X
X
X
X
↑
X
L
Shift register state is not changed.
Storage register is cleared.
X
X
X
H
H
Shift register data is stored in the storage register.
Storage register state is not changed.
†
logic symbol
13
12
RCLR
RCLK
R3
C2
SRG8
10
11
SRCLR
SRCLK
R
C1/
15
14
Q
Q
3
2D
SER
1D
A
B
1
2
3
Q
Q
C
D
4
5
6
7
9
Q
Q
E
F
Q
Q
Q
G
H
2D
3
H′
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, NS, PW, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV594A, SN74LV594A
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS413B – APRIL 1998 – REVISED SEPTEMBER 1999
logic diagram (positive logic)
13
RCLR
12
RCLK
10
SRCLR
11
SRCLK
R
3D
C3
14
15
SER
Q
Q
Q
1D
C1
R
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
A
B
C
D
E
F
R
3D
1
2
2D
C2
R
C3
R
3D
2D
C2
C3
R
R
3
4
5
6
Q
Q
2D
C2
3D
C3
Q
Q
R
R
2D
C2
3D
C3
R
R
2D
C2
3D
C3
Q
Q
Q
Q
Q
Q
R
R
2D
C2
3D
C3
G
R
R
7
9
Q
Q
2D
C2
3D
C3
H
R
H′
Pin numbers shown are for the D, DB, J, NS, PW, and W packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV594A, SN74LV594A
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS413B – APRIL 1998 – REVISED SEPTEMBER 1999
timing diagram
SRCLK
SER
RCLK
SRCLR
RCLR
Q
Q
A
B
Q
Q
C
D
Q
E
Q
F
Q
G
Q
H
Q
H’
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV594A, SN74LV594A
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS413B – APRIL 1998 – REVISED SEPTEMBER 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through V
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LV594A
MIN MAX
SN74LV594A
UNIT
MIN
2
MAX
V
V
Supply voltage
2
5.5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
V
V
V
× 0.7
CC
CC
CC
CC
CC
CC
High-level input voltage
V
V
IH
× 0.7
× 0.7
× 0.7
× 0.7
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
× 0.3
× 0.3
5.5
V
V
V
× 0.3
CC
CC
CC
CC
CC
CC
V
IL
Low-level input voltage
× 0.3
× 0.3
5.5
V
V
Input voltage
0
0
V
V
I
Output voltage
0
V
0
V
CC
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
–50
–2
–50
–2
–6
–12
50
2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
Low-level output current
OH
OL
–6
mA
µA
–12
50
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
6
6
mA
12
12
200
100
20
85
0
0
0
200
100
20
0
0
0
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
–55
125
–40
°C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV594A, SN74LV594A
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS413B – APRIL 1998 – REVISED SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV594A
SN74LV594A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
TYP
MAX
MIN
TYP
MAX
I
I
I
I
I
I
I
I
= –50 µA
2 V to 5.5 V
2.3 V
3 V
V
–0.1
2
V
CC
–0.1
2
OH
OH
OH
OH
OL
OL
OL
OL
CC
= –2 mA
= –6 mA
= –12 mA
= 50 µA
= 2 mA
V
V
V
OH
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
3 V
0.1
0.4
0.44
0.55
±1
0.1
0.4
0.44
0.55
±1
V
OL
= 6 mA
= 12 mA
4.5 V
5.5 V
5.5 V
0 V
I
I
I
V = V
or GND
or GND,
µA
µA
µA
I
I
CC
CC
V = V
I = 0
O
20
20
CC
off
I
V or V = 0 to 5.5 V
5
5
I
O
3.3 V
5 V
3.5
2
3.5
2
C
V = V
I
or GND
pF
i
CC
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 2.5 V ± 0.2 V
CC
T
= 25°C
SN54LV594A SN74LV594A
A
UNIT
MIN
7
MAX
MIN
7.5
6.5
3
MAX
MIN
7.5
6.5
3
MAX
RCLK or SRCLK high or low
RCLR or SRCLR low
t
w
Pulse duration
ns
6
SER before SRCLK↑
2.5
8
†
SRCLK↑ before RCLK↑
9
9
t
t
SRCLR low before RCLK↑
8.5
6
9.5
6.8
7.6
1.5
9.5
6.8
7.6
1.5
ns
ns
Setup time
Hold time
su
SRCLR high (inactive) before SRCLK↑
RCLR high (inactive) before RCLK↑
SER after SRCLK↑
6.7
1.5
h
†
This setup time ensures the output register sees stable data from the shift-register outputs. The clocks can be tied together, in which case the
shift register is one clock pulse ahead of the storage register.
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V ± 0.3 V
CC
T
= 25°C
SN54LV594A SN74LV594A
A
UNIT
MIN
5.5
5
MAX
MIN
5.5
5
MAX
MIN
5.5
5
MAX
RCLK or SRCLK high or low
RCLR or SRCLR low
t
w
Pulse duration
ns
SER before SRCLK↑
3.5
8
3.5
8.5
9
3.5
8.5
9
†
SRCLK↑ before RCLK↑
t
t
SRCLR low before RCLK↑
8
ns
ns
Setup time
Hold time
su
SRCLR high (inactive) before SRCLK↑
RCLR high (inactive) before RCLK↑
SER after SRCLK↑
4.2
4.6
1.5
4.8
5.3
1.5
4.8
5.3
1.5
h
†
This setup time ensures the output register sees stable data from the shift-register outputs. The clocks can be tied together, in which case the
shift register is one clock pulse ahead of the storage register.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV594A, SN74LV594A
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS413B – APRIL 1998 – REVISED SEPTEMBER 1999
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V ± 0.5 V
CC
T
= 25°C
SN54LV594A SN74LV594A
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
RCLK or SRCLK high or low
RCLR or SRCLR low
t
w
Pulse duration
ns
5.2
3
5.2
3
5.2
3
SER before SRCLK↑
†
SRCLK↑ before RCLK↑
5
5
5
t
t
SRCLR low before RCLK↑
5
5
5
ns
ns
Setup time
Hold time
su
SRCLR high (inactive) before SRCLK↑
RCLR high (inactive) before RCLK↑
SER after SRCLK↑
2.9
3.2
2
3.3
3.7
2
3.3
3.7
2
h
†
This setup time ensures the output register sees stable data from the shift-register outputs. The clocks can be tied together, in which case the
shift register is one clock pulse ahead of the storage register.
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
80
SN54LV594A SN74LV594A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
65
MAX
MIN
45
40
1
MAX
MIN
45
40
1
MAX
C
= 15 pF*
= 50 pF
L
f
MHz
max
C
60
70
L
t
t
t
t
t
t
t
t
t
t
t
t
*
*
*
*
*
*
6.4
10.6
10.4
12.1
11.6
12.7
11.9
14.1
15.5
15.7
16.1
17.4
16.5
11.1
11.1
12.8
12.8
13.6
13.1
14.6
17.2
16.5
18.6
19
11.1
11.1
12.8
12.8
13.6
13.1
14.6
17.2
16.5
18.6
19
PLH
PHL
PLH
PHL
PHL
PHL
PLH
PHL
PLH
PHL
PHL
PHL
RCLK
Q –Q
A
H
6.3
1
1
7.4
1
1
C
= 15 pF
ns
SRCLK
Q
L
H′
7.2
1
1
7.9
1
1
RCLR
Q –Q
A
H
7.4
1
1
SRCLR
Q
H′
9.5
1
1
RCLK
Q –Q
A
H
10.8
10.6
11.3
12.1
11.6
1
1
1
1
C
= 50 pF
ns
SRCLK
Q
L
H′
1
1
1
1
RCLR
Q –Q
A
H
1
18.6
1
18.6
SRCLR
Q
H′
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV594A, SN74LV594A
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS413B – APRIL 1998 – REVISED SEPTEMBER 1999
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
120
105
4.6
4.9
5.4
5.5
6
SN54LV594A SN74LV594A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
80
MAX
MIN
70
50
1
MAX
MIN
70
50
1
MAX
C
= 15 pF*
= 50 pF
L
f
MHz
max
C
55
L
t
t
t
t
t
t
t
t
t
t
t
t
*
*
*
*
*
*
8
8.2
8.5
8.8
8.5
8.8
PLH
PHL
PLH
PHL
PHL
PHL
PLH
PHL
PLH
PHL
PHL
PHL
RCLK
Q –Q
A
H
1
1
9.1
1
9.7
1
9.7
C
= 15 pF
ns
SRCLK
Q
L
H′
9.2
1
9.9
1
9.9
9.8
1
10.6
10
1
10.6
10
RCLR
Q –Q
A
H
5.6
6.9
8.1
7.7
8.4
9.1
8.5
9.2
1
1
SRCLR
Q
H′
10.5
11.9
11.7
12.5
13.1
12.4
1
11.1
13.1
12.4
13.9
14.4
14
1
11.1
13.1
12.4
13.9
14.4
14
RCLK
Q –Q
A
H
1
1
1
1
C
= 50 pF
ns
SRCLK
Q
L
H′
1
1
1
1
RCLR
Q –Q
A
H
1
1
SRCLR
Q
H′
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
170
140
3.3
3.7
3.7
4.1
4.5
4.1
4.9
5.8
5.5
6
SN54LV594A SN74LV594A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
135
120
MAX
MIN
115
95
1
MAX
MIN
115
95
1
MAX
C
= 15 pF*
= 50 pF
L
f
MHz
max
C
L
t
t
t
t
t
t
t
t
t
t
t
t
*
*
*
*
*
*
6.2
6.5
6.8
7.2
7.6
7.1
7.8
8.9
8.6
9.2
10
6.5
6.9
6.5
6.9
PLH
PHL
PLH
PHL
PHL
PHL
PLH
PHL
PLH
PHL
PHL
PHL
RCLK
Q –Q
A
H
1
1
1
7.2
1
7.2
C
= 15 pF
ns
SRCLK
Q
L
H′
1
7.6
1
7.6
1
8.2
1
8.2
RCLR
Q –Q
A
H
1
7.6
1
7.6
SRCLR
Q
H′
1
8.3
1
8.3
RCLK
Q –Q
A
H
1
9.7
1
9.7
1
9.1
1
9.1
C
= 50 pF
ns
SRCLK
Q
L
H′
1
10.1
10.7
10.1
1
10.1
10.7
10.1
6.6
6
1
1
RCLR
Q –Q
A
H
9.2
1
1
SRCLR
Q
H′
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV594A, SN74LV594A
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS413B – APRIL 1998 – REVISED SEPTEMBER 1999
noise characteristics, V
= 3.3 V, C = 50 pF, T = 25°C (see Note 5)
CC
L
A
SN74LV594A
UNIT
PARAMETER
MIN
TYP
MAX
V
V
V
V
V
Quiet output, maximum dynamic V
0.5
0.8
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
–0.1
2.8
–0.8
OL
OH
2.31
0.99
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
f = 10 MHz
V
TYP
93
UNIT
CC
3.3 V
5 V
C
Power dissipation capacitance
pF
pd
112
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV594A, SN74LV594A
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS413B – APRIL 1998 – REVISED SEPTEMBER 1999
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
GND
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
V
CC
Open Drain
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
Timing Input
CC
0 V
t
w
t
h
t
V
su
CC
V
CC
50% V
50% V
CC
Input
Input
CC
50% V
50% V
CC
Data Input
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
50% V
50% V
50% V
t
CC
CC
t
CC
CC
0 V
0 V
t
t
t
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
≈ V
OH
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
V
OL
+ 0.3 V
S1 at V
(see Note B)
CC
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
– 0.3 V
50% V
50% V
50% V
CC
CC
CC
≈ 0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PHL
PHZ
PZH
PLH
.
Figure 1. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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