SN54LVTH2952FK [TI]
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS; 3.3 -V ABT八路总线收发器和寄存器具有三态输出
| 型号： | SN54LVTH2952FK |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS |
| 文件： | 总8页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LVTH2952, SN74LVTH2952
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS710D – OCTOBER 1997 – REVISED APRIL 1999
SN54LVTH2952 . . . JT PACKAGE
SN74LVTH2952 . . . DB, DGV, DW, OR PW PACKAGE
(TOP VIEW)
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
B8
B7
V
CC
A8
1
24
23
I
and Power-Up 3-State Support Hot
2
off
Insertion
B6
B5
B4
3
22 A7
21 A6
20 A5
4
Bus-Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
5
6
19
18
17
16
15
14
13
B3
B2
B1
A4
A3
A2
A1
OEBA
CLKBA
CLKENBA
7
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
8
9
OEAB
CLKAB
CLKENAB
GND
3.3-V V
)
CC
10
11
12
Support Unregulated Battery Operation
Down to 2.7 V
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
= 3.3 V, T = 25°C
CC
A
SN54LVTH2952 . . . FK PACKAGE
(TOP VIEW)
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
4
3
2
1
28 27 26
25
5
6
7
8
9
B5
B4
B3
NC
B2
A6
A5
A4
NC
A3
A2
A1
24
23
22
21
20
19
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Thin Very Small-Outline (DGV) Packages,
Ceramic Chip Carriers (FK), and Ceramic
(JT) DIPs
10
11
B1
OEAB
12 13 14 15 16 17 18
description
These octal bus transceivers and registers are
designed specifically for low-voltage (3.3-V) V
CC
operation, but with the capability to provide a TTL
interface to a 5-V system environment.
NC – No internal connection
The ’LVTH2952 devices consist of two 8-bit back-to-back registers that store data flowing in both directions
between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition
of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB or CLKENBA) input is low.
Taking the output-enable (OEAB or OEBA) input low accesses the data on either port.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
through a pullup resistor;
CC
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH2952, SN74LVTH2952
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS710D – OCTOBER 1997 – REVISED APRIL 1999
description (continued)
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54LVTH2952 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH2952 is characterized for operation from –40°C to 85°C.
†
FUNCTION TABLE
INPUTS
OUTPUT
B
CLKENAB CLKAB OEAB
A
‡
‡
H
X
L
X
L
L
L
L
H
X
X
L
B
B
0
0
H or L
↑
↑
L
H
Z
L
H
X
X
X
†
‡
A-to-B data flow is shown; B-to-A data flow is similar
but uses CLKENBA, CLKBA, and OEBA.
Level of B before the indicated steady-state input
conditions were established
§
logic symbol
15
OEBA
CLKENBA
CLKBA
EN3
13
G1
14
1 C5
9
OEAB
CLKENAB
CLKAB
EN4
11
G2
10
2 C6
8
16
5D
4
B1
A1
3
1
1
6D
17
18
19
20
21
22
23
7
6
5
4
3
2
1
A2
A3
A4
A5
A6
A7
A8
B2
B3
B4
B5
B6
B7
B8
§
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DGV, DW, JT, and PW packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH2952, SN74LVTH2952
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS710D – OCTOBER 1997 – REVISED APRIL 1999
logic diagram (positive logic)
11
CLKENAB
10
CLKAB
9
OEAB
13
CLKENBA
14
CLKBA
15
OEBA
C1
1D
16
8
B1
A1
C1
1D
To Seven Other Channels
Pin numbers shown are for the DB, DGV, DW, JT, and PW packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH2952, SN74LVTH2952
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS710D – OCTOBER 1997 – REVISED APRIL 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I : SN54LVTH2952 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74LVTH2952 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, I (see Note 2): SN54LVTH2952 . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
SN74LVTH2952 . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVTH2952 SN74LVTH2952
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
5.5
–24
48
0.8
5.5
–32
64
V
IL
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
–55
200
–40
CC
T
A
Operating free-air temperature
125
85
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH2952, SN74LVTH2952
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS710D – OCTOBER 1997 – REVISED APRIL 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTH2952
SN74LVTH2952
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
= 2.7 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
CC
CC
I
= 2.7 V to 3.6 V,
= 2.7 V,
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –8 mA
= –24 mA
= –32 mA
= 100 µA
= 24 mA
= 16 mA
= 32 mA
= 48 mA
= 64 mA
V
–0.2
V
–0.2
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
CC
2.4
CC
2.4
V
V
OH
2
V
= 3 V
CC
CC
2
0.2
0.5
0.2
0.5
0.4
0.5
V
= 2.7 V
0.4
V
OL
0.5
V
CC
= 3 V
0.55
0.55
±1
V
V
= 3.6 V,
V = V
I
or GND
±1
10
20
1
CC
CC
Control inputs
= 0 or 3.6 V,
V = 5.5 V
I
10
CC
I
I
V = 5.5 V
I
20
µA
‡
A or B ports
A or B ports
V
CC
= 3.6 V
V = V
I CC
1
V = 0
I
–5
–5
I
I
V
V
= 0,
V or V = 0 to 4.5 V
±100
µA
µA
off
CC
I
O
V = 0.8 V
I
75
75
= 3 V
CC
V = 2 V
I
–75
–75
I(hold)
§
V
V
= 3.6 V ,
V = 0 to 3.6 V
±500
±100
CC
I
= 0 to 1.5 V, V = 0.5 V to 3 V,
OE = don’t care
CC
O
±100
±100
µA
µA
I
I
OZPU
V
= 1.5 V to 0, V = 0.5 V to 3 V,
CC
OE = don’t care
O
±100
OZPD
Outputs high
Outputs low
0.19
5
0.19
5
V
I
= 3.6 V,
CC
= 0,
I
mA
mA
CC
O
V = V
I
or GND
CC
Outputs disabled
0.19
0.19
V
= 3 V to 3.6 V, One input at V – 0.6 V,
CC
CC
Other inputs at V
¶
∆I
0.2
0.2
CC
or GND
CC
C
C
V = 3 V or 0
4
9
4
9
pF
pF
i
I
V
O
= 3 V or 0
io
On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
‡
§
¶
All typical values are at V
= 3.3 V, T = 25°C.
CC
or GND
A
Unused terminals at V
CC
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH2952, SN74LVTH2952
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS710D – OCTOBER 1997 – REVISED APRIL 1999
timing requirement over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVTH2952
= 3.3 V
SN74LVTH2952
= 3.3 V
V
CC
V
CC
V
= 2.7 V
V
= 2.7 V
UNIT
CC
CC
± 0.3 V
± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
f
t
Clock frequency
Pulse duration
150
150
150
150
MHz
ns
clock
CLK high
CLK low
Data high
Data low
Data high
Data low
3.3
3.3
1.6
1.6
1.6
2
3.3
3.3
2.2
2.2
1.9
2.6
0.2
0.2
3.3
3.3
1.5
1.5
1.5
1.9
1
3.3
3.3
2.1
2.1
1.8
2.5
0.2
0.2
w
A or B before CLK↑
CE before CLK↑
t
t
ns
ns
Setup time
Hold time
su
1
A or B after CLK↑
CE after CLK↑
h
1.2
1.2
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN54LVTH2952
= 3.3 V
SN74LVTH2952
FROM
(INPUT)
TO
(OUTPUT)
V
V
= 3.3 V
V
CC
CC
V
CC
= 2.7 V
= 2.7 V
MAX
PARAMETER
UNIT
CC
± 0.3 V
± 0.3 V
†
MIN
150
1.2
1.2
1
MAX
MIN
MAX
MIN TYP
MAX
MIN
f
t
t
t
t
t
t
150
150
150
MHz
ns
max
PLH
PHL
PZH
PZL
PHZ
PLZ
4.8
4.8
4.8
4.8
5.6
5.4
5.5
5.5
5.9
5.9
6
1.3
1.3
1.1
1.1
1.3
1.6
2.9
3.1
2.6
3
4.6
4.6
4.6
4.6
5.4
5.1
5.3
5.3
5.8
5.8
5.9
5.3
CLKBA or
CLKAB
A or B
A or B
A or B
ns
ns
OEBA or OEAB
OEBA or OEAB
1
1.2
1.5
3.6
3.6
5.6
†
All typical values are at T = 25°C.
A
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH2952, SN74LVTH2952
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS710D – OCTOBER 1997 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
6 V
S1
Open
500 Ω
TEST
/t
S1
From Output
Under Test
GND
t
Open
6 V
PLH PHL
t
/t
PLZ PZL
C
= 50 pF
L
500 Ω
t
/t
GND
(see Note A)
PHZ PZH
LOAD CIRCUIT FOR OUTPUTS
2.7 V
0 V
1.5 V
Timing Input
Data Input
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
Input
1.5 V
1.5 V
1.5 V
1.5 V
t
PLH
t
t
t
PLZ
PHL
PZL
Output
Waveform 1
S1 at 6 V
V
V
OH
3 V
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈ 0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 1999, Texas Instruments Incorporated
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