SN65ELT21DGK [TI]
5-V PECL-to-TTL Translator; 5 -V PECL至TTL转换器
| 型号： | SN65ELT21DGK |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 5-V PECL-to-TTL Translator |
| 文件： | 总11页 (文件大小：436K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65ELT21
www.ti.com ....................................................................................................................................................................................................... SLLS923–JUNE 2009
5-V PECL-to-TTL Translator
1
FEATURES
PIN ASSIGNMENT
•
3ns (TYP) Propagation Delay
•
Operating Range: VCC = 4.2 V to 5.7 V with
GND = 0 V
D or DGK PACKAGE
(TOP VIEW)
•
•
24-mA TTL Output
Deterministic Output Value for Open Input
Conditions or When Inputs < 1.3 V
NC
D
V
CC
1
2
8
7
•
•
Built-In Temperature Compensation
Q
Drop-In Compatible to the MC10ELT21,
MC100ELT21
D
6
5
NC
3
4
APPLICATIONS
•
Data and Clock Transmission Over Backplane
GND
V
•
Signaling Level Conversion for Clock or Data
BB
DESCRIPTION
Table 1. Pin Descriptions
The SN65ELT21 is
a
differential PECL-to-TTL
translator. It operates on +5-V supply and ground
only. The device includes circuitry to maintain Q to a
low logic level when inputs are in an open condition
or < 1.3 V.
PIN
FUNCTION
PECL data inputs
TTL output
D, D
Q
VCC
VEE
VBB
Positive supply
The VBB pin is a reference voltage output for the
device. When the device is used in single-ended
mode, the unused input should be tied to VBB. This
reference voltage can also be used to bias the input
when it is ac coupled. When it is used, place a
Negative supply
Reference voltage output
0.01µF decoupling capacitor between VCC and VBB
Also limit the sink/source current to < 0.5 mA to VBB
Leave VBB open when it is not used.
.
.
The SN65ELT21 is housed in an industry standard
SOIC-8 package and is also available in an optional
TSSOP-8 package.
ORDERING INFORMATION(1)(2)
PART NUMBER
SN65ELT21D
PART MARKING
ELT21
SIII
PACKAGE
SOIC
SOIC-TSSOP
LEAD FINISH
NiPdAu
SN65ELT21DGK
NiPdAu
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Leaded device options are not initially available; contact a sales representative for further details.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65ELT21
SLLS923–JUNE 2009....................................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)
PARAMETER
Absolute PECL mode supply voltage
Sink/source current, VBB
CONDITIONS
VCC (GND = 0 V)
VALUE
6
UNIT
V
±0.5
mA
V
PECL input voltage
GND = 0 V, VI ≤ VCC
6
Operating temperature range
Storage temperature range
–40 to 85
–65 to 150
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
POWER RATING THERMAL RESISTANCE,
DERATING FACTOR
TA > 25°C
POWER RATING
TA = 85°C
(mW)
CIRCUIT BOARD
MODEL
JUNCTION-TO-AMBIENT
PACKAGE
TA < 25°C
(mW)
NO AIRFLOW
(mW/°C)
SOIC
Low-K
High-K
Low-K
High-K
719
840
469
527
139
119
213
189
7
8
5
5
288
336
188
211
SOIC-TSSOP
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX UNIT
θJB
Junction-to-board thermal resistance
SOIC
79
120
98
°C/W
SOIC-TSSOP
SOIC
θJC
Junction-to-case thermal resistance
°C/W
SOIC-TSSOP
74
KEY ATTRIBUTES
CHARACTERISTICS
VALUE
Internal input pull-down resistor
Moisture sensitivity level
50 kΩ
Level 1
Flame ability rating (oxygen index: 28 to 34)
Electrostatic discharge
UL 94 V-0 at 0.125 in
2 kV
Human body model
Charged-device model
1.5 kV
Meets or exceeds JEDEC Spec EIA/JESD78 latchup test
2
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): SN65ELT21
SN65ELT21
www.ti.com ....................................................................................................................................................................................................... SLLS923–JUNE 2009
PECL DC CHARACTERISTICS
At VCC = 5.0 V, GND = 0.0 V (unless otherwise noted)(1)(2)
TA = –40°C
TA = 25°C
TA = 85°C
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP MAX MIN TYP MAX MIN
MAX
VIH
VIL
High-level input voltage,
single-ended
3835
4120 3835
3525 3190
4120 3835
3525 3190
4120 mV
3525 mV
Low-leveI input voltage,
single-ended
3190
VBB
Output reference voltage
3.62
2.2
3.69 3.74 3.62 3.69 3.74 3.62
3.69
3.74
5.0
V
V
(3)
VIHCMR High-level input voltage,
common-mode range,
differential
See
5.0
2.2
5.0
2.2
IIH
IIL
High-level input current
Low-level input current
150
150
150 µA
µA
0.5
0.5
0.5
(1) The device will meet the specifications after thermal balance has been established when mounted in a socket or printed circuit board
with maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are
applied individually under normal operating conditions and not valid simultaneously.
(2) Input parameters vary 1:1 with VCC. VCC can vary +0.7 V / –0.8 V.
(3) VIHCMR(min) varies 1:1 with GND, VIHCMR(max) varies 1:1 with VCC
.
TTL DC CHARACTERISTICS
At VCC = 4.2 V to 5.7 V, TA = –40°C to 85°C (unless otherwise noted)(1)
PARAMETER
Power supply current
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICCH
ICCL
VOH
VOL
IOS
20
mA
mA
V
Power supply current
20
(2)
High-level output voltage
Low-level output voltage
Output short circuit current
IOH = –3.0 mA
IOL = 24 mA
2.4
See
0.5
V
–150
–60
mA
(1) The device will meet the specifications after thermal balance has been established when mounted in a socket or printed circuit board
with maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are
applied individually under normal operating conditions and not valid simultaneously.
(2) VOH(max) level is VCC – 0.7.
AC CHARACTERISTICS
At VCC = 4.2 V to 5.7 V, GND = 0.0 V (unless otherwise noted)(1)(2)
TA = –40°C
MIN TYP MAX
TA = 25°C
MIN TYP MAX
TA = 85°C
MIN TYP MAX
TEST
CONDITIONS
PARAMETER
UNIT
fMAX
Maximum switching
frequency
At Vol < 0.5V
(See Figure 4)
200
200
200
MHz
tPLH/tPHL Propagation delay times
At 1.5 V
2
4.5
20
2
4.5
20
2
4.5
20
ns
ps
tJITTER
VPP
Random clock jitter (RMS)
Input swing
5
5
5
(3)
See
200
1000
200
1000
200
1000 mV
ps
tr/tf
Output rise/fall times
Q (10%–90%)
750
780
910
(1) The device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are
applied individually under normal operating conditions and not valid simultaneously.
(2) RL = 500 Ω to GND and CL = 20 pF to GND. See Figure 1.
(3) VPP(min) is minimum input swing for which ac parameters are assured.
Copyright © 2009, Texas Instruments Incorporated
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3
Product Folder Link(s): SN65ELT21
SN65ELT21
SLLS923–JUNE 2009....................................................................................................................................................................................................... www.ti.com
TTL Output
CL
RL
CL Includes Test
Fixture Capacitance
AC Test Load
GND
Figure 1. TTL Output AC Test Loading Condition
IN
IN
1.5 V
1.5 V
OUT
t
t
PHL
PLH
Figure 2. Output Propagation Delay
90%
10%
t
t
f
r
Figure 3. Output Rise and Fall Times
4
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): SN65ELT21
SN65ELT21
www.ti.com ....................................................................................................................................................................................................... SLLS923–JUNE 2009
OUTPUT VOLTAGE
vs
FREQUENCY
5
VOH 85
4
VOH 25
VOH -40
3
2
1
0
VOL 85
VOL 25
VOL -40
VCC = 5.0V
0
50 100 150 200 250 300 350 400 450 500
Frequency - MHz
Figure 4.
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): SN65ELT21
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jul-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN65ELT21D
ACTIVE
SOIC
D
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65ELT21DGK
SN65ELT21DGKR
SN65ELT21DR
PREVIEW
PREVIEW
ACTIVE
MSOP
MSOP
SOIC
DGK
DGK
D
8
8
8
80
TBD
TBD
Call TI
Call TI
Call TI
Call TI
2500
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Aug-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65ELT21DGKR
SN65ELT21DR
MSOP
SOIC
DGK
D
8
8
2500
2500
330.0
330.0
12.4
12.4
5.3
6.4
3.4
5.2
1.4
2.1
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Aug-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN65ELT21DGKR
SN65ELT21DR
MSOP
SOIC
DGK
D
8
8
2500
2500
346.0
346.0
346.0
346.0
29.0
29.0
Pack Materials-Page 2
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