SN65LBC173A-EP [TI]

四路 RS-485 差分线路接收器,SN65LBC173A-EP;
SN65LBC173A-EP
型号: SN65LBC173A-EP
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

四路 RS-485 差分线路接收器,SN65LBC173A-EP

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SN65LBC173A-EP  
ZHCSFQ1 NOVEMBER 2016  
SN65LBC173A-EP 四路 RS-485 差分线路接收器  
1 特性  
3 说明  
1
专为 TIA/EIA-485TIA/EIA-422 和  
SN65LBC173A 是一款具有三态输出的四路差分接收  
ISO 8482 应用 设计  
信号传输速率 (1)高达 50Mbps  
器,专为 TIA/EIA-485 (RS-485)TIA/EIA-422 (RS-  
422) ISO 8482(欧盟的 RS-485)应用 而设计。  
在总线短路、开路和空闲总线条件下提供故障保护  
当数据速率高达甚至超过 5000bps 时,该器件针对均  
衡后的多点总线通信进行了优化。传输介质可采用双绞  
线电缆、印刷电路板走线或背板。最终数据传输速率和  
距离取决于介质衰减特性和环境噪声耦合。  
为总线输入提供的静电放电 (ESD) 保护电压超过  
6kV  
共模总线电压输入范围:-7V 12V  
传播延迟时间 < 18ns  
低待机功耗:< 32µA  
接收器的正负共模输入电压范围较大, 其 ESD 保护  
电压高达 6kV,适用于严苛环境中的 高速多点数据传  
输 应用。这些器件通过 LinBiCMOS®进行设计,兼具  
低功耗特性和极强稳定性。  
针对 AM26LS32DS96F173LTC488 和  
SN75173 进行引脚兼容升级  
2 应用  
G G 输入为正/负逻辑提供使能控制逻辑,从而使能  
全部四个驱动器。禁用或关闭器件后,接收器输入针对  
总线呈现高阻抗状态,从而降低系统负载。  
支持国防、航天和医疗 应用  
受控基线  
同一组装和测试场所  
同一制造场所  
器件信息(1)  
延长的产品生命周期  
延长产品的变更通知周期  
产品可追溯性  
器件型号  
封装  
SOIC (16)  
封装尺寸(标称值)  
SN65LBC173A-EP  
9.90mm x 3.90mm  
(1) 要了解所有可用封装,请参见数据表末尾的可订购产品附录。  
(1) 线路的信号传输速率是指每秒钟的电压转换次数,单位为 bps  
(每秒比特数)。  
.
逻辑图  
G
G
1A  
1B  
1Y  
2A  
2B  
2Y  
3Y  
3A  
3B  
4A  
4B  
4Y  
Copyright © 2016, Texas Instruments Incorporated  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
English Data Sheet: SLLSEH1  
 
 
 
SN65LBC173A-EP  
ZHCSFQ1 NOVEMBER 2016  
www.ti.com.cn  
目录  
8.3 Feature Description................................................. 10  
8.4 Device Functional Modes........................................ 11  
Application and Implementation ........................ 12  
9.1 Application Information............................................ 12  
9.2 Typical Application .................................................. 12  
1
2
3
4
5
6
特性.......................................................................... 1  
应用.......................................................................... 1  
说明.......................................................................... 1  
修订历史记录 ........................................................... 2  
Pin Configuration and Functions......................... 3  
Specifications......................................................... 4  
6.1 Absolute Maximum Ratings ...................................... 4  
6.2 ESD Ratings.............................................................. 4  
6.3 Recommended Operating Conditions....................... 4  
6.4 Thermal Information.................................................. 4  
6.5 Electrical Characteristics........................................... 5  
6.6 Switching Characteristics.......................................... 5  
6.7 Typical Characteristics.............................................. 7  
Parameter Measurement Information .................. 8  
Detailed Description ............................................ 10  
8.1 Overview ................................................................. 10  
8.2 Functional Block Diagram ....................................... 10  
9
10 Power Supply Recommendations ..................... 14  
11 Layout................................................................... 14  
11.1 Layout Guidelines ................................................. 14  
11.2 Layout Example .................................................... 14  
12 器件和文档支持 ..................................................... 15  
12.1 接收文档更新通知 ................................................. 15  
12.2 社区资源................................................................ 15  
12.3 ....................................................................... 15  
12.4 静电放电警告......................................................... 15  
12.5 Glossary................................................................ 15  
13 机械、封装和可订购信息....................................... 16  
7
8
4 修订历史记录  
日期  
修订版本  
注释  
2016 11 月  
*
最初发布版本。  
2
Copyright © 2016, Texas Instruments Incorporated  
 
SN65LBC173A-EP  
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ZHCSFQ1 NOVEMBER 2016  
5 Pin Configuration and Functions  
D Package  
16-Pin SOIC  
Top View  
1B  
1A  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
CC  
4B  
4A  
4Y  
G
1Y  
G
2Y  
2A  
3Y  
3A  
3B  
2B  
GND  
Not to scale  
Pin Functions  
PIN  
I/O  
DESCRIPTION  
NAME  
1A  
NO.  
2
I
I
RS-485 differential input (noninverting).  
RS-485 differential input (inverting).  
Logic level output.  
1B  
1
1Y  
3
O
I
2A  
6
RS-485 differential input (noninverting).  
RS-485 differential input (inverting).  
Logic level output.  
2B  
7
I
2Y  
5
O
I
3A  
10  
9
RS-485 differential input (noninverting).  
RS-485 differential input (inverting).  
Logic level output.  
3B  
I
3Y  
11  
14  
15  
13  
12  
4
O
I
4A  
RS-485 differential input (noninverting).  
RS-485 differential input (inverting).  
Logic level output.  
4B  
I
4Y  
O
I
G
Active-low select.  
G
I
Active-high select.  
GND  
VCC  
8
Ground.  
16  
Power supply.  
Copyright © 2016, Texas Instruments Incorporated  
3
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ZHCSFQ1 NOVEMBER 2016  
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6 Specifications  
6.1 Absolute Maximum Ratings  
over operating free-air temperature range (unless otherwise noted)(1)  
MIN  
–0.3  
–10  
–30  
–0.5  
–10  
–65  
MAX  
UNIT  
V
(2)  
Supply voltage, VCC  
6
15  
Voltage at any bus input (DC)  
V
Voltage at any bus input (transient pulse through 100 , see 10)  
Input voltage at G and G, VI  
30  
V
VCC + 0.5  
10  
V
Receiver output current, IO  
mA  
°C  
Storage temperature, Tstg  
150  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating  
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltage values, except differential I/O bus voltages, are with respect to GND.  
6.2 ESD Ratings  
VALUE  
±6000  
±5000  
UNIT  
A and B to GND  
All pins  
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)  
V(ESD)  
Electrostatic discharge  
V
Charged-device model (CDM), per JEDEC specification  
JESD22-C101(2)  
All pins  
±2000  
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.  
6.3 Recommended Operating Conditions  
MIN NOM  
MAX UNIT  
VCC  
Supply voltage  
4.75  
–7  
2
5
5.25  
12  
V
V
Voltage at any bus terminal  
High-level input voltage  
Low-level input voltage  
Output current  
A, B  
G, G  
Y
VIH  
VIL  
VCC  
0.8  
8
V
0
V
–8  
–55  
mA  
°C  
TJ  
Junction temperature  
125  
6.4 Thermal Information  
SN65LBC173A-EP  
THERMAL METRIC(1)  
D (SOIC)  
16 PINS  
78  
UNITS  
θJA  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
θJCtop  
θJB  
39.5  
35.4  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
8.5  
ψJB  
35.1  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report.  
4
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6.5 Electrical Characteristics  
over recommended operating conditions  
PARAMETER  
TEST CONDITIONS  
MIN TYP(1)  
MAX UNIT  
VIT+ Positive-going differential input voltage threshold  
–80  
–10 mV  
–7 V VCM 12 V (VCM = (VA + VB ) / 2)  
VIT-  
VHYS Hysteresis voltage (VIT+ – VIT−  
VIK Input clamp voltage  
Negative-going differential input voltage threshold  
–200  
–120  
40  
mV  
mV  
V
)
II = –18 mA  
–1.5  
2.7  
–0.8  
VID = 200 mV,  
VOH High-level output voltage  
VOL Low-level output voltage  
4.8  
0.2  
V
IOH = –8 mA  
See 6  
VID = –200 mV,  
0.4  
V
IOL = 8 mA  
IOZ  
II  
High-impedance-state output current  
Line input current  
VO = 0 V to VCC  
–1  
1
µA  
VI = 12 V  
VI = –7 V  
0.9  
Other input at 0 V,  
VCC = 0 V or 5 V  
mA  
–0.7  
IIH  
IIL  
RI  
High-level input current  
110 µA  
µA  
Enable inputs G, G  
A, B inputs  
Low-level input current  
Input resistance  
–100  
12  
kΩ  
G at 0 V, G at  
VCC  
VID = 5 V  
No load  
32 µA  
16 mA  
ICC  
Supply current  
G at VCC, G at 0  
V
11  
(1) All typical values are at VCC = 5 V and 25°C.  
6.6 Switching Characteristics  
over recommended operating conditions  
PARAMETER  
TEST CONDITIONS  
MIN TYP MAX UNIT  
tr  
Differential output voltage rise time  
2
2
7
7
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tf  
Differential output voltage fall time  
VID = –3 V to 3 V,  
See 7  
tPLH  
tPHL  
tPZH  
tPHZ  
tPZL  
tPLZ  
tsk(p)  
tsk(o)  
Propagation delay time, low-to-high level output  
Propagation delay time, high-to-low level output  
Propagation delay time, high-impedance-to-high-level output  
Propagation delay time, high-level-output-to-high impedance  
Propagation delay time, high-impedance-to-low-level output  
Propagation delay time, low-level-output-to-high impedance  
Pulse skew (|tPLH – tPHL|)  
8
8
12  
12  
27  
7
18  
18  
39  
24  
39  
18  
2
See 8  
See 9  
29  
12  
0.2  
Output skew(1)  
3
tsk(pp) Part-to-part skew(2)  
3
(1) Output skew (tsk(o)) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected  
together.  
(2) Part-to-part skew (tsk(pp)) is the magnitude of the difference in propagation delay times between any specified terminals of two devices  
when both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical  
packages and test circuits.  
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100  
10  
1
0.1  
85  
105  
125  
145  
165  
Operating Junction Temperature (èC)  
D001  
(1) See data sheet for absolute maximum and minimum recommended operating conditions.  
(2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect  
life).  
(3) Enhanced plastic product disclaimer applies.  
1. SN65LBC173A-EP Wirebond Life Derating Chart  
6
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6.7 Typical Characteristics  
6
5
4
3
2
1
800  
600  
V
= 0 V  
CC  
V
V
= −7 V  
IC  
= 0 V  
IC  
IC  
400  
200  
0
V
= 12 V  
V
CC  
= 5 V  
V
IC  
= −7 V  
= 0 V  
V
IC  
V
IC  
= 12 V  
−200  
−400  
−600  
0
−150  
−100  
−50  
0
50  
−10  
−5  
0
5
10  
15  
Differential Input Voltage − mV  
Bus Input Voltage − V  
VCC = 5 V  
TA = 25°C  
3. Output Voltage vs Differential Input Voltage  
2. Bus Input Current vs Bus Input Voltage  
60  
50  
14  
13.5  
13  
40  
30  
V
= 5.25 V, C = 15 pF  
L
CC  
12.5  
12  
V
= 5 V, C = 15 pF  
L
CC  
V = 4.75 V, C = 15 pF  
CC L  
20  
10  
11.5  
TPHL  
TPLH  
11  
-55  
V
CC  
= 5 V, No Load  
-35  
-15  
5
25  
45  
65  
85  
105 125  
Operating Junction Temperature (èC)  
D005  
0
1
10  
Signaling Rate (All Four Channels) − Mbps  
100  
5. Propagation Delay Time vs Free-Air Temperature  
4. Supply Current vs Signaling Rate (All Four Channels)  
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7 Parameter Measurement Information  
V
A
I
O
V
ID  
V
B
V
O
6. Voltage and Current Definitions  
Input B  
3 V  
0 V  
A
B
Generator  
Generator  
50  
1.5 V  
1.5 V  
Y
Input A  
t
t
PHL  
PLH  
C
= 15 pF  
V
L
(Includes Probe and  
OH  
OL  
90%  
10%  
90%  
10%  
Output Y  
1.5 V  
Jig Capacitance)  
50 Ω  
V
t
t
f
r
Generators: PRR = 1 MHz, 50% Duty Cycle,  
t <6 ns, Z = 50 Ω  
r o  
7. Switching Test Circuit and Waveforms  
V
CC  
A
B
1.5 V  
1 k  
Y
3 V  
0 V  
C
= 15 pF  
L
(Includes Probe and  
G
1.5 V  
1.5 V  
Jig Capacitance)  
t
t
PHZ  
PZH  
Y
V
OH  
−0.5 V  
G
G
V
OH  
1.5 V  
V
CC  
GND  
Generator  
50 Ω  
Generators: PRR = 1 MHz, 50% Duty Cycle,  
t <6 ns, Z = 50 Ω  
r o  
8. Test Circuit Waveforms, tPZH and tPHZ  
8
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Parameter Measurement Information (接下页)  
V
CC  
A
B
1 k  
−1.5 V  
Y
3 V  
C
= 15 pF  
L
(Includes Probe and  
G
1.5 V  
1.5 V  
Jig Capacitance)  
0 V  
PLZ  
t
t
PZL  
Y
V
CC  
G
G
1.5 V  
V
+ 0.5 V  
V
OL  
V
CC  
Generator  
50 Ω  
OL  
Generators: PRR = 1 MHz, 50% Duty Cycle,  
t <6 ns, Z = 50 Ω  
r o  
9. Test Circuit Waveforms, tPZL and tPLZ  
V
TEST  
100  
0 V  
Pulse Generator,  
15 µs Duration,  
1% Duty Cycle  
15 µs  
1.5 ms  
V
TEST  
10. Test Circuit and Waveform, Transient Over-Voltage Test  
A Input  
B Input  
V
CC  
V
CC  
100 k  
4 kΩ  
4 kΩ  
16 V  
16 V  
16 V  
16 V  
18 kΩ  
18 kΩ  
Input  
Input  
100 kΩ  
4 kΩ  
4 kΩ  
G Input  
G Input  
V
CC  
V
CC  
Y Output  
V
CC  
100 kΩ  
1 kΩ  
1 kΩ  
5 Ω  
Input  
Input  
8 V  
Output  
8 V  
100 kΩ  
8 V  
8 V  
8 V  
11. Equivalent Input and Output Schematic Diagrams  
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8 Detailed Description  
8.1 Overview  
The SN65LBC173A is a quadruple differential line receiver with tri-state outputs, designed for TIA/EIA-485 (RS-  
485), TIA/EIA-422 (RS-422), and ISO 8482 (Euro RS-485) applications. This device is optimized for balanced  
multipoint bus communication at data rates up to and exceeding 50 million bits per second. The transmission  
media may be twisted-pair cables, printed-circuit board traces, or backplanes. The ultimate rate and distance of  
data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the  
environment.  
The receiver operates over a wide range of positive and negative common-mode input voltages, and features  
ESD protection to 6 kV, making it suitable for high-speed multipoint data transmission applications in harsh  
environments. These devices are designed using LinBiCMOS®, facilitating low-power consumption and  
robustness.  
The G and G inputs provide enable control logic for either positive- or negative-logic enabling all four drivers.  
When disabled or powered off, the receiver inputs present a high-impedance to the bus for reduced system  
loading.  
8.2 Functional Block Diagram  
G
G
1A  
1Y  
1B  
2A  
2Y  
2B  
3A  
3Y  
3B  
4A  
4Y  
4B  
Copyright © 2016, Texas Instruments Incorporated  
8.3 Feature Description  
The device can be configured using the G and G logic inputs to select receiver output. The high voltage or logic  
1 on the G pin allows the device to operate on an active-high, and having a low voltage or logic 0 on the G  
enables active low operation. These are simple ways to configure the logic to match that of the receiving or  
transmitting controller or microprocessor.  
10  
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8.4 Device Functional Modes  
The receivers implemented in these RS-485 device can be configured using the G and G logic pins to be  
enabled or disabled. This allows users to ignore or filter out transmissions as desired.  
1. Function Table(1)  
INPUT  
ENABLES  
OUTPUT  
Y
A - B (VID  
)
G
H
X
H
X
H
X
L
G
X
VID ≤ −0.2 V  
0.2 V < VID < -0.01 V  
0.01 V VID  
X
L
?
L
X
L
X
H
Z
L
H
OPEN  
OPEN  
H
X
H
X
L
Short circuit  
Open circuit  
H
H
X
(1) H = high level, L = low level, X = irrelevant, Z = high impedance  
(off), ? = indeterminate  
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9 Application and Implementation  
Information in the following applications sections is not part of the TI component  
specification, and TI does not warrant its accuracy or completeness. TI’s customers are  
responsible for determining suitability of components for their purposes. Customers should  
validate and test their design implementation to confirm system functionality.  
9.1 Application Information  
Extending SPI operation over RS-485 link.  
9.2 Typical Application  
The following block diagram shows an MCU host connected via RS-485 to a SPI slave device. This device can  
be an ADC, DAC, MCU, or other SPI slave peripheral.  
SN65LBC174A-EP  
SN65LBC173A-EP  
MCU or DSP  
SPI MASTER  
PERIPHERIAL  
SPI SLAVE  
SPISIMO  
SPI MOSI  
SPI CS  
GPIO or Tie  
Enabled  
SPI CS  
GPIO or Tie  
Enabled  
SPICLK  
SPI CLK  
GPIO Optional  
Handshaking  
GPIO Optional  
Handshaking  
SPISOMI  
SPI MISO  
Copyright © 2016, Texas Instruments Incorporated  
12. DSP-to-DSP Link via Serial Peripheral Interface  
9.2.1 Design Requirements  
This application can be implemented using standard SPI protocol on DSP or MCU devices. The interface is  
independent of the specific frame or data requirements of the host or slave device. An additional but not required  
handshake bit is provided that can be used for customer purposes.  
9.2.2 Detailed Design Procedure  
The interface design requirements are fairly straight forward in this single source/destination scenario. Trace  
lengths and cable lengths need to be matched to maximize SPI timing. If there is a benefit to put the interface to  
sleep, GPIOs can be used to control the enable signals of the transmitter and receiver. If GPIOs are not  
available, or constant uptime needed, both the enables on transmit and receive can be hard tied enabled.  
12  
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Typical Application (接下页)  
The link shown can operate at up to 50 Mbps, well within the capability of most SPI links.  
9.2.3 Application Curves  
500 mV  
A, B  
−500 mV  
20 ns  
5 V  
Y
0 V  
13. Receiver Inputs and Outputs, 50-Mbps Signaling Rate  
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13  
SN65LBC173A-EP  
ZHCSFQ1 NOVEMBER 2016  
www.ti.com.cn  
10 Power Supply Recommendations  
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-  
impedance power supplies.  
11 Layout  
11.1 Layout Guidelines  
For best operational performance of the device, use good PCB layout practices including:  
Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the  
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance  
power sources local to the analog circuitry.  
Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to  
the device as possible.  
Place termination resistor as close as possible to the input pins (if end point node).  
Keep trace lengths from input pins to buss as short as possible to reduce stub lengths and reflections on any  
nodes that are not end points of bus.  
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If  
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as  
opposed to in parallel with the noisy trace.  
11.2 Layout Example  
VDD  
1B  
1
2
3
4
5
6
7
8
VCC  
16  
0.1 F  
4B 15  
4A 14  
4Y 13  
1A  
1Y  
Termination Resistor  
Reduce logic signal trace  
when possible  
G
2Y  
G
12  
3Y 11  
3A 10  
2A  
2B  
3B  
9
14. Layout with PCB Recommendations  
14  
版权 © 2016, Texas Instruments Incorporated  
SN65LBC173A-EP  
www.ti.com.cn  
ZHCSFQ1 NOVEMBER 2016  
12 器件和文档支持  
12.1 接收文档更新通知  
如需接收文档更新通知,请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册  
后,即可每周定期收到已更改的产品信息。有关更改的详细信息,请查阅已修订文档中包含的修订历史记录。  
12.2 社区资源  
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective  
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of  
Use.  
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration  
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help  
solve problems with fellow engineers.  
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and  
contact information for technical support.  
12.3 商标  
E2E is a trademark of Texas Instruments.  
LinBiCMOS is a registered trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
12.4 静电放电警告  
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可  
能会损坏集成电路。  
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可  
能会导致器件与其发布的规格不相符。  
12.5 Glossary  
SLYZ022 TI Glossary.  
This glossary lists and explains terms, acronyms, and definitions.  
版权 © 2016, Texas Instruments Incorporated  
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ZHCSFQ1 NOVEMBER 2016  
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13 机械、封装和可订购信息  
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对  
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本,请查阅左侧的导航栏。  
16  
版权 © 2016, Texas Instruments Incorporated  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
SN65LBC173AMDREP  
V62/13623-02XE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
D
D
16  
16  
2500 RoHS & Green  
2500 RoHS & Green  
NIPDAU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
-55 to 125  
-55 to 125  
LBC173AEP  
LBC173AEP  
NIPDAU  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
Addendum-Page 2  
重要声明和免责声明  
TI 均以原样提供技术性及可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资  
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