SN65LBC173DR [TI]
四路低功耗差分线路接收器 | D | 16 | -40 to 85;
| 型号： | SN65LBC173DR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 四路低功耗差分线路接收器 | D | 16 | -40 to 85 驱动 信息通信管理 光电二极管 接口集成电路 线路驱动器或接收器 驱动程序和接口 |
| 文件： | 总10页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LBC173, SN75LBC173
QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS
SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000
Meets or Exceeds the Requirements of
D OR N PACKAGE
(TOP VIEW)
ANSI Standards EIA/TIA-422-B,
EIA/TIA-423-B, RS-485, and ITU
Recommendations V.10 and V.11.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
1B
1A
CC
Designed to Operate With Pulse Durations
as Short as 20 ns
4B
4A
4Y
G
1Y
Designed for Multipoint Bus Transmission
on Long Bus Lines in Noisy Environments
G
2Y
Input Sensitivity . . . ±200 mV
3Y
3A
3B
2A
2B
Low-Power Consumption . . . 20 mA Max
Open-Circuit Fail-Safe Design
GND
Pin Compatible With SN75173 and
AM26LS32
description
The SN65LBC173 and SN75LBC173 are monolithic quadruple differential line receivers with 3-state outputs.
Both are designed to meet the requirements of the ANSI standards EIA/TIA-422-B, EIA/TIA-423-B, RS-485,
and ITU Recommendations V.10 and V.11. The devices are optimized for balanced multipoint bus transmission
at data rates up to and exceeding 10 million bits per second. The four receivers share two ORed enable inputs,
one active when high, the other active when low.
Each receiver features high input impedance, input hysteresis for increased noise immunity, and input
sensitivity of ±200 mV over a common-mode input voltage range of 12 V to –7 V. Fail-safe design ensures that
iftheinputsareopencircuited, theoutputisalwayshigh. BothdevicesaredesignedusingtheTexasInstruments
proprietary LinBiCMOS technology that provides low power consumption, high switching speeds, and
robustness.
These devices offer optimum performance when used with the SN75LBC172 or SN75LBC174 quadruple line
drivers. The SN65LBC173 and SN75LBC173 are available in the 16-pin DIP (N) and SOIC (D) packages.
The SN65LBC173 is characterized over the industrial temperature range of –40°C to 85°C. The SN75LBC173
is characterized for operation over the commercial temperature range of 0°C to 70°C.
FUNCTION TABLE
(each receiver)
ENABLES
DIFFERENTIAL INPUTS
A–B
OUTPUT
Y
G
G
H
X
X
L
H
H
V
ID
≥ 0.2 V
H
X
X
L
?
?
–0.2 V < V < 0.2 V
ID
H
X
X
L
L
L
V
ID
≤ –0.2 V
X
L
H
Z
H
X
X
L
H
H
Open Circuit
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinBiCMOS is a trademark of Texas Instruments Incorporated.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC173, SN75LBC173
QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS
SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000
†
logic symbol
logic diagram (positive logic)
4
G
4
≥ 1
G
G
12
12
G
2
1A
1
2
1
3
1A
1B
3
5
1Y
1Y
2Y
3Y
4Y
1B
6
2A
7
2B
10
3A
9
3B
14
4A
15
4B
5
11
13
2Y
3Y
4Y
6
7
2A
2B
10
9
3A
3B
11
13
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
14
15
4A
4B
schematics of inputs and outputs
EQUIVALENT OF A AND B INPUTS
TYPICAL OF ALL OUTPUTS
TYPICAL OF G AND G INPUTS
V
CC
V
CC
V
CC
100 kΩ
3 kΩ
A Only
Receiver
Input
Input
18 kΩ
Y Output
100 kΩ
B Only
12 kΩ
1 kΩ
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC173, SN75LBC173
QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS
SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
CC
Input voltage, V (A or B inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
I
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
ID
Voltage range at Y, G, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
+ 0.5 V
CC
Operating free-air temperature range, T : SN65LBC173 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
A
SN75LBC173 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
D
N
1100 mW
1150 mW
8.7 mW/°C
9.2 mW/°C
708 mW
736 mW
578 mW
598 mW
recommended operating conditions
MIN NOM
MAX
5.25
12
UNIT
V
Supply voltage, V
CC
4.75
–7
5
Common-mode input voltage, V
IC
V
Differential input voltage, V
±6
V
ID
High-level input voltage, V
IH
2
V
G inputs
Low-level input voltage, V
0.8
–8
16
85
70
V
IL
High-level output current, I
mA
mA
OH
OL
Low-level output current, I
SN65LBC173
SN75LBC173
–40
0
Operating free-air temperature, T
°C
A
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC173, SN75LBC173
QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS
SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
Positive-going input threshold voltage
Negative-going input threshold voltage
I
I
= –8 mA
= 16 mA
0.2
IT+
IT–
hys
IK
O
–0.2
V
O
Hysteresis voltage (V
IT+
– V
)
45
–0.9
4.5
mV
V
IT–
Enable input clamp voltage
High-level output voltage
Low-level output voltage
I = –18 mA
–1.5
I
V
V
V
V
V
V
V
V
V
V
= 200 mV,
I
I
= –8 mA
= 16 mA
3.5
V
OH
OL
ID
ID
O
OH
= –200 mV,
0.3
0.5
±20
1
V
OL
I
High-impedance-state output current
= 0 V to V
= 12 V,
= 12 V,
= –7 V,
= –7 V,
= 5 V
µA
mA
mA
mA
mA
µA
µA
mA
OZ
CC
V
V
V
V
= 5 V, Other inputs at 0 V
= 0 V, Other inputs at 0 V
= 5 V, Other inputs at 0 V
= 0 V, Other inputs at 0 V
0.7
0.8
IH
IH
IH
IH
IH
IL
CC
CC
CC
CC
1
I
I
Bus input current
A or B inputs
–0.5
–0.4
–0.8
–0.8
±20
–20
I
I
I
High-level input current
Low-level input current
Short-circuit output current
IH
= 0 V
IL
= 0
–80 –120
OS
O
Outputs enabled,
Outputs disabled
I
O
= 0,
V
ID
= 5 V
11
20
I
Supply current
mA
CC
0.9
1.4
†
All typical values are at V
= 5 V and T = 25°C.
A
CC
switching characteristics, V
= 5 V, C = 15 pF, T = 25°C
L A
CC
PARAMETER
TEST CONDITIONS
MIN
11
TYP
22
22
17
18
35
25
0.5
5
MAX
30
30
30
30
45
40
6
UNIT
ns
t
t
t
t
t
t
t
t
Propagation delay time, high- to low-level output
PHL
PLH
PZH
PZL
PHZ
PLZ
sk(p)
t
V
ID
= –1.5 V to 1.5 V, See Figure 1
Propagation delay time, low- to high-level output
Output enable time to high level
11
ns
See Figure 2
See Figure 3
See Figure 2
See Figure 3
See Figure 2
See Figure 1
ns
Output enable time to low level
ns
Output disable time from high level
Output disable time from low level
ns
ns
Pulse skew (|t
– t
PHL PLH
|)
ns
Transition time
10
ns
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC173, SN75LBC173
QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS
SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
1.5 V
Generator
(see Note A)
Input
t
0 V
0 V
50 Ω
Output
= 15 pF
– 1.5 V
C
t
L
PLH
PHL
(see Note B)
V
OH
OL
90%
10%
Output
1.3 V
1.3 V
V
t
t
t
t
2 V
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 1. t and t Test Circuit and Voltage Waveforms
pd
t
V
CC
2 kΩ
Input
Output
1.5 V
S1
3 V
0 V
1.3 V
1.3 V
C
= 15 pF
L
(see Note B)
t
t
PHZ
0.5 V
PZH
5 kΩ
See Note C
V
OH
Output
S1 Open
1.3 V
S1 Closed
2 V
≈ 1.4 V
0 V
Generator
(see Note A)
VOLTAGE WAVEFORMS
50 Ω
(see Note D)
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, t ≤ 6 ns,
r
t ≤ 6 ns, Z = 50 Ω.
f
O
B.
C
includes probe and jig capacitance.
L
C. All diodes are 1N916 or equivalent.
D. To test the active-low enable G, ground G and apply an inverted input waveform to G.
Figure 2. t
and t
Test Circuit and Voltage Waveforms
PHZ
PZH
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC173, SN75LBC173
QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS
SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
CC
2 kΩ
Output
1.5 V
3 V
0 V
Input
t
C
= 15 pF
1.3 V
1.3 V
L
(see Note B)
5 kΩ
See Note C
t
PZL
PLZ
S2 Closed
≈ 1.4 V
S2 Open
2 V
Output
1.3 V
Generator
V
OL
(see Note A)
S2
0.5 V
VOLTAGE WAVEFORMS
50 Ω
(see Note D)
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, t ≤ 6 ns,
r
t ≤ 6 ns, Z = 50 Ω.
f
O
B.
C
includes probe and jig capacitance.
L
C. All diodes are 1N916 or equivalent.
D. To test the active-low enable G, ground G and apply an inverted input waveform to G.
Figure 3. t
and t
Test Circuit and Voltage Waveforms
PZL
PLZ
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
DIFFERENTIAL INPUT VOLTAGE
5.5
5
4.5
4
V
T
A
= 5 V
= 25°C
CC
V
CC
= 5.25 V
4.5
4
3.5
3
V
CC
= 5 V
3.5
3
V
CC
= 4.75 V
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
V
T
A
= 0.2 V
ID
= 25°C
0.5
0
0
– 4 – 8 – 12 – 16 – 20 – 24 – 28 – 32 – 36 – 40
0
10 20 30 40 50 60 70 80 90 100
I
– High-Level Output Current – mA
V
ID
– Differential Input Voltage – mV
OH
Figure 4
Figure 5
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC173, SN75LBC173
QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS
SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000
TYPICAL CHARACTERISTICS
AVERAGE SUPPLY CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
vs
FREQUENCY
14
12
10
8
660
600
540
480
420
360
300
240
180
120
60
T
V
CC
= 25°C
= 5 V
A
T
V
V
= 25°C
A
= 5 V
= 200 mV
CC
ID
6
4
2
0
0
10 K
100 K
2 M
10 M
100 M
0
3
6
9
12 15 18 21 24 27 30
f – Frequency – Hz
I
– Low-Level Output Current – mA
OL
Figure 6
Figure 7
BUS
INPUT CURRENT
vs
INPUT VOLTAGE
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
(COMPLEMENTARY INPUT AT 0 V)
1
0.8
24.5
24
T
V
= 25°C
V
C
= 5 V
= 15 pF
= ±1.5 V
A
CC
L
= 5 V
CC
V
IO
0.6
0.4
t
PHL
0.2
23.5
23
0
– 0.2
– 0.4
– 0.6
– 0.8
– 1
t
PLH
22.5
22
The shaded region of this graph represents
more than 1 unit load per RS-485.
– 8 – 6 – 4 – 2
0
2
4
6
8
10 12
– 40
– 20
0
20
40
60
80
100
V – Input Voltage – V
I
T
A
– Free-Air Temperature – °C
Figure 8
Figure 9
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC173, SN75LBC173
QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS
SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–8°
0.044 (1,12)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC173, SN75LBC173
QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS
SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000
MECHANICAL DATA
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PIN SHOWN
PINS **
14
16
18
20
DIM
0.775
(19,69)
0.775
(19,69)
0.920
(23.37)
0.975
(24,77)
A MAX
A
16
9
0.745
(18,92)
0.745
(18,92)
0.850
(21.59)
0.940
(23,88)
A MIN
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.020 (0,51) MIN
0.310 (7,87)
0.290 (7,37)
0.035 (0,89) MAX
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
14/18 PIN ONLY
4040049/C 08/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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Copyright 2000, Texas Instruments Incorporated
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