SN65LVDM320DGGR [TI]
HIGH-SPEED DIFFERENTIAL 8-BIT REGISTERED TRANSCEIVER; 高速差分8位寄存收发器
| 型号： | SN65LVDM320DGGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-SPEED DIFFERENTIAL 8-BIT REGISTERED TRANSCEIVER |
| 文件： | 总32页 (文件大小：433K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDM320
SLLS462 – AUGUST 2001
HIGH-SPEED DIFFERENTIAL 8-BIT REGISTERED TRANSCEIVER
D
D
D
D
Open-Circuit Differential Receiver Fail Safe
Assures a Low-Level Output
FEATURES
D
D
8-Bit Bidirectional Data Storage Register With
Full Parallel Access
Reset at Power Up
12-kV Bus-Pin ESD Protection
†
Parallel Transfer Rates
Bus Pins Remain High-Impedance When
– Buffer Mode: Up to 475 Megatransfers
– Flip-Flop Mode: Up to 300 Megatransfers
– Latch Mode: Up to 300 Megatransfers
Disabled or With V
Below 1.5 V for
CC
Power-Up/Down Glitch-Free Performance and
Hot Plugging
D
D
Operates With a Single 3.3-V Supply
D
5-V Tolerant LVCMOS Inputs
Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV Across a
50-Ω Load
APPLICATIONS
D
D
D
D
Telecom Switching
D
D
D
Bus and Logic Loopback Capability
Very Low Radiation Emission
Printers and Copiers
Audio Mixing Consoles
Automated Test Equipment
Low Skew Performance
– Pulse Skew Less Than 100 ps
– Output Skew Less Than 320 ps
– Part-to-Part Skew Less Than 1 ns
logic diagram
OEB
OMODE1
OMODE2
LPBK
NODE
CLK/LEAB
D
D
Q
Q
BY
C
BZ
Q
Q
DA
C
IMODE1
IMODE2
CLK/LEBA
Q
Q
D
RA
C
Q
Q
D
C
OEA
LPBK
ENR
One-of-Eight Channels
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
Parallel data transfer through all channels simultaneously as defined by TIA/EIA–644 with t of t less than 30%of the unit interval.
r
f
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2001, Texas Instruments Incorporated
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SN65LVDM320
SLLS462 – AUGUST 2001
DESCRIPTION
The SN65LVDM320 is an 8-bit data storage register with differential line drivers and receivers that are
electrically compatible with ANSI EIA/TIA-644 for multipoint architectures with standard-compliant parallel
transfer rates of 475 Mbps. The SN65LVDM320 includes transmitter and receiver data registers that remain
active regardless of the state of their associated outputs.
The logic element for data flow in each direction is configured by mode-control inputs. IMODE1 and IMODE2
control data flow in the B-to-A (bus side to digital side) direction when configured as a buffer, a D-type flip-flop,
or a D-type latch. OMODE1 and OMODE2 control data flow in each of the operating modes for the A-to-B (digital
side to bus side) direction. When configured in buffer mode, input data appears at the output port. In the flip-flop
mode, data is stored on the rising edge of the appropriate clock input, CLKAB/LEAB or CLKBA/LEBA. In the
latch mode, this clock pin also serves as an active-high transparent latch enable.
Data flow is further controlled by the A-side loopback (LPBK) input. When LPBK is high, DA input data is looped
back to the RA output. B-side bus data is looped back to the bus in latch mode by means of the IMODE and
OMODE logic states.
The A-side output enable/disable control is provided by OEA. When OEA is low or V
is less than 2 V, the A
CC
side is in the high-impedance state. When OEA is high, the A side is active (high or low logic levels). The B-side
output enable/disable control is provided by OEB. When OEB is low or V is less than 2 V, the B side is in the
CC
high impedance state. When OEB is high, the B side is active (high or low logic levels).
The A-to-B and B-to-A logic elements are active regardless of the state of their associated outputs. New data
can be entered (in latch and flip-flop modes) or previously stored data can be retained while the associated
outputs are in the high-impedance or inactive states. The SN65LVDM320 also includes internally isolated
analog (B-side) and digital (A-side) grounds for enhanced operation.
The SN65LVDM320 is characterized for operation from –40°C to 85°C.
Table 1. Mode Functions
INPUTS
CLK/LEBA OEA OEB ENR OMODE1 OMODE2 IMODE1 IMODE2
MODE
CLK/LEAB
LPBK
X
X
L
L
X
X
X
X
X
X
Isolation
A-to-B buffer mode
(see Figure 1)
X
X
X
H
X
L
L
X
X
X
X
A-to-B flip-flop mode
(see Figure 2)
↑
X
X
X
X
H
H
X
X
L
H
L
X
X
X
X
H
(B follows A)
A-to-B latch mode
(see Figure 3)
H
X
L
(B latched)
B-to-A buffer mode
(see Figure 4)
X
X
X
H
H
L
L
L
L
X
X
X
X
L
L
L
L
L
B-to-A flip-flop mode
(see Figure 5)
↑
H
H
(A follows B)
B-to-A latch mode
(see Figure 6)
X
H
L
L
X
X
H
L
L
L
(A latched)
Bus loopback latch mode
(see Figure 7)
X
X
X
X
L
L
L
H
H
H
X
H
X
H
X
H
X
L
DA to RA loopback mode
(see Figures 8 through 10)
H
H
H = high level, L = low level, X = don’t care, ↑ = low-to-high
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SN65LVDM320
SLLS462 – AUGUST 2001
pin assignments
Table 2. Pin Descriptions
SN65LVDM320DGG
(Marked as LVDM320)
(TOP VIEW)
PIN
DESCRIPTION
NAME
AGND
NO.
36, 44, 54, Analog (B-side) ground
58, 62
1DA
1RA
2DA
2RA
DGND
VCC
3DA
3RA
4DA
4RA
1BY
1BZ
AGND
VCC
2BY
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
1BY–8BY &
1BZ–8BZ
64 & 63,
60 & 59,
56 & 55,
52 & 51,
46 & 45,
42 & 41,
38 & 37,
34 & 33
Differential I/O pair
3
4
5
2BZ
6
AGND
VCC
3BY
7
8
CLK/LEBA
CLK/LEAB
1DA–8DA
18
14
B-side to A-side clock input or latch enable
A-side to B-side clock input or latch enable
9
3BZ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DGND
VCC
OMODE1
CLK/LEAB
DGND
VCC
OMODE2
CLK/LEBA
DGND
VCC
AGND
VCC
4BY
1, 3, 7, 9, Single-ended input
21, 25, 29,
31
DGND
ENR
5, 11, 15, Digital (A-side) ground
19, 23, 27
4BZ
IMODE1
IMODE2
LPBK
OEA
5BY
39
Receiver differential data enable
IMODE1
IMODE2
50,
49
B-side to A-side buffer, flip-flop, or latch mode control and
bus loopback control (see Table 3)
LPBK
OEA
OEB
48
47
40
A-side loopback enable
A-side output enable
B-side output enable
5BZ
5DA
5RA
DGND
VCC
6DA
6RA
DGND
VCC
7DA
7RA
AGND
VCC
6BY
OMODE1,
OMODE2
13,
17
A-side to B-side buffer, flip-flop, or latch mode control and
bus loopback control (see Table 3)
6BZ
RA
2, 4, 8, 10, Single-ended output
22, 26, 30,
32
OEB
ENR
7BY
VCC
6, 12, 16, Supply voltage
20, 24, 28,
35, 43, 53,
7BZ
AGND
VCC
8BY
57, 61
8DA
8RA
8BZ
Table 3. IMODE Logic
Table 4. OMODE Logic
MODE FUNCTION
(B SIDE TO A SIDE)
MODE FUNCTION
(A SIDE TO B SIDE)
IMODE1
IMODE2
IMODE1
IMODE2
0
0
1
1
0
1
0
1
Buffer
0
0
1
1
0
1
0
1
Buffer
Flip-Flop
Latch
Flip-Flop
Latch
†
†
Bus loopback
Bus loopback
†
All IMODE and OMODE pins must be high for the differential bus loopback latch mode.
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SN65LVDM320
SLLS462 – AUGUST 2001
mode function diagrams
OEB (High)
OMODE1 (Low)
OMODE2 (Low)
BY
BZ
DA
Figure 1. A-to-B Buffer Mode
OEB (High)
OMODE1 (Low)
OMODE2 (High)
CLK/LEAB (↑)
D
Q
BY
BZ
C
DA
Figure 2. A-to-B Flip-Flop Mode
OEB (High)
OMODE1 (High)
OMODE2 (Low)
CLK/LEAB
(Low to High)
BY
BZ
D
C
Q
DA
Figure 3. A-to-B Latch Mode
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SN65LVDM320
SLLS462 – AUGUST 2001
mode function diagrams (continued)
OEB (Low)
IMODE1 (Low)
IMODE2 (Low)
BY
BZ
RA
OEA (High)
LPBK (Low)
ENR (Low)
One-of-Eight Channels
Figure 4. B-to-A Buffer Mode
OEB (Low)
IMODE1 (Low)
IMODE2 (High)
CLK/LEAB (↑)
BY
BZ
Q
D
C
RA
OEA (High)
LPBK (Low)
ENR (Low)
One-of-Eight Channels
Figure 5. B-to-A Flip-Flop Mode
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SN65LVDM320
SLLS462 – AUGUST 2001
mode function diagrams (continued)
OEB (Low)
IMODE1 (High)
IMODE2 (Low)
CLK/LEAB
(Low to High)
BY
BZ
RA
Q
D
C
OEA (High)
LPBK (Low)
ENR (Low)
One-of-Eight Channels
Figure 6. B-to-A Latch Mode
OEB (Low to Receive,
High to Transmit)
OMODE1 (High)
OMODE2 (High)
BY
BZ
IMODE1 (High)
IMODE2 (High)
CLK/LEBA
Q
Q
D
C
D
C
LPBK (Low)
ENR (Low to Receive,
High to Transmit)
One-of-Eight Channels
Figure 7. Bus Loopback Latch Mode
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SN65LVDM320
SLLS462 – AUGUST 2001
mode function diagrams (continued)
OEB (Low)
OMODE1 (Low)
OMODE2 (Low)
LPBK
NODE
BY
BZ
DA
IMODE1 (Low)
IMODE2 (Low)
RA
OEA (High)
LPBK (High)
ENR (High)
One-of-Eight Channels
Figure 8. DA to RA Buffer Mode
OEB (Low)
OMODE1 (Low)
OMODE2 (High)
CLK/LEAB (↑)
LPBK
NODE
D
Q
BY
BZ
C
DA
IMODE1 (Low)
IMODE2 (High)
CLK/LEBA (↑)
Q
D
RA
C
OEA (High)
LPBK (High)
ENR (High)
One-of-Eight Channels
Figure 9. DA to RA Flip-Flop Mode
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SN65LVDM320
SLLS462 – AUGUST 2001
mode function diagrams (continued)
OEB (Low)
OMODE1 (High)
OMODE2 (Low)
CLK/LEAB (Low to High)
LPBK
NODE
BY
BZ
D
Q
DA
C
IMODE1 (High)
IMODE2 (Low)
CLK/LEBA (Low to High)
RA
Q
Q
D
C
OEA (High)
LPBK (High)
ENR (High)
One-of-Eight Channels
Figure 10. DA to RA Latch Mode
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SN65LVDM320
SLLS462 – AUGUST 2001
equivalent input and output schematic diagrams
V
CC
V
CC
50 Ω
DA, OEB, or ENR Input
5 Ω
RA Output
7 V
7 V
300 kΩ
V
CC
V
CC
300 kΩ
300 kΩ
10 kΩ
5 Ω
BY or BZ Output
7 V
Z Input
Y Input
7 V
7 V
Table 5. LVDM Receiver Function Table
BUS INPUTS
= V – V
Z
OUTPUT
V
ID
Y
V
≥ 100 mV
H
?
L
L
ID
–100 mV < V < 100 mV
ID
V
ID
≤ –100 mV
Open
H = high-level, L = low-level, ? = indeterminate
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SN65LVDM320
SLLS462 – AUGUST 2001
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Voltage range (TTL pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Voltage range BY and BZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Electrostatic discharge:
Y, Z, and GND (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A: 12 kV, B: 600 V
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A: 7 kV, B: 500 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see Dissipation Rating Table)
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883E Method 3015.7.
DISSIPATION RATING TABLE
DERATING FACTOR
T
= 70°C
T = 85°C
A
POWER RATING
A
PACKAGE
T
A
≤ 25°C
(see Note 3)
POWER RATING
ABOVE T = 25°C
A
DGG (see Note 4)
DGG (see Note 5)
2094 mW
3765 mW
16.7 mW/°C
30.1 mW/°C
1340 mW
2410 mW
1089 mW
1958 mW
NOTES: 3. This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
4. Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51–3.
5. Tested in accordance with the High-K thermal metric definitions of EIA/JESD51–7.
recommended operating conditions
MIN NOM
MAX
UNIT
Supply voltage, V
CC
3
2
3.3
3.6
V
V
V
V
High-level input voltage, V
IH
Low-level input voltage, V
0.8
0.6
IL
Magnitude of differential input voltage, |V
|
0.1
ID
ŤVIDŤ
2
ŤVIDŤ
2
2.4 –
Common-mode input voltage, V
IC
V
V
CC
–0.8
Operating free-air temperature, T
–40
85
°C
A
supply current
PARAMETER
TEST CONDITIONS
Driver enabled, receiver enabled, R = 50 Ω
(DA, OEA, OEB to V , ENR to GND)
CC
MIN NOM
MAX
UNIT
L
75
130
mA
Driver disabled, receiver disabled
(DA, OEA, OEB to GND, ENR to V
1
60
20
3
100
40
mA
mA
mA
)
CC
I
Supply current
CC
Driver enabled, receiver disabled, R = 50 Ω
L
(DA, OEB, ENR to V , OEA to GND)
CC
Driver disabled, receiver enabled
(DA, OEB, ENR to GND, OEA to V
)
CC
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SN65LVDM320
SLLS462 – AUGUST 2001
electrical characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
mV
V
|V
|
Differential output voltage magnitude
247
330
454
OD
R
= 50 Ω,
See Figures 11 and 12
L
Change in differential output voltage magnitude between
logic states
‡
–50
∆|V
|
50
1.375
50
OD
V
Steady-state common-mode B-port output voltage
1.125
OC(SS)
Change in steady-state common-mode B-port output voltage
between logic states
∆V
OC(SS)
–50
See Figure 13
mV
V
Peak-to-peak common-mode B-port output voltage
RA-port high-impedance output current
DA port high-level input current
50
150
10
OC(PP)
I
V
V
V
V
V
V
= 0 V or 3.6 V
= 2 V
–10
µA
µA
µA
mA
mA
µA
OZ
O
I
IH
20
IH
I
IL
DA port low-level input current
= 0.8 V
10
IL
or V
= 0
= 0
OZ
–10
–10
–10
10
OY
OD
OD
I
Differential short-circuit output current
OS
10
I
Power-off differential output current
= 2.4 V, V
= 1.5 V
CC
10
O(OFF)
V
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
High-level RA port output voltage
100
IT+
See Figure 16 and Table 6
mV
V
IT–
V
OH
V
OL
–100
I
= –8 mA
2.4
V
V
OH
Low-level RA port output voltage
I
= 8 mA
0.4
OL
V = 0 V
–35
–10
µA
µA
I
I
I
Input current (Y or Z inputs)
V = 2.4 V
I
V
V
= 0 and V = 100 mV,
IZ
IY
IY
I
Differential input current
I
– I
–10
–20
10
20
µA
ID
IY IZ
= 2.4 V and V = 2.3 V
IZ
I
Power-off input current (Y or Z inputs)
DA port Input capacitance
V
CC
0 V, V = 2.4 V
µA
pF
I(OFF)
I
C
V = 0.4 sin (4E6πt) + 0.5 V
I
5
6
(INA)
C
B-port Input capacitance
V = 0.4 sin (4E6πt) + 0.5 V
I
pF
(INB)
V
B-port crosstalk output voltage (zero-to-peak)
See Figure 20
0.1
mV
O(0PX)
†
‡
All typical values are at 25°C and with a 3.3-V supply voltage.
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
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SN65LVDM320
SLLS462 – AUGUST 2001
device switching characteristics over recommended operating conditions (unless otherwise
noted)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
TYP MAX
UNIT
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
1.4
1.4
3.3
3.3
5.2
5.3
PLH
DA (buffer mode)
See Figures 1 & 14
BY, BZ
RA
ns
PHL
BY, BZ (buffer
mode) See
See Figures 4 & 17
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
2.5
2.5
4.3
4.3
6.2
6.5
PLH
ns
ns
ns
PHL
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
3
3
5.5
5.5
8.5
8.7
PLH
DA (latch mode)
See Figures 3 & 14
BY, BZ
RA
PHL
BY,BZ
(latch mode)
See Figure 6
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
4
4
6.5
6.5
9.3
9.8
PLH
PHL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
Output signal rise time B port
3.5
3.5
3.8
3.8
1.8
1.8
6.5
6.5
6.5
6.5
3.2
3.2
15
9.5
9.5
10.5
10.5
7
PLH
PHL
PLH
PHL
PLH
PHL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
PZH
PZL
r(B)
CLKAB
See Figures 2 & 22
BY, BZ
RA
ns
ns
ns
ns
ns
ns
ns
CLKBA
See Figures 5 & 23
DA
RA
See Figures 8 & 19
7
26
15
23
OEA
See Figure 20
RA
15
26
15
23
10
15
10
17
OEB
See Figure 15
BY, BZ
10
15
10
17
470
450
580
630
0.3
0.7
See Figure 14
ps
ps
Output signal fall time B port
f(B)
Output signal rise time A port
r(A)
See Figure 17
Output signal fall time A port
f(A)
†
Output skew channel-to-channel
ns
ns
ns
ns
sk(o)
sk(p)
Pulse skew (|t
Pulse skew (|t
– t
PHL PLH
|)—A-port
|)—B-port
t
t
– t
PHL PLH
0.7
0.6
sk(p)
‡
Part-to-part skew
sk(pp)
†
t
is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same
sk(o)
direction while driving identical specified loads.
‡
t
is the magnitude of the difference delay times between any specified terminals of two devices when both devices operate with the same
sk(pp)
supply voltages, at the same temperature, and have identical packages and test circuits.
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SN65LVDM320
SLLS462 – AUGUST 2001
timing requirements over recommended operating conditions (see Figure 21) (unless otherwise
noted)
MIN
TYP
MAX
UNIT
MHz
ns
f
t
CLK/LEAB or CLK/LEBA in flip-flop mode
Setup for flip-flop
300
max
0.2
1.0
1.9
1.0
Setup time
Hold time
SU
Setup for latch
ns
Hold time for flip-flop
Hold time for latch
ns
t
h
ns
PARAMETER MEASUREMENT INFORMATION
V
CC
I
OY
BY
I
I
V
OY
+ V
C
DA
2
V
OD
I
OZ
ENABLES
OEB
V
OY
H
L
L
BZ
V
IA
V
OC
OMODE1
OMODE2
V
OZ
Figure 11. Driver Voltage and Current Definitions
3.75 kΩ
BY
ENABLES
+
DA
OEB
H
L
L
0 V ≤ V
≤ 2.4 V
V
50 Ω
Input
test
_
OD
OMODE1
OMODE2
BZ
3.75 kΩ
Figure 12. VOD Test Circuit
V
OBY
25 Ω ±1% (2 Places)
BY
BZ
V
OBZ
V
OC(SS)
DA
Input
V
OC(PP)
C
= 2 pF
L
V
OC
V
OC
ENABLES
OEB
H
L
L
OMODE1
OMODE2
Figure 13. Test Circuit and Definitions for the Differential Common-Mode Output Voltage
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
r
f
pulse width = 500 ± 10 ns . C includes instrumentation and fixture capacitance within 0,06 m of the device under test. The measurement
L
of V
is made on test equipment with a –3-dB bandwidth of at least 300 MHz.
OC(PP)
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SN65LVDM320
SLLS462 – AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
BY
DA
C
= 2 pF
L
V
OD
Input
50 Ω ±1%
BZ
V
CC
CC
V
/2
Input
0 V
t
t
PHL
PLH
100%
80%
V
OD(H)
Output
0 V
V
OD(L)
20%
0%
t
t
r
f
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse
r
f
width = 10 ± 0.2 ns . C includes instrumentation and fixture capacitance within 0,06 m of the device under test.
L
Figure 14. Test Circuit, Timing, and Voltage Definitions for the DIfferential Output Signal
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SN65LVDM320
SLLS462 – AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
25 Ω ± 1% (2 Places)
BY
C
= 2 pF
L
DA
V
OD
+
BZ
1.2 V
OEB
Input
V
OBY
V
OBZ
–
V
OD
= (V
– V
)
OBZ
OBY
V
CC
CC
Input
V
/2
0 V
t
t
PHZ
PZH
DA = V
CC
V
OD(H)
Output
Input
50 mV
≡ 0 V
V
CC
V
CC
/2
0 V
t
t
PLZ
PZL
DA = 0 V
≡ 0 V
50 mV
V
OD(L)
Output
Figure 15. A-to-B Enable/Disable Time Test Circuit and Definitions
Y
RA
ENABLES
ENR
V
ID
Z
L
L
L
H
IMODE1
IMODE2
OEA
V
O
V
IC
V
IY
(V + V )/2
IY IZ
V
IZ
Figure 16. Voltage Definitions
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SN65LVDM320
SLLS462 – AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
Table 6. Receiver Minimum and Maximum Fail-Safe Input Threshold Test Voltages
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON-MODE
INPUT VOLTAGE
APPLIED VOLTAGES
V
IY
V
IZ
V
ID
V
IC
1.25 V
1.15 V
2.4 V
2.3 V
0.1 V
0 V
1.15 V
1.25 V
2.3 V
2.4 V
0 V
100 mV
–100 mV
100 mV
–100 mV
100 mV
–100 mV
600 mV
–600 mV
600 mV
–600 mV
600 mV
–600 mV
1.2 V
1.2 V
2.35 V
2.35 V
0.05 V
0.05 V
1.2 V
1.2 V
2.1 V
2.1 V
0.3 V
0 .3V
0.1 V
0.9 V
1.5 V
1.8 V
2.4 V
0 V
1.5 V
0.9 V
2.4 V
1.8 V
0.6 V
0 V
0.6 V
V
1.4 V
1 V
IY
V
V
IZ
RA
0.4 V
V
ID
ID
V
IY
V
IC
= 0 V
V
O
V
IZ
C = 10 pF
L
–0.4 V
t
t
PLH
PHL
V
V
V
V
O
OH
80%
20%
/2
CC
OL
t
t
r
f
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse
r
f
width = 10 ± 0.2 ns . C includes instrumentation and fixture capacitance within 0,06 m of the device under test.
L
Figure 17. Timing Test Circuit and Waveforms
V
IH
RA
DA
V
I
V
CC
V
IL
/2
2 V
V
O
t
t
PLH
LPBK
PHL
V
I
C = 10 pF
L
V
OH
V
CC
V
OL
/2
V
O
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse
r
f
width = 10 ± 0.2 ns . C includes instrumentation and fixture capacitance within 0,06 m of the device under test.
L
Figure 18. LPBK Timing Test Circuit and Waveforms
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SN65LVDM320
SLLS462 – AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
V
IH
RA
DA
V
V
I
V
CC
V
IL
/2
V
O
I
t
t
PLH
PHL
C
= 10 pF
L
V
OH
V
CC
V
OL
/2
V
O
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse
r
f
width = 10 ± 0.2 ns . C includes instrumentation and fixture capacitance within 0,06 m of the device under test.
L
Figure 19. DA to RA Timing Test Circuit and Waveforms
500 Ω
BY
RA
BZ
1.2 V
+
V
test
V
O
_
10 pF
OEA
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
r
f
pulse width = 500 ± 10 ns . C includes instrumentation and fixture capacitance within 0,06 m of the device under test.
L
2.5 V
1 V
V
TEST
BY
V
V
CC
OEA
RA
/2
CC
0 V
t
t
PLZ
PZL
2.5 V
1.4 V
V
OL
V
OL
+ 0.5 V
0 V
V
TEST
1.4 V
BY
V
V
CC
/2
OEA
RA
CC
0 V
t
t
PHZ
PZH
V
V
1.4 V
OH
OH
–0.5 V
0 V
Figure 20. B-to-A Enable/Disable Time Test Circuit and Definitions
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SN65LVDM320
SLLS462 – AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
V
I
D Input
V
M
GND
t
t
h
h
t
t
su
su
1/f
max
V
I
CLK/LEAB
or
V
M
CLK/LEBA
Input
GND
t
W
Figure 21. Setup and Hold Time Definition
OEB (High)
OMODE1 (Low)
OMODE2 (High)
D
Q
DA
BY
BZ
C
= 2 pF
L
C
V
OD
50 Ω ±1%
CLK/LEAB (↑)
V
CC
V
CC
/2
DA Input
0 V
t
= 0.5 ns
su
CLK/LEAB
t
t
PHL
PLH
V
OD
Output
~0 V
V
OD
= V
– V
OBY OBZ
Figure 22. A-to-B Flip-Flop Mode Timing Circuit
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SN65LVDM320
SLLS462 – AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
IMODE1 (Low)
IMODE2 (High)
CLK/LEBA (↑)
Q
D
C
RA Output
10 pF
BY
BZ
V
ID
Input
OEA (High)
LPBK (Low)
ENR (Low)
V
ID
= V
– V
BZ
BY
V
BY
V
BZ
0.4 V
0 V
V
ID
Input
–0.4 V
t
= 0.5 ns
su
CLK/LEBA
t
t
PHL
PLH
~V
CC
V
OH
RA Output
~V /2
CC
~0 V
Figure 23. B-to-A Flip-Flop Mode Timing Circuit
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SN65LVDM320
SLLS462 – AUGUST 2001
APPLICATION INFORMATION
abstract
This section discusses electrical and operational topics not previously covered in this document, such as error
detection and the device’s ability to synchronize clock signals or manage data transfer between systems with
different clock speeds. Basic applications of the analog and digital system diagnostic loopback functions and
timing considerations are also analyzed. The SN65LVDM320 is resistant, although not immune, to the effect
of setup and hold-time violations; therefore, the penalties of a violation are also examined.
introduction
The SN65LVDM320 is a versatile, multifunctional device with many applications. Low EMI, low crosstalk, and
high differential-current output makes the SN65LVDM320 ideally suited for sensitive multipoint applications and
low-impedance loads. Balanced differential signaling reduces noise coupling and allows high signaling rates.
Balanced means that the current flowing in each signal line is equal but opposite in direction, resulting in a field
canceling effect. This is one of the keys to the low-noise performance of an LVDS differential bus.
Balanced differential input signals eliminate induced noise with efficient common mode rejection (CMR).
Internal chip design techniques reduce noise generated by inductive and capacitive mutual coupling, thereby
increasing signal integrity. One of the techniques employed to reduce internal noise is the design of separate,
dedicated grounds for the single-ended and differential circuitry incorporated within the device.
applications
The SN65LVDM320 may be used to connect major system blocks, including parallel processors, DRAMs,
fast-cache SRAMs, and complex ASIC gate arrays. It effectively transceives the addresses, data, and control
signals of these integrated-circuit elements to and from system blocks and backplanes.
The SN65LVDM320 not only facilitates extremely-high parallel burst-transfer rates, but in buffer mode, can
move a constant stream of data at 475 Mbps through all of the eight channels simultaneously for a total data
throughput exceeding 5 Gbps (transfer rate).
Deskewing clock signals is a requirement in many complex high-speed circuits, and the SN65LVDM320
performs this function at synchronous parallel transfers of 300 megatransfers per second (Mxferps) with
very-low channel-to-channel output skew.
The SN65LVDM320 is also ideally suited for connecting system blocks operating at different clock speeds.
When OEA and OEB are low, the system on the A-side of the device may be operated independently of the
system on the B-side.
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SN65LVDM320
SLLS462 – AUGUST 2001
APPLICATION INFORMATION
diagnostics and error detection
OEB (High)
OMODE1 (High)
OMODE2 (Low)
CLK/LEAB
(Low to High)
LPBK
NODE
D
Q
BY
BZ
C
DA
IMODE1 (High)
IMODE2 (Low)
CLK/LEBA
(Low to High)
Q
D
RA
C
OEA (High)
LPBK (High)
ENR (High)
One-of-Eight Channels
Figure 24. Loopback Error Detection
It is not a requirement that the driver be disabled (OEB low) during loopback. The driver may be enabled (OEB
high) while loopback is engaged at any time without damaging the circuit. The loopback configuration in
Figure 24withthedifferentialdriverenabledprovideserrorassessmentinwhichtransmitteddataisloopedback
and compared to the original data by the microprocessor/microcontroller host. This may be implemented in
buffer, flip-flop, or in the latch mode shown in Figure 24, and in accordance with the logic of Tables 2 and 3.
The SN65LVDM320 has been designed to improve a circuit’s fault detection capabilities. 100% of the circuitry
of the SN65LVDM320 may be functionally checked by activating the A-side and B-side loopback modes. With
this functionality, a problem rack, card, circuit block, and even a chip can be located without the burden of
boundary-scan protocols.
Traditionally, testability functions such as read-back, pattern insertion, and functional hardware test control
require additional part count, connector pins, board space, power, and cost. However, the SN65LVDM320
provides full circuit observability and controllability within the package of an 8-bit LVDM transceiver.
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SN65LVDM320
SLLS462 – AUGUST 2001
APPLICATION INFORMATION
metastability in latches and flip-flops
Interfacing the asynchronous world to synchronous logic systems can cause problems. Latches and flip-flops,
or basically, registers which are normally considered to have only two stable states (low and high) actually have
a third state, the metastable state. Metastability can occur when the setup or the hold time is violated and the
latch remains balanced in its threshold region. While in this metastable state, system noise can trigger either
a high or low state.
DA
D1
D3
Q
D4
D2
CLK/LEAB
OEB (High)
Figure 25. The A-Side to B-Side Signal Path
OMODE1 (High)
OMODE2 (Low)
BY
BZ
DA
D
C
Q
CLK/LEAB
Figure 26. SN65LVDM320 D-Type latch
The SN65LVDM320 D-type latch circuitry of Figure 26 is shown in Figure 25. When data at pin DA is applied
to D1, data is internally applied to D2. Therefore, when the CLK/LEAB pin is low, the outputs of D1 and D2 are
high and the D3/D4 R-S latch is latched and stable. When CLK/LEAB transitions to high, the latch is transparent
to the data input to DA and Q equals DA.
If data changes during the setup to hold time period, it is possible for the D1 and D2 outputs to be in the threshold
region of D3 and D4. Under these conditions, D3 and D4 could be perfectly balanced in a metastable condition,
allowing system noise to force the latch into a high or low state. This metastable condition can theoretically last
as long as 25 ns and cause a system to crash if care is not taken with the asynchronous/synchronous interface.
Although the SN65LVDM320 is metastable resistant by design, it is not entirely immune, and the setup and hold
times must adhere to those listed in the timing requirements section.
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SN65LVDM320
SLLS462 – AUGUST 2001
APPLICATION INFORMATION
typical SN65LVDM320 output waveform—the eye pattern
Figure 27 displays a receiver’s detection window in a typical LVDS output signal. When a receiver’s
differential-input voltage level drops, the system noise margin is reduced. Lowering the height enters the input
voltage threshold of a receiver, eventually closing the eye and corrupting the data. Jitter content decreases the
available time for accurate reception, and depending upon the application, may exceed 50% of the bit width
without any problems. To read more about the terms and sources of jitter, see the Jitter Analysis application
report, literature number SLLA075.
Noise Margin
Receiver Detection
Noise Margin
Window
Allowable Jitter
Figure 27. Receiver Detection Window in a Typical LVDS Driver Output
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SN65LVDM320
SLLS462 – AUGUST 2001
APPLICATION INFORMATION
typical SN65LVDM320 output waveform—the eye pattern (continued)
Figure 28. A Receiver Output With All Eight Channels at 630 Megatransfers per Second
The highest signaling rate measurable is 630 Mbps due to the limitations of the test circuit and equipment used
tocapturethisoscillograph. ItwascapturedwhilealleightchannelsweretransmittingdatainB-to-Abuffermode
from the differential bus to the receiver. The measurement is taken from a receiver output test point across a
1.75-in, 50-Ω characteristic impedance trace of a TI bench evaluation board.
test equipment
HP6236Bdcpowersupplyprovidestherequiredsupplyvoltageof3.3VfortheLVDM320. ATektronixHFS9009
signal generator is employed as a nonreturn-to-zero (NRZ), pseudo-random binary sequence (PRBS) signal
source for the LVDM320 and is adjusted as follows:
D
D
D
D
Pattern:
NRZ, PRBS
1.6 V
Differential input high level:
Differential input low level:
Transition time:
0.8 V
800 ps
At high signaling rates, the influence of the equipment used to measure a signal of concern must be minimized.
A Tektronix 794D oscilloscope and Tektronix P6247 differential probes are used in this test. Each probe has a
bandwidth of 1 GHz and the probe capacitance is less than 1 pF.
24
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SN65LVDM320
SLLS462 – AUGUST 2001
APPLICATION INFORMATION
DRIVER BUFFER MODE
HIGH-TO-LOW-LEVEL PROPAGATION TIME
DRIVER BUFFER MODE
LOW-TO-HIGH-LEVEL PROPAGATION TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
4.0
3.5
3.0
2.5
4.0
3.5
3.0
2.5
V
= 3.3 V
V
= 3.3 V
CC
CC
V
CC
= 3.0 V
V
CC
= 3.0 V
V
CC
= 3.6 V
V
CC
= 3.6 V
–40
25
85
–40
25
85
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 29
Figure 30
DRIVER LATCH MODE
LOW-TO-HIGH-LEVEL PROPAGATION TIME
DRIVER LATCH MODE
HIGH-TO-LOW-LEVEL PROPAGATION TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
6.5
6.0
5.5
5.0
4.5
4.0
7.0
6.5
6.0
5.5
5.0
4.5
4.0
V
= 3.3 V
CC
V
CC
= 3.0 V
V
CC
= 3.0 V
V
= 3.6 V
CC
V
CC
= 3.6 V
V
CC
= 3.3 V
–40
25
85
–40
25
85
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 31
Figure 32
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SN65LVDM320
SLLS462 – AUGUST 2001
APPLICATION INFORMATION
DRIVER FLIP-FLOP MODE
LOW-TO-HIGH-LEVEL PROPAGATION TIME
DRIVER FLIP-FLOP MODE
HIGH-TO-LOW-LEVEL PROPAGATION TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
7.5
7.0
6.5
6.0
5.5
5.0
4.5
7.5
7.0
6.5
6.0
5.5
5.0
4.5
V
CC
= 3.3 V
V
= 3.3 V
CC
V
CC
= 3.0 V
V
CC
= 3.0 V
V
CC
= 3.6 V
V
= 3.6 V
CC
–40
25
85
–40
25
85
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 33
Figure 34
RECEIVER BUFFER MODE
RECEIVER BUFFER MODE
LOW-TO-HIGH-LEVEL PROPAGATION TIME
HIGH-TO-LOW-LEVEL PROPAGATION TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
5.0
4.5
4.0
3.5
5.5
V
CC
= 3.3 V
V
CC
= 3.3 V
5.0
4.5
4.0
3.5
V
CC
= 3.0 V
V
CC
= 3.0 V
V
CC
= 3.6 V
V
CC
= 3.6 V
–40
25
–40
25
85
85
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 35
Figure 36
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SN65LVDM320
SLLS462 – AUGUST 2001
APPLICATION INFORMATION
RECEIVER LATCH MODE
LOW-TO-HIGH-LEVEL PROPAGATION TIME
vs
RECEIVER LATCH MODE
HIGH-TO-LOW-LEVEL PROPAGATION TIME
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
7.5
7.0
6.5
6.0
5.5
5.0
7.5
7.0
6.5
6.0
5.5
V
CC
= 3.3 V
V
CC
= 3.0 V
V
CC
= 3.0 V
V
CC
= 3.6 V
V
CC
= 3.6 V
V
CC
= 3.3 V
25
–40
25
–40
85
85
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 37
Figure 38
RECEIVER FLIP-FLOP MODE
RECEIVER FLIP-FLOP MODE
HIGH-TO-LOW-LEVEL PROPAGATION TIME
LOW-TO-HIGH-LEVEL PROPAGATION TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
8.0
7.5
7.0
6.5
6.0
5.5
8.0
7.5
7.0
6.5
6.0
5.5
V
CC
= 3.3 V
V
= 3.3 V
CC
V
CC
= 3.0 V
V
CC
= 3.0 V
V
CC
= 3.6 V
V
CC
= 3.6 V
–40
25
85
–40
25
85
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 39
Figure 40
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SN65LVDM320
SLLS462 – AUGUST 2001
APPLICATION INFORMATION
DRIVER
DRIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
3.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
V
T
= 3.3 V
= 25°C
CC
V
T
A
= 3.3 V
CC
A
= 25°C
3
2.5
2
1.5
1
.5
0
0
–2
–4
–6
–8
0
2
4
6
8
10
12
I
– Low-Level Output Current – mA
I
– High-Level Output Current – mA
OL
OH
Figure 41
Figure 42
RECEIVER
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
V
T
= 3.3 V
= 25°C
V
T
A
= 3.3 V
= 25°C
CC
A
CC
3
2
1
0
0
–20
– High-Level Output Current – mA
–40
–60
–80
0
10
20
30
40
50
60
70
80
I
OH
I
– Low-Level Output Current – mA
OL
Figure 43
Figure 44
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SN65LVDM320
SLLS462 – AUGUST 2001
APPLICATION INFORMATION
AVERAGE SUPPLY CURRENT
AVERAGE SUPPLY CURRENT
vs
vs
FREQUENCY
FREQUENCY
160
155
150
145
150
148
146
144
142
140
V
CC
= 3.3 V
V
CC
= 3.0 V
T
= 85°C
A
T
= 85°C
A
T
A
= 25°C
T
A
= 25°C
T
= –40°C
A
T
= –40°C
A
200
250
300
f – Frequency – MHz
350
400
200
250
300
350
400
f – Frequency – MHz
Figure 45
Figure 46
AVERAGE SUPPLY CURRENT
vs
FREQUENCY
170
V
CC
= 3.6 V
T
= 85°C
A
165
160
155
T
A
= 25°C
T
= –40°C
A
200
250
300
350
400
f – Frequency – MHz
Figure 47
29
www.ti.com
SN65LVDM320
SLLS462 – AUGUST 2001
MECHANICAL DATA
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–ā8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
30
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2005
PACKAGING INFORMATION
Orderable Device
SN65LVDM320DGG
SN65LVDM320DGGR
SN65LVDM320DGGRG4
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
64
64
64
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TSSOP
TSSOP
DGG
DGG
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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