SN65LVDS051 [TI]
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS; 高速差分线路驱动器和接收
| 型号： | SN65LVDS051 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS |
| 文件： | 总19页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
Meets or Exceeds the Requirements of
SN65LVDS179D (Marked as DL179 or LVD179)
SN65LVDS179DGK (Marked as S79)
(TOP VIEW)
ANSI TIA/EIA-644-1995 Standard
Signaling Rates up to 400 Mbit/s
Bus-Terminal ESD Exceeds 12 kV
Operates from a Single 3.3-V Supply
5
6
8
7
3
Y
Z
D
R
V
A
B
Z
Y
1
2
3
4
8
7
6
5
CC
R
A
B
2
Low-Voltage Differential Signaling With
Typical Output Voltages of 350 mV and a
100 Ω Load
D
GND
Propagation Delay Times
– Driver: 1.7 ns Typ
SN65LVDS180D (Marked as LVDS180)
(TOP VIEW)
– Receiver: 3.7 ns Typ
9
NC
R
V
V
A
B
Z
Y
Power Dissipation at 200 MHz
– Driver: 25 mW Typical
– Receiver: 60 mW Typical
1
2
3
4
5
6
7
14
13
12
11
10
9
5
CC
CC
Y
Z
D
10
4
3
RE
DE
RE
DE
LVTTL Input Levels are 5 V Tolerant
12
11
A
B
D
2
Driver is High Impedance When Disabled or
R
GND
GND
With V
< 1.5 V
CC
NC
8
Receiver has Open-Circuit Fail Safe
Surface-Mount Packaging
– D Package (SOIC)
– DGK Package (MSOP) (’LVDS79 Only)
14
13
SN65LVDS050D (Marked as LVDS050)
15
1Y
1Z
(TOP VIEW)
1D
12
9
1B
1A
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
DE
2D
10
11
2Y
2Z
description
1D
1Y
1Z
DE
1R
The
SN65LVDS179,
SN65LVDS180,
RE
2R
2
1
SN65LVDS050, and SN65LVDS051 are differen-
tial line drivers and receivers that use low-voltage
differential signaling (LVDS) to achieve signaling
rates as high as 400 Mbps. The TIA/EIA-644
standard compliant electrical interface provides a
minimum differential output voltage magnitude of
247 mV into a 100 Ω load and receipt of 100 mV
signals with up to 1 V of ground potential
difference between a transmitter and receiver.
3
1A
1B
1R
2A
11 2Z
10 2Y
4
5
RE
2R
6
7
2B
2A
2B
GND
9
2D
SN65LVDS051D (Marked as LVDS051)
14
13
(TOP VIEW)
15
1Y
1Z
1D
1B
1A
V
CC
1D
1Y
1
2
3
4
5
6
7
8
16
15
14
13
12
4
3
The intended application of this device and
signaling technique is for point-to-point baseband
data transmission over controlled impedance
media of approximately 100 Ω characteristic
impedance. The transmission media may be
printed-circuit board traces, backplanes, or
cables. (Note: The ultimate rate and distance of
data transfer is dependent upon the attenuation
characteristics of the media, the noise coupling to
the environment, and other application specific
characteristics).
1DE
1R
2
1
1A
1B
1R
1DE
2R
1Z
10
11
2DE
9
2Y
2Z
2D
2A
11 2Z
10 2Y
12
5
2B
2DE
2R
6
7
GND
9
2D
2A
2B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
description (continued)
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE
(D)
SMALL OUTLINE
(DGK)
SN65LVDS050D
SN65LVDS051D
SN65LVDS179D
SN65LVDS180D
—
—
–40°C to 85°C
SN65LVDS179DGK
—
NOTE:
The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics
of the media, the noise coupling to the environment, and other application specific characteristics.
The SN65LVDS179, SN65LVDS180, SN65LVDS050, and SN65LVDS051 are characterized for operation from
–40°C to 85°C.
Function Tables
SN65LVDS179 RECEIVER
INPUTS
= V – V
B
OUTPUT
V
R
H
?
ID
A
V
≥ 100 mV
ID
–100 MV < V < 100 mV
ID
V
ID
≤ –100 mV
L
Open
H
H = high level, L = low level, ? = indeterminate
SN65LVDS179 DRIVER
INPUT
OUTPUTS
D
L
Y
Z
H
L
L
H
L
H
Open
H
H = high level, L = low level
SN65LVDS180, SN65LVDS050, and
SN65LVDS051 RECEIVER
INPUTS
= V – V
OUTPUT
V
RE
L
R
H
?
ID
A
B
V
≥ 100 mV
ID
–100 MV < V < 100 mV
L
ID
V
ID
≤ –100 mV
Open
X
L
L
L
H
Z
H
H = high level, L = low level, Z = high impedance,
X = don’t care
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
SN65LVDS180, SN65LVDS050, and
SN65LVDS051 DRIVER
INPUTS
OUTPUTS
D
L
DE
H
Y
Z
H
L
L
H
L
H
H
Open
X
H
H
Z
L
Z
H = high level, L = low level, Z = high impedance,
X = don’t care
equivalent input and output schematic diagrams
V
CC
V
CC
V
CC
300 kΩ
50 Ω
5 Ω
50 Ω
10 kΩ
Y or Z
Output
D or RE
Input
DE
Input
7 V
7 V
7 V
300 kΩ
V
CC
V
CC
300 kΩ
300 kΩ
5 Ω
R Output
A Input
B Input
7 V
7 V
7 V
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
CC
Voltage range (D, R, DE, RE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Electrostatic discharge: Y, Z, A, B , and GND (see Note 2) . . . . . . . . . . . . . . . . . . CLass 3, A:12 kV, B:600 V
All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:7 kV, B:500 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see dissipation rating table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T = 85°C
A
POWER RATING
A
PACKAGE
†
POWER RATING
ABOVE T = 25°C
A
D8
D14 or D16
DGK
725 mW
950 mW
424 mW
5.8 mW/°C
7.8 mW/°C
3.4 mW/°C
377 mW
494 mW
220 mW
†
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
recommended operating conditions
MIN NOM
MAX
UNIT
Supply voltage, V
CC
3
2
3.3
3.6
V
V
V
V
High-level input voltage, V
IH
Low-level input voltage, V
IL
Magnitude of differential input voltage, V
0.8
0.6
0.1
ID
V
V
ID
ID
2.4
Common–mode input voltage, V (see Figure 6)
IC
V
2
2
V
–0.8
CC
85
Operating free–air temperature, T
–40
°C
A
device electrical characteristics over recommended operating conditions (unless otherwise
noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
12
12
7
UNIT
SN65LVDS179 No receiver load, Driver R = 100 Ω
9
9
5
mA
L
Driver and receiver enabled, No receiver load, Driver R = 100 Ω
L
Driver enabled, Receiver disabled, R = 100 Ω
L
SN65LVDS180
mA
Driver disabled, Receiver enabled, No load
Disabled
1.5
0.5
12
10
3
2
1
Supply
current
I
Drivers and receivers enabled, No receiver loads, Driver R = 100 Ω
20
16
6
CC
L
Drivers enabled, Receivers disabled, R = 100 Ω
L
SN65LVDS050
SN65LVDS051
mA
mA
Drivers disabled, Receivers enabled, No loads
Disabled
0.5
12
3
1
Drivers enabled, No receiver loads, Driver R = 100 Ω
20
6
L
Drivers disabled, No loads
†
All typical values are at 25°C and with a 3.3-V supply.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
driver electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
Differential output voltage magnitude
247
340
454
OD
R
= 100Ω,
L
mV
Change in differential output voltage magnitude between logic
states
See Figure 1 and Figure 2
∆ V
–50
1.125
–50
50
OD
V
Steady-state common-mode output voltage
1.2 1.375
50
V
OC(SS)
Change in steady-state common-mode output voltage between
logic states
∆V
mV
mV
See Figure 3
OC(SS)
V
Peak-to-peak common-mode output voltage
50
–0.5
2
150
–20
20
OC(PP)
DE
I
IH
High-level input current
D
V
V
= 5 V
µA
µA
mA
µA
IH
DE
–0.5
2
–10
10
I
IL
Low-level input current
D
= 0.8 V
IL
V
V
V
V
V
or V
OZ
= 0 V
3
10
OY
OD
OD
I
Short-circuit output current
OS
= 0 V
= 600 mV
3
10
±1
I
High-impedance output current
OZ
= 0 V or V
CC
±1
O
I
Power-off output current
Input capacitance
= 0 V, V = 3.6 V
±1
µA
O(OFF)
CC
O
C
3
pF
IN
receiver electrical characteristics over recommended operating conditions (unless otherwise
noted)
†
PARAMETER
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
High-level output voltage
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
100
ITH+
ITH–
OH
See Figure 5 and Table 1
mV
–100
2.4
I
I
= –8 mA
= 8 mA
V
V
OH
Low-level output voltage
0.4
OL
OL
V = 0
–2
–11
–3
–20
I
I
I
Input current (A or B inputs)
µA
V = 2.4 V
I
–1.2
I
I
I
I
Power-off input current (A or B inputs)
High-level input current (enables)
Low-level input current (enables)
High-impedance output current
V
V
V
V
= 0
±20
±10
±10
±10
µA
µA
µA
µA
I(OFF)
CC
= 5 V
IH
IH
IL
O
= 0.8 V
= 0 or 5 V
IL
OZ
C
Input capacitance
5
pF
I
†
All typical values are at 25°C and with a 3.3-V supply.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
driver switching characteristics over recommended operating conditions (unless otherwise
noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
2.7
2.7
1
UNIT
ns
t
t
t
t
t
t
t
t
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time
1.7
1.7
0.8
0.8
300
150
4.3
4.6
3.1
3.4
PLH
PHL
r
ns
R
C
= 100Ω,
= 10 pF,
L
L
ns
Differential output signal fall time
1
ns
f
See Figure 6
‡
Pulse skew (|t
– t
|)
ps
sk(p)
sk(o)
PZH
PZL
PHZ
pLZ
pHL pLH
§
Channel-to-channel output skew
ps
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
10
10
10
10
ns
ns
See Figure 7
ns
ns
†
All typical values are at 25°C and with a 3.3-V.
‡
§
¶
t
t
t
is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together.
is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices
sk(p)
sk(o)
sk(pp)
operate with the same supply voltages, same temperature, and have identical packages and test circuits.
receiver switching characteristics over recommended operating conditions (unless otherwise
noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
4.5
UNIT
ns
t
t
t
t
t
t
t
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
3.7
3.7
0.3
0.7
0.9
2.5
2.5
7
PLH
PHL
sk(p)
r
4.5
ns
‡
Pulse skew (|t
– t
pHL pLH
|)
C
= 10 pF, See Figure 6
ns
L
Output signal rise time
Output signal fall time
1.5
1.5
ns
ns
f
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-low-impedance output
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, low-impedance-to-high-level output
ns
PZH
PZL
PHZ
PLZ
ns
See Figure 7
ns
4
ns
†
All typical values are at 25°C and with a 3.3-V.
‡
§
¶
t
t
t
is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together.
is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices
sk(p)
sk(o)
sk(pp)
operate with the same supply voltages, same temperature, and have identical packages and test circuits.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
driver
I
OY
Driver Enable
Y
Z
I
I
A
V
OD
V
V
OY
OZ
I
OZ
V
OY
2
V
I
V
OC
V
OZ
Figure 1. Driver Voltage and Current Definitions
Driver Enable
Y
Z
100 Ω
±1%
V
OD
Input
C
= 10 pF
L
(2 Places)
2 V
Input
1.4 V
0.8 V
t
PHL
t
PLH
100%
80%
V
OD(H)
Output
0 V
V
OD(L)
20%
0%
t
f
t
r
NOTE A: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
r
f
pulse width = 10 ± 0.2 ns . C includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
L
Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
Driver Enable
Input
49.9 Ω, ±1% (2 Places)
3 V
0 V
Y
Z
V
OC
V
OC(PP)
C
= 10 pF
L
V
OC(SS)
(2 Places)
V
OC
NOTE A: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
r
f
pulsewidth=10±0.2ns.C includesinstrumentationandfixturecapacitancewithin0,06mmoftheD.U.T.ThemeasurementofV
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
L
OC(PP)
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
49.9 Ω, ±1% (2 Places)
Y
0.8 V or 2 V
Z
1.2 V
DE
C
= 10 pF
L
V
OY
V
OZ
(2 Places)
2 V
1.4 V
0.8 V
DE
OZ
~1.4 V
1.25 V
1.2 V
V
V
or V
or V
D at 2 V and input to DE
D at 0.8 V and input to DE
OY
t
PZH
t
t
PHZ
1.2 V
1.15 V
~1 V
OZ
OY
t
PZL
PLZ
NOTE A: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
r
f
pulse width = 500 ± 10 ns . C includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
L
Figure 4. Enable and Disable Time Circuit and Definitions
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
receiver
A
V
V
R
IA
IB
V
ID
2
V
IA
B
V
O
V
IC
V
IB
Figure 5. Receiver Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
RESULTING DIFFERENTIAL
INPUT VOLTAGE
(mV)
RESULTING COMMON-
MODE INPUT VOLTAGE
(V)
APPLIED VOLTAGES
(V)
V
IA
V
IB
V
ID
V
IC
1.25
1.15
2.4
2.3
0.1
0
1.15
1.25
2.3
2.4
0
100
–100
100
1.2
1.2
2.35
2.35
0.05
0.05
1.2
–100
100
0.1
0.9
1.5
1.8
2.4
0
–100
600
1.5
0.9
2.4
1.8
0.6
0
–600
600
1.2
2.1
–600
600
2.1
0.3
0.6
–600
0.3
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
receiver (continued)
V
ID
V
IA
C
L
V
O
10 pF
V
IB
V
V
1.4 V
1 V
IA
IB
0.4 V
0 V
V
ID
–0.4 V
t
t
PHL
PLH
V
V
O
OH
2.4 V
0.4 V
1.4 V
V
OL
t
f
t
r
NOTE A: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
r
f
pulse width = 10 ± 0.2 ns. C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
L
Figure 6. Timing Test Circuit and Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
receiver (continued)
B
1.2 V
500 Ω
A
C
10 pF
+
–
L
V
O
V
TEST
Inputs
RE
NOTE A: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
r
f
pulse width = 500 ± 10 ns. C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
L
2.5 V
V
TEST
A
1 V
2 V
RE
1.4 V
0.8 V
t
PZL
R
t
t
PZL
PLZ
2.5 V
1.4 V
V
OL
+0.5 V
V
OL
0 V
V
TEST
A
1.4 V
2 V
RE
1.4 V
0.8 V
t
PZH
R
t
t
PZH
PHZ
V
OH
V
–0.5 V
OH
1.4 V
0 V
Figure 7. Enable/Disable Time Test Circuit and Waveforms
11
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SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
COMMON-MODE INPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
2.5
V
CC
> 3.15 V
V
CC
= 3 V
2
1.5
1
0.5
0
MIN
0
0.1
0.2
0.3
0.4
0.5
0.6
|V |– Differential Input Voltage – V
ID
Figure 8
DRIVER
DRIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
4
3
3.5
3
V
T
A
= 3.3 V
= 25°C
CC
V
T
A
= 3.3 V
= 25°C
CC
2.5
2
2
1
1.5
1
0.5
0
0
0
2
4
6
–1
–4
–3
–2
0
I
– Low-Level Output Current – mA
I
– High-Level Output Current – mA
OL
OH
Figure 9
Figure 10
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
RECEIVER
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
5
4
3
2
1
4
V
T
A
= 3.3 V
= 25°C
CC
V
T
A
= 3.3 V
= 25°C
CC
3
2
1
0
0
0
10
60
–80
–60
– High-Level Output Current – mA
0
20
30
40
50
–40
–20
I
– Low-Level Output Current – mA
I
OH
OL
Figure 11
Figure 12
DRIVER
DRIVER
HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME
LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
2.5
2.5
2
2
V
= 3.3 V
V
= 3.3 V
CC
CC
V
= 3 V
V
= 3 V
CC
CC
V
= 3.6 V
30
V
= 3.6 V
30
CC
CC
1.5
–50
1.5
–50
–30
–10
10
50
90
–30
–10
10
50
90
70
70
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 13
Figure 14
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
RECEIVER
RECEIVER
HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME
LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME
vs
vs
FREE-AIR TEMPERATURE
FREE–AIR TEMPERATURE
4.5
4.5
V
CC
= 3 V
V
CC
= 3.3 V
4
4
V
CC
= 3.3 V
V
CC
= 3 V
3.5
3.5
V
= 3.6 V
CC
V
= 3.6 V
CC
3
3
2.5
–50
2.5
–50
–30
–10
10
50
90
–30
–10
10
50
90
30
70
30
70
T
A
– Free–Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 15
Figure 16
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
APPLICATION INFORMATION
The devices are generally used as building blocks for high-speed point-to-point data transmission. Ground
differences are less than 1 V with a low common–mode output and balanced interface for very low noise emissions.
Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/Receivers maintain ECL speeds without the
power and dual supply requirements.
1000
30% Jitter
100
5% Jitter
10
1
24 AWG UTP 96 Ω (PVC Dielectric)
0.1
100k
1M
10M
100M
Data Rate – Hz
Figure 17. Data Transmission Distance Versus Rate
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
APPLICATION INFORMATION
fail safe
One of the most common problems with differential signaling applications is how the system responds when
no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in
that its output logic state can be indeterminate when the differential input voltage is between –100 mV and
100 mV and within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how
it handles the open-input circuit situation, however.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
will pull each line of the signal pair to near V
through 300-kΩ resistors as shown in Figure 11. The fail-safe
CC
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level regardless of the differential input voltage.
V
CC
300 kΩ
300 kΩ
A
R
t
100 Ω Typ
Y
B
V
IT
≈ 2.3 V
Figure 18. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100-mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as
long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that
could defeat the pullup currents from the receiver and the fail-safe feature.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.010 (0,25)
M
0.014 (0,35)
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–8°
0.044 (1,12)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
MECHANICAL DATA
DGK (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,25
M
0,65
8
0,25
5
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
0°–6°
1
4
0,69
0,41
3,05
2,95
Seating Plane
0,10
1,07 MAX
0,15 MIN
4073329/A 02/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-187
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright 2000, Texas Instruments Incorporated
相关型号：
SN65LVDS051DRQ1
Automotive Catalog High-Speed Differential Line Drivers and Receivers 16-SOIC -40 to 85
TI
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