SN65LVDS22D [TI]
DUAL MULTIPLEXED LVDS REPEATERS; 双复用LVDS转发
| 型号： | SN65LVDS22D |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL MULTIPLEXED LVDS REPEATERS |
| 文件： | 总13页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
D PACKAGE
(TOP VIEW)
Meets or Exceeds the Requirements of
ANSI TIA/EIA–644–1995 Standard
Designed for Signaling Rates Up to
400 Mbit/s
1B
1A
V
V
1
2
3
4
5
6
7
8
16
15
14
13
12
CC
CC
ESD Protection Exceeds 12 kV on Bus Pins
Operates from a Single 3.3-V Supply
S0
1Y
1DE
S1
1Z
Low-Voltage Differential Signaling with
Output Voltages of 350 mVinto:
– 100-Ω Load (SN65LVDS22)
– 50-Ω Load (SN65LVDM22)
2DE
2A
11 2Z
10 2Y
2B
GND
9
GND
Propagation Delay Time; 4 ns Typ
Power Dissipation at 400 Mbit/s of 150 mW
Bus Pins are High Impedance When
logic diagram (positive logic)
Disabled or With V
Less Than 1.5 V
CC
LVTTL Levels are 5 V Tolerant
Open-Circuit Fail Safe Receiver
2
+
_
1A
1B
14
13
0
1
1
1Y
1Z
description
The SN65LVDS22 and SN65LVDM22 are differ-
ential line drivers and receivers that use
low-voltage differential signaling (LVDS) to
achieve signaling rates as high as 400 Mbps. The
receiver outputs can be switched to either or both
drivers through the multiplexer control signals S0
and S1. This allows the flexibility to perform
splitter or signal routing functions with a single
device.
4
1DE
2DE
S0
12
3
5
S1
10
11
0
1
2Y
2Z
6
7
+
_
2A
2B
The TIA/EIA-644 standard compliant electrical
interface provides a minimum differential output
voltage magnitude of 247 mV into a 100-Ω load
and receipt of 100 mV signals with up to 1 V of
ground potential difference between a transmitter
and receiver. The SN65LVDM22 doubles the
output drive current to achieve LVDS levels with a
50 Ω load.
MUX Truth Table
OUTPUT
INPUT
FUNCTION
S1
S0
1Y/1Z
1A/1B
2A/2B
1A/1B
2A/2B
2Y/2Z
1A/1B
2A/2B
2A/2B
1A/1B
0
0
1
1
0
1
0
1
Splitter
Splitter
Router
Router
The intended application of these devices and
signaling technique is for both point–to–point
baseband (single termination) and multipoint
(double termination) data transmissions over
controlled impedance media. The transmission
media may be printed circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data
transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment,
and other application specific characteristics).
The SN65LVDS22 and SN65LVDM22 are characterized for operation from –40 C to 85 C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
equivalent input and output schematic diagrams
V
CC
V
CC
300 kΩ
50 Ω
S0, S1
Input
50 Ω
1DE, 2DE
Input
7 V
300 kΩ
7 V
V
CC
V
CC
300 kΩ
300 kΩ
5 Ω
Y or Z
10 kΩ
Output
A Input
B Input
7 V
7 V
7 V
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
CC
Voltage range (DE, S0, S1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Input voltage range, V (A or B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to Vcc+0.5 V
I
Electrostatic discharge: A, B, Y, Z and GND (see Note 2) . . . . . . . . . . . . . . . . . . . . Class 3, A:12 kV, B:600 V
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:5 kV, B:500 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
‡
T
≤ 25°C
DERATING FACTOR
T = 85°C
A
POWER RATING
A
PACKAGE
POWER RATING
ABOVE T = 25°C
A
D16
950 mW
7.6 mW/°C
494 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with
no air flow.
recommended operating conditions
MIN NOM
MAX
UNIT
Supply voltage, V
3
2
3.3
3.6
V
V
V
V
CC
High-level input voltage, V
S0, S1, 1DE, 2DE
S0, S1, 1DE, 2DE
IH
Low-level input voltage, V
IL
Magnitude of differential input voltage, V
0.8
0.6
0.1
ID
ID
V
V
ID
V
2.4 –
Common-mode input voltage, V (see Figure 1)
IC
2
2
V
CC
–0.8
85
V
Operating free-air temperature, T
–40
°C
A
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
COMMON-MODE INPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
2.5
MAX at V
> 3.15 V
CC
MAX at V
= 3 V
CC
2
1.5
1
0.5
0
Min
0
0.1
0.2
0.3
0.4
0.5
0.6
V
ID
– Differential Input Voltage – V
Figure 1. Common-Mode Input Voltage vs Differential Input Voltage
receiver electrical characteristics over recommended operating conditions (unless otherwise
noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
mV
V
V
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
100
ITH+
–100
–2
mV
ITH–
V = 0 V
I
–20
20
I
I
Input current (A or B inputs)
µA
µA
V = 2.4 V
I
–1.2
I
Power-off input current (A or B inputs)
V
CC
= 0 V
I(OFF)
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
receiver/driver electrical characteristics over recommended operating conditions (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
OD
Differential output voltage magnitude
247
340
454
mV
See Figure 2
See Figure 3
Change in differential output voltage magnitude
between logic states
∆V
–50
50
1.375
50
mV
V
OD
R
R
= 100 Ω (’LVDS22),
L
L
V
Steady-state common-mode output voltage
1.125
–50
OC(SS)
= 50 Ω(’LVDM22)
Change in steady-state common-mode output
voltage between logic states
∆V
3
mV
mV
OC(SS)
V
Peak-to-peak common-mode output voltage
150
12
OC(PP)
No Load
8
13
21
3
R
R
= 100 Ω (‘LVDS22)
= 50 Ω (‘LVDM22)
20
L
L
I
Supply current
mA
CC
27
Disabled
6
DE
High-level input current
S0, S1
–10
20
I
I
V
V
= 5
µA
µA
IH
IH
DE
Low-level input current
S0, S1
–10
10
= 0.8 V
IL
IL
–10
–10
–10
–10
±1
V
V
or V
= 0 V,
= 0 V,
(’LVDS22)
(’LVDM22)
OY
OD
OZ
= 0 V,
I
Short-circuit output current
mA
OS
V
OY
V
OD
or V
OZ
= 0 V,
V
V
V
= 600 mV
0.015
0.015
0.015
3
OD
I
I
High-impedance output current
µA
OZ
= 0 V or V
±1
O
CC
Power-off output current
Input capacitance
= 0 V,
V = 3.6 V
O
±1
µA
O(OFF)
CC
C
pF
IN
†
All typical values are at 25°C and with a 3.3 V supply.
differential receiver to driver switching characteristics over recommended operating conditions
(unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Differential propagation delay, low-to-high
Differential propagation delay, high-to-low
4
4
6
6
PLH
PHL
sk(p)
r
ns
Pulse skew (|t
– t
PHL PLH
|)
0.5
1
ns
C
= 10 pF,
L
Transition, low-to-high
Transition, low-to-high
Transition, high-to-low
Transition, high-to-low
SN65LVDS22
SN65LVDM22
SN65LVDS22
SN65LVDM22
1.5
1.3
1.5
1.3
10
ns
See Figure 4
0.8
1
ns
r
ns
f
0.8
4
ns
f
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
ns
PHZ
PLZ
PZH
PZL
5
10
ns
See Figure 5
5
10
ns
6
10
ns
_R1_Dx
PHL
0.2
0.2
0.2
0.2
_
_
PLH R1 Dx
‡
Channel-to-channel skew, receiver to driver
ns
_
_
PHL R2 Dx
_
_
PLH R2 Dx
†
‡
All typical values are at 25°C and with a 3.3 V supply.
These parametric values are measured over supply voltage and temperature ranges recommended for the device.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
PARAMETER MEASUREMENT INFORMATION
DE
Y
Z
A
B
Pulse
Generator
V
R
(see Note B)
L
OD
Input
(see Note A)
C
= 10 pF
(2 Places)
(see Note C)
L
V
V
1.4 V
1 V
I(B)
100%
80%
V
OD
I(A)
0
20%
0%
t
f
t
r
NOTES: A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
r
f
pulse width = 10 ± 0.2 ns.
= 100 Ω or 50 Ω ±1%
C. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
NOTES: B.
R
L
Figure 2. Test Circuit and Voltage Definitions for the Differential Output Signal
DE
R
(see Note B)
(2 Places)
L
V
V
1.4 V
1 V
I(B)
Y
Z
A
B
Pulse
Generator
I(A)
V
OC(PP)
(see Note D)
Input
(see Note A)
V
OC
V
OC(SS)
C
= 10 pF
L
(2 Places)
(see Note C)
V
CC
NOTES: A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
r
f
pulse width = 10 ± 0.2 ns.
NOTES: B.
C.
R
C
= 100 Ω or 50 Ω ±1%
includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
L
L
D. The measurement of V
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
OC(PP)
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
PARAMETER MEASUREMENT INFORMATION
DE
Y
A
B
Pulse
Generator
R
D
R
(see Note A)
L
Z
10 pF
10 pF
V
V
1.4 V
1 V
IB
0-V Differential
1.2-V CM
t
IA
t
PLH
PHL
V
1.4 V
1 V
OZ
0-V Differential
1.2-V CM
V
OY
80%
0-V Differential
20%
V
OY
– V
OZ
t
f
t
r
NOTES: A.
R = 100 Ω or 50 Ω ±1%
L
B. All input pulses are supplied by a generator having the following characteristics: pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns.
Figure 4. Differential Receiver to Driver Propagation Delay and Driver Transition Time Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
PARAMETER MEASUREMENT INFORMATION
DE
R /2
L
(see Note A)
A
B
1 V or 1.4 V
1.2 V
R
D
1.2 V
R /2
L
(see Note A)
2 V
DE
OZ
1.4 V
0.8 V
t
t
t
t
PZH
PHZ
≈1.4 V
V
OY
or V
1.25 V
1.2 V
PZL
PLZ
1.2 V
1.15 V
V
OY
or V
OZ
≈1 V
NOTES: A.
R = 100 Ω or 50 Ω ±1%
L
B. All input pulses are supplied by a generator having the following characteristics: pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns.
Figure 5. Enable and Disable Timing Circuit
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
TYPICAL CHARACTERISTICS
SN65LVDS22
HIGH-LEVEL OUTPUT VOLTAGE
vs
SN65LVDS22
LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
3.5
3
4
3
2
1
0
V
T
A
= 3.3 V
CC
= 25°C
V
T
= 3.3 V
= 25°C
CC
A
2.5
2
1.5
1
.5
0
–4
–3
–2
–1
0
0
2
4
6
I
– High-Level Output Current – mA
I
– Low-Level Output Current – mA
OH
OL
Figure 6
Figure 7
SN65LVDM22
SN65LVDM22
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
3.5
4
3
2
1
0
V
T
A
= 3.3 V
CC
= 25°C
V
T
A
= 3.3 V
= 25°C
CC
3
2.5
2
1.5
1
.5
0
–8
–6
–4
–2
0
0
2
4
6
8
10
12
I
– High-Level Output Current – mA
I
– Low-Level Output Current – mA
OH
OL
Figure 8
Figure 9
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
APPLICATION INFORMATION
The devices are generally used as building blocks for high-speed point-to-point data transmission. Ground
differences are less than 1 V with a low common–mode output and balanced interface for very low noise emissions.
Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/Receivers maintain ECL speeds without the
power and dual supply requirements.
1000
30% Jitter
100
5% Jitter
10
1
24 AWG UTP 96 Ω (PVC Dielectric)
0.1
100k
1M
10M
100M
Data Rate – Hz
Figure 10. Data Transmission Distance Versus Rate
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
APPLICATION INFORMATION
fail safe
One of the most common problems with differential signaling applications is how the system responds when
no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in
that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100
mV and within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how it
handles the open-input circuit situation, however.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
will pull each line of the signal pair to near V
through 300-kΩ resistors as shown in Figure 11. The fail-safe
CC
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level regardless of the differential input voltage.
V
CC
300 kΩ
300 kΩ
A
Rt = 100 Ω (Typ)
Y
B
V
IT
≈ 2.3 V
Figure 11. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100 mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as
long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that
could defeat the pull-up currents from the receiver and the fail-safe feature.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS22, SN65LVDM22
DUAL MULTIPLEXED LVDS REPEATERS
SLLS315– DECEMBER 1998
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–8°
0.044 (1,12)
A
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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BE FULLY AT THE CUSTOMER’S RISK.
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safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 1999, Texas Instruments Incorporated
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