SN65LVDS32PWG4 [TI]
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS; 高速差动线路接收器
| 型号： | SN65LVDS32PWG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-SPEED DIFFERENTIAL LINE RECEIVERS |
| 文件： | 总31页 (文件大小：1018K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN55LVDS32, SN65LVDS32
SN65LVDS3486, SN65LVDS9637
www.ti.com
SLLS262N–JULY 1997–REVISED MARCH 2004
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
FEATURES
SN55LVDS32 . . . J OR W
SN65LVDS32 . . . D OR PW
(Marked as LVDS32 or 65LVDS32)
(TOP VIEW)
•
Meet or Exceed the Requirements of ANSI
TIA/EIA-644 Standard
•
•
Operate With a Single 3.3-V Supply
1B
1A
1Y
VCC
4B
4A
4Y
G
1
2
3
4
5
6
7
8
16
15
14
13
12
Designed for Signaling Rate of up to 400
Mbps
•
•
•
Differential Input Thresholds ±100 mV Max
Typical Propagation Delay Time of 2.1 ns
G
2Y
2A
11 3Y
Power Dissipation 60 mW Typical Per
Receiver at 200 MHz
10
9
2B
GND
3A
3B
•
•
•
Bus-Terminal ESD Protection Exceeds 8 kV
Low-Voltage TTL (LVTTL) Logic Output Levels
SN55LVDS32FK
(TOP VIEW)
Pin Compatible With AM26LS32, MC3486, and
µA9637
•
Open-Circuit Fail-Safe
3
4
2
1
20 19
1Y
G
4A
4Y
NC
G
18
17
16
15
14
DESCRIPTION
5
6
7
The SN55LVDS32, SN65LVDS32, SN65LVDS3486,
and SN65LVDS9637 are differential line receivers
that implement the electrical characteristics of
low-voltage differential signaling (LVDS). This
signaling technique lowers the output voltage levels
of 5-V differential standard levels (such as
EIA/TIA-422B) to reduce the power, increase the
switching speeds, and allow operation with a 3.3-V
supply rail. Any of the four differential receivers
provides a valid logical output state with a ±100-mV
differential
common-mode
common-mode voltage range allows 1 V of ground
potential difference between two LVDS nodes.
NC
2Y
2A
3Y
8
9
10 11 12 13
SN65LVDS3486D (Marked as LVDS3486)
(TOP VIEW)
1B
1A
1Y
VCC
4B
4A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
input
voltage
voltage
within
range.
the
The
input
input
1,2EN
2Y
4Y
3,4EN
3Y
The intended application of these devices and
signaling technique is both point-to-point and
multidrop (one driver and multiple receivers) data
transmission over controlled impedance media of
approximately 100 Ω. The transmission media may
be printed-circuit board traces, backplanes, or cables.
The ultimate rate and distance ofdata transfer
depends on the attenuation characteristics of the
media and the noise coupling to the environment.
2A
2B
GND
10 3A
3B
9
SN65LVDS9637D (Marked as DK637 or LVDS37)
SN65LVDS9637DGN (Marked as L37)
SN65LVDS9637DGK (Marked as AXF)
(TOP VIEW)
VCC
1Y
2Y
1A
1B
2A
2B
1
2
3
4
8
7
6
5
The
SN65LVDS32,
SN65LVDS3486,
and
SN65LVDS9637 are characterized for operation from
–40°C to 85°C. The SN55LVDS32 is characterized
for operation from –55°C to 125°C.
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1997–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN55LVDS32, SN65LVDS32
SN65LVDS3486, SN65LVDS9637
www.ti.com
SLLS262N–JULY 1997–REVISED MARCH 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
CHIP CARRIER
(FK)
CERAMIC DIP
(J)
FLAT PACK
(W)
MSOP
(D)
(PW)
SN65LVDS32D
SN65LVDS3486D
SN65LVDS9637D
—
SN65LVDS32PW
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–40°C to 85°C
SN65LVDS9637DGN
SN65LVDS9637DGK
–55°C to
125°C
SNJ55LVDS32W
SN55LVDS32W
—
—
—
SNJ55LVDS32FK SNJ55LVDS32J
’LVDS32 logic diagram
(positive logic)
SN65LVDS3486D logic diagram SN65LVDS9637D logic diagram
(positive logic)
(positive logic)
2
8
4
3
1A
1B
2
1A
G
1Y
1Y
2Y
1
4
7
12
G
1B
6
5
2
1,2EN
3
3
1A
2A
2B
1Y
6
7
1
5
2A
2B
1B
2Y
3Y
6
5
2A
2B
2Y
3Y
4Y
7
10
9
3A
3B
11
10
9
3A
3B
11
13
12
3,4EN
14
15
4A
4B
14
15
13
4A
4B
4Y
FUNCTION TABLES
SN55LVDS32, SN65LVDS32(1)
SN65LVDS3486(1)
ENABLES
DIFFERENTIAL INPUT
A, B
OUTPUT
Y
DIFFERENTIAL INPUT
ENABLE
EN
OUTPUT
Y
A, B
ID ≥ 100 mV
–100 mV < VID < 100 mV
G
G
H
X
X
L
H
H
VID ≥ 100 mV
V
H
H
H
?
H
X
X
L
?
?
–100 mV < VID < 100 mV
H
X
X
L
L
L
V
ID ≤ –100 mV
V
ID ≤ –100 mV
H
L
L
Z
H
X
L
H
Z
X
H
X
X
L
H
H
Open
Open
H
(1) H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
2
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SN55LVDS32, SN65LVDS32
SN65LVDS3486, SN65LVDS9637
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SLLS262N–JULY 1997–REVISED MARCH 2004
logic symbols†
SN55LVDS32, SN65LVDS32
SN65LVDS3486
4
4
1, 2EN
EN
≥ 1
G
G
EN
2
1
6
7
12
1A
1B
2A
2B
3
5
1Y
2Y
2
1
1A
1B
3
5
1Y
2Y
3Y
12
6
7
3, 4EN
EN
2A
2B
3A
3B
10
9
3A
3B
4A
4B
11
13
10
9
11
13
3Y
4Y
14
15
14
15
4A
4B
4Y
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Function Table
SN65LVDS9637
DIFFERENTIAL INPUT
A, B
OUTPUT
Y
V
ID ≥ 100 mV
H
?
–100 mV < VID < 100 mV
VID ≤ –100 mV
L
Open
H
H = high level, L = low level, ? = indeterminate
logic symbol†
SN65LVDS9637
8
7
6
5
1A
1B
2A
2B
2
3
1Y
2Y
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication617-12.
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SN55LVDS32, SN65LVDS32
SN65LVDS3486, SN65LVDS9637
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SLLS262N–JULY 1997–REVISED MARCH 2004
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
EQUIVALENT OF EACH A OR B INPUT
EQUIVALENT OF G, G, 1,2EN OR
3,4EN INPUTS
TYPICAL OF ALL OUTPUTS
V
CC
V
CC
V
CC
300 kΩ
300 kΩ
50 Ω
5 Ω
Input
Y Output
7 V
7 V
A Input
B Input
7 V
7 V
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
–0.5 V to 4 V
VCC Supply voltage range(2)
Enables and output
–0.5 V to VCC + 0.5 V
–0.5 V to 4 V
VI
Input voltage range
A or B
Continuous total power dissipation
See Dissipation Rating Table
260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Storage temperature range
Tstg
–65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages, except differential I/O bus voltages, are with respect to the network ground terminal.
DISSIPATION RATING TABLE
T
A ≤ 25°C
DERATING FACTOR(1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
PACKAGE
POWER RATING
D (8)
D (16)
DGK
DGN(2)
FK
725 mW
5.8 mW/°C
7.6 mW/°C
3.4 mW/°C
17.1 mW/°C
11.0 mW/°C
11.0 mW/°C
6.2 mW/°C
8.0 mW/°C
464 mW
608 mW
272 mW
1.37 W
377 mW
494 mW
221 mW
1.11 W
—
—
950 mW
425 mW
—
2.14 W
—
1375 mW
1375 mW
774 mW
880 mW
880 mW
496 mW
640 mW
715 mW
715 mW
402 mW
520 mW
275 mW
275 mW
—
J
PW (16)
W
1000 mW
200 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.
(2) The PowerPAD™ must be soldered to a thermal land on the printed-circuit board. See the application note PowerPAD Thermally
Enhanced Package (SLMA002)
4
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SN55LVDS32, SN65LVDS32
SN65LVDS3486, SN65LVDS9637
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SLLS262N–JULY 1997–REVISED MARCH 2004
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
VCC
VIH
VIL
Supply voltage
3
2
3.3
3.6
V
V
V
V
High-level input voltage
Low-level input voltage
G, G, 1,2EN, or 3,4EN
G, G, 1,2EN, or 3,4EN
0.8
0.6
|VID
|
Magnitude of differential input voltage
0.1
|V
|
|V
|
V
ID
ID
2.4 *
VIC
Common-mode input voltage (see Figure 1)
2
2
VCC– 0.8
85
SN65 prefix
SN55 prefix
–40
–55
Operating free-air
temperature
TA
°C
125
COMMON-MODE INPUT VOLTAGE RANGE
vs
DIFFERENTIAL INPUT VOLTAGE
2.5
2
Max at V > 3.15 V
CC
Max at V = 3 V
CC
1.5
1
0.5
0
Min
0.3
0
0.1
0.2
0.4
0.5
0.6
V
ID
- Differential Input Voltage - V
Figure 1. VIC Versus VID and VCC
5
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SN55LVDS32, SN65LVDS32
SN65LVDS3486, SN65LVDS9637
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SLLS262N–JULY 1997–REVISED MARCH 2004
SN55LVDS32 ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX UNIT
(2)
(2)
VITH+ Positive-going differential input voltage threshold
VITH– Negative-going differential input voltage threshold(3)
VOH High-level output voltage
See Figure 2, Table 1, and
See Figure 2, Table 1, and
IOH = –8 mA
100
mV
mV
V
–100
2.4
VOL Low-level output voltage
IOL = 8 mA
0.4
18
V
Enabled,
Disabled
VI = 0
No load
10
ICC
Supply current
mA
0.25
0.5
–2
–10 –20
–3
II
Input current (A or B inputs)
µA
µA
VI = 2.4 V
–1.2
II(OFF
Power-off input current (A or B inputs)
VCC = 0,
VI = 2.4 V
6
20
)
IIH
High-level input current (EN, G, or G inputs)
Low-level input current (EN, G, or G inputs)
High-impedance output current
VIH = 2 V
10
10
µA
µA
µA
IIL
VIL = 0.8 V
VO = 0 or VCC
IOZ
±12
(1) All typical values are at TA = 25°C and with VCC = 3.3 V.
(2) |VITH| = 200 mV for operation at –55°C
(3) The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the
negative-going differential input voltage threshold only.
SN55LVDS32 SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
tPLH
tPHL
tsk(o)
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Channel-to-channel output skew(1)
1.3
1.4
2.3
2.2
0.1
0.6
0.7
6.5
5.5
8
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.1
CL = 10 pF, See Figure 3
Output signal rise time, 20% to 80%
tf
Output signal fall time, 80% to 20%
tPHZ
tPLZ
tPZH
tPZL
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
12
12
14
12
See Figure 4
3
(1) tsk(o) is the maximum delay time difference between drivers on the same device.
6
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SN65LVDS3486, SN65LVDS9637
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SLLS262N–JULY 1997–REVISED MARCH 2004
SN65LVDSxxxx ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
SN65LVDS32
SN65LVDS3486
SN65LVDS9637
PARAMETER
TEST CONDITIONS
UNIT
MIN TYP(1) MAX
VIT+
VIT-
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold(2)
See Figure 2 and Table 1
See Figure 2 and Table 1
IOH = –8 mA
IOH = –4 mA
IOL = 8 mA
100
mV
mV
–100
2.4
VOH
VOL
High-level output voltage
Low-level output voltage
V
V
2.8
0.4
Enabled, No load
Disabled
10
0.25
5.5
18
0.5
10
SN65LVDS32, SN65LVDS3486
SN65LVDS9637
ICC
Supply current
mA
No load
VI = 0
–2
–10 –20
–3
II
Input current (A or B inputs)
µA
VI = 2.4 V
–1.2
II(OFF)
IIH
Power-off input current (A or B inputs)
High-level input current (EN, G, or G inputs)
Low-level input current (EN, G, or G inputs)
High-impedance output current
VCC = 0, VI = 3.6 V
VIH = 2 V
6
20
10
µA
µA
µA
µA
IIL
VIL = 0.8 V
10
IOZ
VO = 0 or VCC
±10
(1) All typical values are at TA = 25°C and with VCC = 3.3 V.
(2) The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the
negative-going differential input voltage threshold only.
SN65LVDSxxxx SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
SN65LVDS32
SN65LVDS3486
SN65LVDS9637
PARAMETER
TEST CONDITIONS
UNIT
MIN
1.5
TYP
2.1
2.1
0
MAX
3
tPLH
tPHL
tsk(p)
tsk(o)
tsk(pp)
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Pulse skew (|tPHL - tPLH|)
Channel-to-channel output skew(1)
Part-to-part skew(2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.5
3
0.4
0.3
1
CL = 10 pF, See Figure 3
0.1
Output signal rise time, 20% to 80%
0.6
0.7
6.5
5.5
8
tf
Output signal fall time, 80% to 20%
tPHZ
tPLZ
tPZH
tPZL
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
12
12
12
12
See Figure 4
3
(1) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, same temperature, and have identical packages and test circuits.
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SN65LVDS3486, SN65LVDS9637
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SLLS262N–JULY 1997–REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
A
Y
V
ID
B
V
IA
(V + V )/2
V
O
IA
IB
V
IC
V
IB
Figure 2. Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
Resulting Differential
Input Voltage
Resulting Common-Mode
Input Voltage
Applied Voltages
VIA(V)
VIB(V)
1.15
1.25
2.3
2.4
0
VID(mV)
100
VIC(V)
1.2
1.25
1.15
2.4
2.3
0.1
0
–100
100
1.2
2.35
2.35
0.05
0.05
1.2
–100
100
0.1
0.9
1.5
1.8
2.4
0
–100
600
1.5
0.9
2.4
1.8
0.6
0
–600
600
1.2
2.1
–600
600
2.1
0.3
0.6
–600
0.3
8
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SN65LVDS3486, SN65LVDS9637
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SLLS262N–JULY 1997–REVISED MARCH 2004
V
ID
V
IA
C
L
= 10 pF
V
O
V
IB
V
V
1.4 V
1 V
IA
IB
0.4 V
0
V
ID
-0.4 V
t
t
PLH
PHL
V
OH
80%
20%
80%
20%
1.4 V
V
O
V
OL
t
f
t
r
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition
rate(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns.
B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
Figure 3. Timing Test Circuit and Waveforms
9
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SN65LVDS3486, SN65LVDS9637
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SLLS262N–JULY 1997–REVISED MARCH 2004
B
A
1.2 V
500 Ω
10 pF
G
G
±
(see Note B)
V
O
Inputs
(see Note A)
V
TEST
1,2EN or 3,4EN
2.5 V
V
TEST
A
1 V
2 V
1.4 V
0.8 V
G, 1,2EN,
or 3,4EN
2 V
1.4 V
0.8 V
G
t
t
PLZ
PLZ
t
t
PZL
PZL
2.5 V
1.4 V
OL
OL
Y
V
V
+ 0.5 V
V
TEST
0
1.4 V
A
2 V
1.4 V
0.8 V
G, 1,2EN,
or 3,4EN
2 V
1.4 V
0.8 V
t
PHZ
G
t
PHZ
t
t
PZH
PZH
V
V
OH
OH
- 0.5 V
Y
1.4 V
0
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition
rate(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns.
B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
Figure 4. Enable- and Disable-Time Test Circuit and Waveforms
10
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SLLS262N–JULY 1997–REVISED MARCH 2004
TYPICAL CHARACTERISTICS
SN55LVDS32, SN65LVDS32
SUPPLY CURRENT
vs
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
FREQUENCY
85
2.7
2.5
2.3
Four Receivers, Loaded
Per Figure 3, Switching
Simultaneously
V
V
= 3.6 V
= 3.3 V
CC
75
V
CC
= 3 V
CC
V
CC
= 3.3 V
65
55
V
= 3 V
CC
V
CC
= 3.6 V
2.1
1.9
45
35
1.7
1.5
25
15
50
100
150
200
−50
0
50
100
f − Frequency − MHz
T
A
− Free-Air Temperature − °C
Figure 5.
Figure 6.
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
2.7
2.5
2.3
2.1
1.9
1.7
1.5
V
= 3 V
CC
V
CC
= 3.3 V
V
CC
= 3.6 V
−50
0
50
100
T
A
− Free-Air Temperature − °C
Figure 7.
11
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SLLS262N–JULY 1997–REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
−60
−50
−40
−30
−20
−10
0
0
10
20
30
40
50
60
70
80
I
− High-Level Output Current − mA
I
− Low-Level Output Current − mA
OH
OL
Figure 8.
Figure 9.
12
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SN65LVDS3486, SN65LVDS9637
www.ti.com
SLLS262N–JULY 1997–REVISED MARCH 2004
APPLICATION INFORMATION
USING AN LVDS RECEIVER WITH RS-422 DATA
Receipt of data from a TIA/EIA-422 line driver can be accomplished using a TIA/EIA-644 line receiver with the
addition of an attenuator circuit. This technique gives the user a high-speed and low-power 422 receiver.
If the ground noise between the transmitter and receiver is not a concern (less than ±1 V), the answer can be as
simple as shown in Figure 10. A resistor divider circuit in front of the LVDS receiver attenuates the 422
differential signal to LVDS levels.
The resistors present a total differential load of 100 Ω to match the characteristic impedance of the transmission
line and to reduce the signal 10:1. The maximum 422 differential output signal, or 6 V, is reduced to 600 mV. The
high input impedance of the LVDS receiver prevents input bias offsets and maintains a greater than 200-mV
differential input voltage threshold at the inputs to the divider. This circuit is used in front of each LVDS channel
that also receives 422 signals.
R1
45.3 Ω
’LVDS32
R3
5.11 Ω
A
B
Y
R4
5.11 Ω
R2
45.3 Ω
NOTE: The components used were standard values. (1) R1, R2 = NRC12F45R3TR, NIC components, 45.3 Ω, 1/8 W, 1%,
1206 package (2) R3, R4 = NRC12F5R11TR, NIC components, 5.11 Ω, 1/8 W, 1%, 1206 package (3) The resistor
values do not need to be 1% tolerance. However, it can be difficult locating a supplier of resistors having values less
than 100 Ω in stock and readily available. The user may find other suppliers with comparable parts having tolerances
of 5% or even 10%. These parts are adequate for use in this circuit.
Figure 10. RS-422 Data Input to an LVDS Receiver Under Low Ground-Noise Conditions
If ground noise between the RS-422 driver and LVDS receiver is a concern, the common-mode voltage must be
attenuated. The circuit must then be modified to connect the node between R3 and R4 to the LVDS receiver
ground. This modification to the circuit increases the common-mode voltage from ±1 V to greater than ±4.5 V.
The devices are generally used as building blocks for high-speed point-to-point data transmission where ground
differences are less than 1 V. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers
approach ECL speeds without the power and dual-supply requirements.
13
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SN65LVDS3486, SN65LVDS9637
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SLLS262N–JULY 1997–REVISED MARCH 2004
APPLICATION INFORMATION (continued)
TRANSMISSION DISTANCE
vs
SIGNALING RATE
100
10
30% Jitter
(see Note A)
5% Jitter
(see Note A)
1
24 AWG UTP 96 Ω
(PVC Dielectric)
0.1
10
100
Signaling Rate − Mbps
1000
A. This parameter is the percentage of distortion of the unit interval (UI) with a pseudorandom data pattern.
Figure 11. Typical Transmission Distance Versus Signaling Rate
3.3 V
1
2
16
1B
1A
V
CC
0.1 µF
(see Note A)
0.001 µF
(see Note A)
100 Ω
15
14
4B
4A
3
4
100 Ω
(see Note B)
1Y
G
V
CC
13
12
11
5
6
4Y
G
2Y
2A
See Note C
3Y
100 Ω
7
8
10
9
3A
3B
2B
100 Ω
GND
A. Place a 0.1-µF and a 0.001-µF Z5U ceramic, mica, or polystyrene dielectric, 0805 size, chip capacitor between VCC
and the ground plane. The capacitors should be located as close as possible to the device terminals.
B. The termination resistance value should match the nominal characteristic impedance of the transmission media with
±10%.
C. Unused enable inputs should be tied to VCC or GND as appropriate.
Figure 12. Typical Application Circuit Schematic
14
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SN65LVDS3486, SN65LVDS9637
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SLLS262N–JULY 1997–REVISED MARCH 2004
APPLICATION INFORMATION
1/4 ’LVDS31
Strb/Data_TX
TpBias on
Twisted-Pair A
Strb/Data_Enable
TP
TP
’LVDS32
55 Ω
5 kΩ
Data/Strobe
1 Arb_RX
55 Ω
3.3 V
20 kΩ
500 Ω
500 Ω
VG on
Twisted-Pair B
20 kΩ
3.3 V
20 kΩ
500 Ω
500 Ω
2 Arb_RX
20 kΩ
3.3 V
Twisted-Pair B Only
Port_Status
7 kΩ
7 kΩ
10 kΩ
3.3 kΩ
A. Resistors are leadless, thick film (0603), 5% tolerance.
B. Decoupling capacitance is not shown but recommended.
C. VCC is 3 V to 3.6 V.
D. The differential output voltage of the 'LVDS31 can exceed that allowed by IEEE1394.
Figure 13. 100-Mbps IEEE 1394 Transceiver
FAIL-SAFE
One of the most common problems with differential signaling applications is how the system responds when no
differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers in that
its output logic state can be indeterminate when the differential input voltage is between –100 mV and100 mV if it
is within its recommended input common-mode voltage range. However, TI LVDS receivers handle the
open-input circuit situation differently.
15
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SN65LVDS3486, SN65LVDS9637
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SLLS262N–JULY 1997–REVISED MARCH 2004
APPLICATION INFORMATION (continued)
Open-input circuit means that there is little or no input current to the receiver from the data line itself. This could
be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS
receiver pulls each line of the signal pair to near VCC through 300-kΩ resistors (see Figure 14). The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high level, regardless of the differential input voltage.
V
CC
300 kΩ
300 kΩ
A
B
Rt
Y
V
IT
≈ 2.3 V
Figure 14. Open-Circuit Fail-Safe of LVDS Receiver
It is only under these conditions that the output of the receiver is valid with less than a 100-mV differential input
voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it
is connected as shown in Figure 14. Other termination circuits may allow a dc current to ground that could defeat
the pullup currents from the receiver and the fail-safe feature.
0.01 µF
≈3.6 V
16
V
CC
5 V
1
2
1B
1A
0.1 µF
(see Note A)
1N645
(two places)
100 Ω
15
14
4B
4A
3
4
5
6
100 Ω
(see Note B)
1Y
G
V
CC
13
12
11
4Y
G
2Y
2A
See Note C
3Y
100 Ω
7
8
10
9
3A
3B
2B
100 Ω
GND
A. Place a 0.1-µF Z5U ceramic, mica, or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground
plane. The capacitor should be located as close as possible to the device terminals.
B. The termination resistance value should match the nominal characteristic impedance of the transmission media with
±10%.
C. Unused enable inputs should be tied to VCC or GND, as appropriate.
Figure 15. Operation With 5-V Supply
16
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SN55LVDS32, SN65LVDS32
SN65LVDS3486, SN65LVDS9637
www.ti.com
SLLS262N–JULY 1997–REVISED MARCH 2004
APPLICATION INFORMATION (continued)
RELATED INFORMATION
IBIS modeling is available for this device. Contact the local TI sales office or the TI Web site at www.ti.com for
more information.
For more application guidelines, see the following documents:
•
•
•
•
•
•
Low-Voltage Differential Signaling Design Notes (SLLA014)
Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038)
Reducing EMI With LVDS (SLLA030)
Slew Rate Control of LVDS Circuits (SLLA034)
Using an LVDS Receiver With TIA/EIA-422 Data (SLLA031)
Low Voltage Differential Signaling (LVDS) EVM (SLLA033)
17
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-9762201Q2A
5962-9762201QEA
5962-9762201QFA
5962-9762201VFA
5962-9762202Q2A
SN55LVDS32W
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
16
16
16
20
16
16
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
W
W
FK
W
D
CFP
LCCC
CFP
POST-PLATE N / A for Pkg Type
A42 SNPB N / A for Pkg Type
SN65LVDS32D
SOIC
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS32DG4
SN65LVDS32DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SO
D
D
16
16
16
16
16
16
16
16
16
16
16
16
16
8
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS32DRG4
SN65LVDS32NSR
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
NS
NS
PW
PW
PW
PW
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS32NSRG4
SN65LVDS32PW
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
MSOP
MSOP
MSOP
MSOP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS32PWG4
SN65LVDS32PWR
SN65LVDS32PWRG4
SN65LVDS3486D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS3486DG4
SN65LVDS3486DR
SN65LVDS3486DRG4
SN65LVDS9637D
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS9637DG4
SN65LVDS9637DGK
SN65LVDS9637DGKG4
SN65LVDS9637DGKR
SN65LVDS9637DGKRG4
SN65LVDS9637DGN
D
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGK
DGK
DGK
DGK
DGN
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2006
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN65LVDS9637DGNG4
ACTIVE
MSOP-
Power
PAD
DGN
8
8
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS9637DGNR
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGN
DGN
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS9637DGNRG4
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS9637DR
ACTIVE
ACTIVE
SOIC
D
D
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS9637DRG4
SOIC
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ55LVDS32FK
SNJ55LVDS32J
SNJ55LVDS32W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
16
16
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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