SN65LVDS33 [TI]
HIGH SPEED DIFFERENTIAL RECEIVERS; 高速差分接收器
| 型号： | SN65LVDS33 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH SPEED DIFFERENTIAL RECEIVERS |
| 文件： | 总20页 (文件大小：417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅꢆꢀ ꢇ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄꢅꢆꢉ ꢇ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄꢅꢆꢀ ꢇ ꢊ ꢈ ꢀꢁꢂ ꢃꢄꢅ ꢆꢉ ꢇꢊ
ꢋꢌ ꢍꢋ ꢎꢀꢏꢐ ꢐꢆ ꢆꢌ ꢑꢑ ꢐꢒ ꢐꢁꢉ ꢌꢓ ꢄ ꢒꢐ ꢔꢐ ꢌ ꢅꢐ ꢒ ꢀ
SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
1
SN65LVDS33D
SN65LVDT33D
SN65LVDS33PW
SN65LVDT33PW
D
400-Mbps Signaling Rate and 200-Mxfr/s
Data Transfer Rate
D
Operates With a Single 3.3-V Supply
D
−4-V to 5-V Common-Mode Input Voltage
Range
D OR PW PACKAGE
(TOP VIEW)
logic diagram (positive logic)
G
D
D
D
D
D
D
D
Differential Input Thresholds < 50 mV With
50 mV of Hysteresis Over Entire
Common-Mode Input Voltage Range
1B
1A
1Y
G
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
G
4B
4A
4Y
G
SN65LVDT33 ONLY
1A
1Y
1B
Integrated 110-Ω Line Termination
Resistors On LVDT Products
2Y
2A
2B
TSSOP Packaging (33 Only)
11 3Y
10 3A
2A
Complies With TIA/EIA-644 (LVDS)
2Y
2B
Active Failsafe Assures a High-Level
Output With No Input
9
GND
3B
3A
3Y
Bus-Pin ESD Protection Exceeds
15 kV HBM
3B
4A
Input Remains High-Impedance on Power
Down
4Y
4B
D
TTL Inputs Are 5-V Tolerant
D
Pin-Compatible With the AM26LS32,
SN65LVDS32B, µA9637, SN65LVDS9637B
SN65LVDS34D
SN65LVDT34D
D PACKAGE
(TOP VIEW)
description
logic diagram (positive logic)
V
1A
1B
2A
2B
1
2
3
4
8
7
6
5
This family of four LVDS data line receivers offers
CC
1A
1Y
2Y
the widest common-mode input voltage range in
the industry. These receivers provide an input
voltage range specification compatible with a 5-V
PECL signal as well as an overall increased
ground-noise tolerance. They are in industry
standard footprints with integrated termination as
an option.
1Y
2Y
1B
SN65LVDT34 ONLY
GND
2A
2B
Precise control of the differential input voltage
thresholds allows for inclusion of 50 mV of input
voltage hysteresis to improve noise rejection on
slowly changing input signals. The input thresh-
olds are still no more than 50 mV over the full
input common-mode voltage range.
AVAILABLE OPTIONS
NUMBER
†
PART NUMBER
TERMINATION
SYMBOLIZATION
OF
RESISTOR
RECEIVERS
SN65LVDS33D
4
4
4
4
2
2
No
No
LVDS33
LVDS33
LVDT33
LVDT33
LVDS34
LVDT34
SN65LVDS33PW
SN65LVDT33D
SN65LVDT33PW
SN65LVDS34D
SN65LVDT34D
Yes
Yes
No
The high-speed switching of LVDS signals usually
necessitates the use of a line impedance
matching resistor at the receiving-end of the cable
or transmission media. The SN65LVDT series of
receivers eliminates this external resistor by
integrating it with the receiver. The nonterminated
SN65LVDS series is also available for multidrop
or other termination circuits.
Yes
†
Add the suffix R for taped and reeled carrier.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
The signalling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
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Copyright 2001 − 2004, Texas Instruments Incorporated
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1
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ꢋ ꢌꢍ ꢋꢎꢀ ꢏꢐꢐ ꢆ ꢆ ꢌꢑ ꢑꢐ ꢒꢐ ꢁꢉ ꢌ ꢓꢄ ꢒꢐ ꢔꢐ ꢌ ꢅꢐ ꢒ ꢀ
SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
description (continued)
The receivers can withstand 15 kV human-body model (HBM) and 600 V machine model (MM) electrostatic
discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled
and other connections where potentially damaging noise is always a threat.
The receivers also include a (patent pending) failsafe circuit that will provide a high-level output within 600 ns
after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines,
or powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these
fault conditions. This feature may also be used for Wired-Or bus signaling. See The Active Failsafe Feature of
the SN65LVDS32B application note.
The intended application and signaling technique of these devices is point-to-point baseband data transmission
over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board
traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation
characteristics of the media and the noise coupling to the environment.
The SN65LVDS33, SN65LVDT33, SN65LVDS34 and SN65LVDT34 are characterized for operation from −40°C
to 85°C.
Function Tables
SN65LVDS33 and SN65LVDT33
DIFFERENTIAL INPUT ENABLES
= V − V
SN65LVDS34 and SN65LVDT34
DIFFERENTIAL INPUT OUTPUT
= V − V
OUTPUT
V
ID
G
H
X
H
X
H
X
L
G
X
L
Y
H
H
?
V
ID
Y
H
?
A
B
A
B
V
≥ -32 mV
ID
−100 mV < V ≤ −32 mV
V
ID
≥ -32 mV
ID
X
L
V
ID
≤ -100 mV
L
−100 mV < V ≤ −32 mV
ID
?
Open
H
X
L
L
H = high level, L = low level,
? = indeterminate
V
ID
≤ −100 mV
L
X
H
X
L
Z
H
H
H
X
Open
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
2
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SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
equivalent input and output schematic diagrams
V
CC
Attenuation
Network
6.5 kΩ
6.5 kΩ
V
CC
1 pF
60 kΩ
B Input
A Input
200 kΩ
3 pF
7 V
7 V
7 V
7 V
250 kΩ
LVDT Only 110 Ω
V
CC
V
CC
300 kΩ
(G Only)
100 Ω
Enable
Inputs
37 Ω
Y Output
7 V
7 V
300 kΩ
(G Only)
3
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ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢀꢇ ꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢉꢇ ꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢀꢇ ꢊ ꢈ ꢀꢁꢂ ꢃ ꢄꢅꢆꢉ ꢇ ꢊ
ꢋ ꢌꢍ ꢋꢎꢀ ꢏꢐꢐ ꢆ ꢆ ꢌꢑ ꢑꢐ ꢒꢐ ꢁꢉ ꢌ ꢓꢄ ꢒꢐ ꢔꢐ ꢌ ꢅꢐ ꢒ ꢀ
SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V
CC
Voltage range: Enables or Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1 V to 6 V
A or B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 V to 6 V
V − V (LVDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 V
A
B
Electrostatic discharge: A, B, and GND (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . Class 3, A: 15 kV, B: 500 V
Charged-device mode: All pins (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with JEDEC Standard 22, Test Method A114-A.
3. Tested in accordance with JEDEC Standard 22, Test Method C101.
DISSIPATION RATING TABLE
‡
T
A
≤ 25°C
OPERATING FACTOR
T = 85°C
A
POWER RATING
PACKAGE
POWER RATING
ABOVE T = 25°C
A
D8
PW16
D16
725 mW
5.8 mW/°C
6.2 mW/°C
7.6 mW/°C
377 mW
774 mW
402 mW
950 mW
494 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with
no air flow.
recommended operating conditions
MIN NOM
MAX
3.6
5
UNIT
Supply voltage, V
CC
3
2
3.3
V
V
V
High-level input voltage, V
IH
Enables
Enables
LVDS
Low-level input voltage, V
IL
0
0.8
3
0.1
Magnitude of differential input voltage, V
ID
V
LVDT
0.8
5
Voltage at any bus terminal (separately or common-mode), V or V
−4
V
I
IC
Operating free-air temperature, T
−40
85
°C
A
4
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SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
electrical characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
Positive-going differential input voltage threshold
50
IT1
Negative-going differential input voltage
threshold
V
= −4 V or 5 V, See Figures 1 and 2
mV
IB
−50
−32
IT2
Differential input failsafe voltage threshold
Differential input voltage hysteresis,
See Table 1 and Figure 5
−100
mV
mV
IT3
50
ID(HYS)
V
IT1
− V
IT2
V
V
High-level output voltage
Low-level output voltage
I
I
= −4 mA
= 4 mA
2.4
V
V
OH
OH
0.4
23
5
OL
OL
G at V
CC
,
No load, Steady-state
16
1.1
8
SN65LVDx33
G at GND
SN65LVDx34 No load,
V = 0 V,
I
Supply current
mA
CC
Steady-state
12
20
20
75
40
40
40
150
80
3
Other input open
Other input open
Other input open
Other input open
Other input open
Other input open
Other input open
Other input open
I
V = 2.4 V,
I
SN65LVDS
SN65LVDT
µA
V = −4 V,
I
V = 5 V,
I
I
I
Input current (A or B inputs)
Differential input current
V = 0 V,
I
V = 2.4 V,
I
µA
V = −4 V,
I
V = 5 V,
I
SN65LVDS
SN65LVDT
V
V
= 100 mV,
= 200 mV,
V
V
= −4 V or 5 V
= −4 V or 5 V
µA
ID
ID
IC
I
I
ID
(I − I
IA IB
)
1.55
2.22
20
50
30
100
10
10
10
mA
IC
V
or V = 0 V or 2.4 V,
V
= 0 V
A
B
CC
= 0 V
SN65LVDS
SN65LVDT
V
or V = −4 or 5 V,
V
CC
Power-off input current
(A or B inputs)
A
B
µA
I(OFF)
V
or V =0 V or 2.4 V, V
= 0 V
= 0 V
A
B
CC
CC
V
or V = −4 V or 5 V, V
B
A
I
I
I
High-level input current (enables)
Low-level input current (enables)
High-impedance output current
V
= 2 V
µA
µA
µA
pF
IH
IH
IL
V
= 0.8 V
IL
−10
OZ
C
Input capacitance, A or B input to GND
V = 0.4 sin (4E6πt) + 0.5 V
5
I
I
†
All typical values are at 25°C and with a 3.3 V supply.
5
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SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
switching characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Delay time, failsafe deactivate time
TEST CONDITIONS
MIN TYP
MAX
6
UNIT
ns
ns
ns
µs
ps
ps
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
2.5
2.5
4
4
PLH(1)
PHL(1)
d1
See Figure 3
6
9
C
= 10 pF,
L
See Figures 3 and 6
Delay time, failsafe activate time
0.3
1.5
d2
Pulse skew (|t
– t
PHL(1) PLH(1)
|)
200
150
sk(p)
sk(o)
sk(pp)
r
‡
Output skew
Part-to-part skew
§
1
See Figure 3
Output signal rise time
Output signal fall time
0.8
0.8
5.5
4.4
3.8
7
f
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
Propagation delay time, high-impedance -to-high-level output
Propagation delay time, high-impedance-to-low-level output
9
9
9
9
PHZ
PLZ
PZH
PZL
See Figure 4
†
‡
§
All typical values are at 25°C and with a 3.3-V supply.
t
is the magnitude of the time difference between the t
is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices
or t
of all receivers of a single device with all of their inputs driven together.
sk(o)
PLH
PHL
t
sk(pp)
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
6
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SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION
I
IA
A
B
V
O
Y
V
ID
V
IA
I
IB
(V + V )/2
IA IB
V
O
V
IC
V
IB
Figure 1. Voltage and Current Definitions
1000 Ω
†
100 Ω
100 Ω
V
ID
1000 Ω
V
O
10 pF,
2 Places
+
V
IC
−
10 pF
†
Remove for testing LVDT device.
V
IT1
0 V
V
ID
−100 mV
V
O
100 mV
0 V
V
ID
V
IT2
V
O
NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of <1 ns.
Figure 2. V
and V
Input Voltage Threshold Test Circuit and Definitions
IT2
IT1
7
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SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION
V
ID
V
IA
V
O
C
= 10 pF
V
IB
L
V
V
1.4 V
IA
1 V
IB
0.4 V
V
ID
0 V
−0.4 V
t
t
PLH
PHL
V
OH
1.4 V
80%
20%
80%
20%
V
O
V
OL
t
t
r
f
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
r
f
pulsewidth = 10 0.2 ns . C includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
L
Figure 3. Timing Test Circuit and Waveforms
8
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ꢀꢁꢂ ꢃ ꢄꢅꢆꢀ ꢇ ꢇ ꢈ ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢉꢇ ꢇ ꢈ ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢀꢇ ꢊ ꢈ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢉ ꢇꢊ
ꢋꢌ ꢍꢋ ꢎꢀꢏꢐ ꢐꢆ ꢆꢌ ꢑꢑ ꢐꢒ ꢐꢁꢉ ꢌꢓ ꢄ ꢒꢐꢔ ꢐ ꢌꢅ ꢐ ꢒꢀ
SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION
B
1.2 V
500 Ω
A
10 pF
V
O
Inputs
G
G
V
TEST
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse
r
f
repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 10 ns . C includes instrumentation and fixture
L
capacitance within 0,06 mm of the D.U.T.
2.5 V
V
TEST
A
1 V
2 V
1.4 V
0.8 V
G
G
2 V
1.4 V
0.8 V
t
t
PLZ
PLZ
t
t
PZL
PZL
Y
2.5 V
1.4 V
OL
OL
V
V
+0.5 V
V
TEST
0
1.4 V
A
G
2 V
1.4 V
0.8 V
2 V
1.4 V
0.8 V
t
PHZ
G
t
PHZ
t
t
PZH
PZH
Y
V
V
OH
OH
−0.5 V
1.4 V
0
Figure 4. Enable/Disable Time Test Circuit and Waveforms
9
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ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢀꢇ ꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢉꢇ ꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢀꢇ ꢊ ꢈ ꢀꢁꢂ ꢃ ꢄꢅꢆꢉ ꢇ ꢊ
ꢋ ꢌꢍ ꢋꢎꢀ ꢏꢐꢐ ꢆ ꢆ ꢌꢑ ꢑꢐ ꢒꢐ ꢁꢉ ꢌ ꢓꢄ ꢒꢐ ꢔꢐ ꢌ ꢅꢐ ꢒ ꢀ
SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION
Table 1. Receiver Minimum and Maximum V
Input Threshold Test Voltages
IT3
†
APPLIED VOLTAGES
RESULTANT INPUTS
V
IA
(mV) (mV)
V
V
(mV)
V (mV)
IC
Output
IB
ID
−100
−4000
−4000
4900
−3900
−3968
5000
−3950
−3984
4950
L
H
L
−32
−100
−32
4968
5000
4984
H
†
These voltages are applied for a minimum of 1.5 µs.
V
V
IA
−100 mV @ 250 KHz
IB
V
O
a) No Failsafe
V
IA
−32 mV @ 250 KHz
V
IB
V
O
Failsafe Asserted
b) Failsafe Asserted
Figure 5. V
Failsafe Threshold Test
IT3
1.4 V
1 V
0.4 V
>1.5 µs
0 V
−0.2 V
−0.4 V
t
t
d2
d1
V
OH
1.4 V
V
OL
Figure 6. Waveforms for Failsafe Activate and Deactivate
10
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ꢀꢁꢂ ꢃ ꢄꢅꢆꢀ ꢇ ꢇ ꢈ ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢉꢇ ꢇ ꢈ ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢀꢇ ꢊ ꢈ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢉ ꢇꢊ
ꢋꢌ ꢍꢋ ꢎꢀꢏꢐ ꢐꢆ ꢆꢌ ꢑꢑ ꢐꢒ ꢐꢁꢉ ꢌꢓ ꢄ ꢒꢐꢔ ꢐ ꢌꢅ ꢐ ꢒꢀ
SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT CURRENT
5
4
3
4
3
V
T
A
= 3.3 V
= 25°C
V
= 3.3 V
CC
CC
T = 25°C
A
2
1
2
1
0
0
0
10
20
30
40
−40
−30
−20
−10
0
I
− Low-Level Output Current − mA
I
OH
− High-Level Output Current − mA
OL
Figure 7
Figure 8
LOW-TO-HIGH PROPAGATION DELAY TIME
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
5
5
4.5
4
4.5
4
V
= 3 V
V
= 3 V
CC
CC
V
CC
= 3.3 V
V
CC
= 3.3 V
V
CC
= 3.6 V
V
CC
= 3.6 V
3.5
3
3.5
3
−50
0
50
100
−50
0
50
100
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 9
Figure 10
11
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ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢀꢇ ꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢉꢇ ꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢀꢇ ꢊ ꢈ ꢀꢁꢂ ꢃ ꢄꢅꢆꢉ ꢇ ꢊ
ꢋ ꢌꢍ ꢋꢎꢀ ꢏꢐꢐ ꢆ ꢆ ꢌꢑ ꢑꢐ ꢒꢐ ꢁꢉ ꢌ ꢓꢄ ꢒꢐ ꢔꢐ ꢌ ꢅꢐ ꢒ ꢀ
SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREQUENCY
140
120
V
= 3.3 V
100
80
CC
V
= 3.6 V
CC
60
40
V
CC
= 3 V
20
0
0
100
150
200
f − Switching Frequency − MHz
Figure 11
12
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ꢀꢁꢂ ꢃ ꢄꢅꢆꢀ ꢇ ꢇ ꢈ ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢉꢇ ꢇ ꢈ ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢀꢇ ꢊ ꢈ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢉ ꢇꢊ
ꢋꢌ ꢍꢋ ꢎꢀꢏꢐ ꢐꢆ ꢆꢌ ꢑꢑ ꢐꢒ ꢐꢁꢉ ꢌꢓ ꢄ ꢒꢐꢔ ꢐ ꢌꢅ ꢐ ꢒꢀ
SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
0.01 µF
≈3.6 V
16
V
CC
5 V
1
1B
0.1 µF
1N645
(see Note A)
(2 places)
100 Ω
2
1A
15
4B
3
100 Ω
(see Note B)
1Y
G
14
4
5
6
4A
V
CC
13
12
11
4Y
G
2Y
2A
See Note C
3Y
100 Ω
7
8
10
9
3A
3B
2B
100 Ω
GND
NOTES: A. Place a 0.1-µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between V
and the ground plane. The
CC
capacitor should be located as close as possible to the device terminals.
B. The termination resistance value should match the nominal characteristic impedance of the transmission media with 10%.
C. Unused enable inputs should be tied to V or GND as appropriate.
CC
Figure 12. Operation With 5-V Supply
related information
IBIS modeling is available for this device. Please contact the local TI sales office or the TI Web site at www.ti.com
for more information.
For more application guidelines, please see the following documents:
D
D
D
D
D
D
Low-Voltage Differential Signalling Design Notes (TI literature number SLLA014)
Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038)
Reducing EMI With LVDS (SLLA030)
Slew Rate Control of LVDS Circuits (SLLA034)
Using an LVDS Receiver With RS-422 Data (SLLA031)
Evaluating the LVDS EVM (SLLA033)
13
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ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢀꢇ ꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢉꢇ ꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢀꢇ ꢊ ꢈ ꢀꢁꢂ ꢃ ꢄꢅꢆꢉ ꢇ ꢊ
ꢋ ꢌꢍ ꢋꢎꢀ ꢏꢐꢐ ꢆ ꢆ ꢌꢑ ꢑꢐ ꢒꢐ ꢁꢉ ꢌ ꢓꢄ ꢒꢐ ꢔꢐ ꢌ ꢅꢐ ꢒ ꢀ
SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
active failsafe feature
A differential line receiver commonly has a failsafe circuit to prevent it from switching on input noise. Current
LVDS failsafe solutions require either external components with subsequent reductions in signal quality or
integrated solutions with limited application. This family of receivers has a new integrated failsafe that solves
the limitations seen in present solutions. A detailed theory of operation is presented in application note The
Active Failsafe Feature of the SN65LVDS32B, literature number SLLA082A.
The following figure shows one receiver channel with active failsafe. It consists of a main receiver that can
respond to a high-speed input differential signal. Also connected to the input pair are two failsafe receivers that
form a window comparator. The window comparator has a much slower response than the main receiver and
it detects when the input differential falls below 80 mV. A 600-ns failsafe timer filters the window comparator
outputs. When failsafe is asserted, the failsafe logic drives the main receiver output to logic high.
Output
Buffer
Main Receiver
+
_
A
B
R
Failsafe
Timer
Reset
A > B + 80 mV
+
_
Failsafe
B > A + 80 mV
+
_
Window Comparator
Figure 13. Receiver With Active Failsafe
14
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ꢀꢁꢂ ꢃ ꢄꢅꢆꢀ ꢇ ꢇ ꢈ ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢉꢇ ꢇ ꢈ ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢀꢇ ꢊ ꢈ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢉ ꢇꢊ
ꢋꢌ ꢍꢋ ꢎꢀꢏꢐ ꢐꢆ ꢆꢌ ꢑꢑ ꢐꢒ ꢐꢁꢉ ꢌꢓ ꢄ ꢒꢐꢔ ꢐ ꢌꢅ ꢐ ꢒꢀ
SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
ECL/PECL-to-LVTTL conversion with TI’s LVDS receiver
The various versions of emitter-coupled logic (i.e. ECL, PECL and LVPECL) are often the physical layer of
choice for system designers. Designers know of the established technology and that it is capable of high-speed
data transmission. In the past, system requirements often forced the selection of ECL. Now technologies like
LVDS provide designers with another alternative. While the total exchange of ECL for LVDS may not be a design
option, designers have been able to take advantage of LVDS by implementing a small resistor divider network
at the input of the LVDS receiver. TI has taken the next step by introducing a wide common-mode LVDS receiver
(no divider network required) which can be connected directly to an ECL driver with only the termination bias
voltage required for ECL termination (V
– 2 V).
CC
Figures 14 and 15 show the use of an LV/PECL driver driving 5 meters of CAT−5 cable and being received by
TI’s wide common-mode receiver and the resulting eye-pattern. The values for R3 are required in order to
provide a resistor path to ground for the LV/PECL driver. With no resistor divider, R1 simply needs to match the
characteristic load impedance of 50 Ω. The R2 resistor is a small value and is intended to minimize any possible
common-mode current reflections.
V
V
CC
I
CC
I
R1 = 50 Ω
R2 = 50 Ω
CC
CC
V
B
5 Meters
of CAT-5
LV/PECL
LVDS
V
B
R3
R3
R1
R1
V
EE
R2
R3 = 240 Ω
Figure 14. LVPECL or PECL to Remote Wide Common-Mode LVDS Receiver
Figure 15. LV/PECL to Remote SN65LVDS33 at 500 Mbps Receiver Output (CH1)
15
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ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢀꢇ ꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢉꢇ ꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢀꢇ ꢊ ꢈ ꢀꢁꢂ ꢃ ꢄꢅꢆꢉ ꢇ ꢊ
ꢋ ꢌꢍ ꢋꢎꢀ ꢏꢐꢐ ꢆ ꢆ ꢌꢑ ꢑꢐ ꢒꢐ ꢁꢉ ꢌ ꢓꢄ ꢒꢐ ꢔꢐ ꢌ ꢅꢐ ꢒ ꢀ
SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
test conditions
D
D
D
V
= 3.3 V
CC
T = 25°C (ambient temperature)
A
All four channels switching simultaneously with NRZ data. Scope is pulse-triggered simultaneously with
NRZ data.
equipment
D
D
D
Tektronix PS25216 programmable power supply
Tektronix HFS 9003 stimulus system
Tektronix TDS 784D 4-channel digital phosphor oscilloscope − DPO
Tektronix PS25216
Programmable
Power Supply
Tektronix HFS 9003
Stimulus System
Trigger
Tektronix TDS 784D 4-Channel
Digital Phosphor
Bench Test Board
Oscilloscope − DPO
Figure 16. Equipment Setup
100 Mbit/s
200 Mbit/s
Figure 17. Typical Eye Pattern SN65LVDS33
16
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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