SN65LVDS391PWRG4 [TI]
HIGH-SPEED DIFFERENTIAL LINE DRIVERS; 高速差分线路驱动器
| 型号： | SN65LVDS391PWRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-SPEED DIFFERENTIAL LINE DRIVERS |
| 文件： | 总18页 (文件大小：323K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
’LVDS389
DBT PACKAGE
(TOP VIEW)
’LVDS387
DGG PACKAGE
(TOP VIEW)
Four (’391), Eight (’389) or Sixteen (’387)
Line Drivers Meet or Exceed the
Requirements of ANSI EIA/TIA-644
Standard
GND
A1Y
A1Z
A2Y
A2Z
A3Y
A3Z
A4Y
A4Z
B1Y
B1Z
B2Y
B2Z
B3Y
B3Z
B4Y
B4Z
C1Y
C1Z
C2Y
C2Z
C3Y
C3Z
C4Y
C4Z
D1Y
D1Z
D2Y
D2Z
D3Y
D3Z
D4Y
D4Z
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND
A1Y
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
†
Designed for Signaling Rates up to
V
2
V
A1Z
A2Y
A2Z
A3Y
A3Z
A4Y
A4Z
NC
CC
2
CC
630 Mbps With Very Low Radiation (EMI)
V
3
GND
ENA
A1A
A2A
A3A
A4A
GND
CC
3
GND
ENA
A1A
A2A
A3A
A4A
ENB
B1A
B2A
B3A
B4A
GND
Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100-Ω Load
4
4
5
5
6
6
7
Propagation Delay Times Less Than 2.9 ns
Output Skew Is Less Than 150 ps
7
8
8
9
9
Part-to-Part Skew Is Less Than 1.5 ns
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
V
NC
10
11
12
13
14
15
16
CC
35-mW Total Power Dissipation in Each
Driver Operating at 200 MHz
GND
B1A
B2A
B3A
B4A
ENB
NC
B1Y
B1Z
B2Y
B2Z
B3Y
B3Z
B4Y
B4Z
Driver Is High Impedance When Disabled or
With V
< 1.5 V
CC
SN65’ Version Bus-Pin ESD Protection
Exceeds 15 kV
V
CC
V
CC
GND 17
18
GND 19
Packaged in Thin Shrink Small-Outline
Package With 20-mil Terminal Pitch
GND
C1A
C2A
C3A
C4A
ENC
D1A
D2A
D3A
D4A
END
GND
V
CC
Low-Voltage TTL (LVTTL) Logic Inputs Are
5-V Tolerant
’LVDS391
D OR PW PACKAGE
(TOP VIEW)
description
This family of four, eight, and sixteen differential
line drivers implements the electrical characteris-
tics of low-voltage differential signaling (LVDS).
Thissignalingtechniquelowerstheoutputvoltage
levels of 5-V differential standard levels (such as
EIA/TIA-422B) to reduce the power, increase the
switching speeds, and allow operation with a
3.3-V supply rail. Any of the sixteen current-mode
drivers will deliver a minimum differential output
voltage magnitude of 247 mV into a 100-Ω load
when enabled.
EN1,2
1Y
1Z
2Y
2Z
3Y
1
2
3
4
5
6
7
8
16
15
14
13
12
1A
2A
V
CC
GND
3A
V
11 3Z
10 4Y
CC
V
4A
CC
GND
EN3,4
9
4Z
Theintendedapplicationofthisdeviceandsignalingtechniqueisforpoint-to-pointandmultidropbasebanddata
transmission over controlled impedance media of approximately 100 Ω. The transmission media can be
printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same
substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of
clock and data for synchronous parallel data transfers. When used with the companion 16- or 8-channel
receivers, the SN65LVDS386 or SN65LVDS388, over 300 million data transfers per second in single-edge
clocked systems are possible with very little power. (Note: The ultimate rate and distance of data transfer is
dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other
system characteristics.)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
description (continued)
When disabled, the driver outputs are high impedance. Each driver input (A) and enable (EN) have an internal
pulldown that will drive the input to a low level when open circuited.
The SN65LVDS387, SN65LVDS389, and SN65LVDS391 are characterized for operation from –40°C to 85°C.
The SN75LVDS387, SN75LVDS389, and SN75LVDS391 are characterized for operation from 0°C to 70°C.
logic diagram (positive logic)
1Y
1Z
1Y
1Z
1A
1A
EN
2A
2Y
2Z
2Y
2Z
2A
EN
3A
3Y
3Z
3Y
3Z
3A
EN
4A
4Y
4Z
4Y
4Z
4A
(1/4 of ’LVDS387 or 1/2 of ’LVDS389 shown)
(’LVDS391 shown)
AVAILABLE OPTIONS
TEMPERATURE
RANGE
NO. OF
DRIVERS
BUS-PIN
ESD
†
PART NUMBER
SN65LVDS387DGG
SN75LVDS387DGG
SN65LVDS389DBT
SN75LVDS389DBT
SN65LVDS391D
–40°C to 85°C
0°C to 70°C
16
16
8
15 kV
4 kV
–40°C to 85°C
0°C to 70°C
15 kV
4 kV
8
–40°C to 85°C
0°C to 70°C
4
15 kV
4 kV
SN75LVDS391D
4
SN65LVDS391PW
–40°C to 85°C
0°C to 70°C
4
15 kV
4 kV
SN75LVDS391PW
4
†
This package is available taped and reeled. To order this packaging option, add
an R suffix to the part number (e.g., SN65LVDS387DGGR).
DRIVER FUNCTION TABLE
INPUT
ENABLE
OUTPUTS
A
EN
H
Y
H
L
Z
L
H
L
H
H
Z
H
X
L
Z
L
OPEN
H
H = high-level, L = low-level, X = irrelevant,
Z = high-impedance (off)
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
equivalent input and output schematic diagrams
EQUIVALENT OF EACH A OR EN INPUT
TYPICAL OF ALL OUTPUTS
V
CC
V
CC
50 Ω
A or EN
10 kΩ
5 Ω
Input
Y or Z
7 V
Output
300 kΩ
7 V
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
CC
Input voltage range: Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Y or Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Electrostatic discharge: SN65’ (Y, Z, and GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:15 kV, B: 500 V
SN75’ (Y, Z, and GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:4 kV, B: 400 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see Dissipation Rating Table)
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
‡
DERATING FACTOR
T
= 70°C
T = 85°C
A
POWER RATING
A
PACKAGE
T ≤ 25°C
A
ABOVE T = 25°C
POWER RATING
A
D
950 mW
1071 mW
2094 mW
774 mW
7.6 mW/°C
8.5 mW/°C
16.7 mW/°C
6.2 mW/°C
608 mW
494 mW
DBT
DGG
PW
688 mW
556 mW
1342 mW
496 mW
1089 mW
402 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) and with no air flow.
recommended operating conditions
MIN NOM MAX
UNIT
Supply voltage, V
CC
3
2
3.3
3.6
V
V
High-level input voltage, V
IH
Low-level input voltage, V
0.8
70
V
IL
SN75’
SN65’
0
°C
Operating free-air temperature, T
A
–40
85
°C
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
electrical characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
|V
|
Differential output voltage magnitude
247
340
454
OD
R
= 100 Ω,,
L
mV
Change in differential output voltage
magnitude between logic states
See Figure 1 and Figure 2
∆|V
|
–50
50
1.375
50
OD
V
Steady-state common-mode output voltage
1.125
–50
V
OC(SS)
Change in steady-state common-mode output
voltage between logic states
∆V
mV
mV
See Figure 3
OC(SS)
OC(PP)
V
Peak-to-peak common-mode output voltage
50
85
50
20
0.5
0.5
0.5
3
150
95
’LVDS387
Enabled,
’LVDS389
’LVDS391
’LVDS387
’LVDS389
’LVDS391
70
R
= 100 Ω,
= 0.8 V or 2 V
L
V
IN
26
I
Supply current
mA
CC
1.5
1.5
1.3
20
Disabled,
V = 0 V or V
IN
CC
I
I
High-level input current
Low-level input current
V
V
V
V
V
V
= 2 V
µA
µA
mA
mA
µA
µA
pF
IH
IH
= 0.8 V
2
10
IL
IL
or V
OZ
= 0 V
= 0 V
±24
±12
±1
±1
OY
OD
I
Short-circuit output current
OS
I
I
High-impedance output current
Power-off output current
Input capacitance
= 0 V or V
CC
OZ
O
= 1.5 V,
V = 2.4 V
O
O(OFF)
CC
C
V = 0.4 sin (4E6πt) + 0.5 V
I
5
IN
V = 0.4 sin (4E6πt) + 0.5 V,
Disabled
I
C
Output capacitance
9.4
pF
O
†
All typical values are at 25°C and with a 3.3-V supply.
switching characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
2.9
2.9
1
UNIT
t
t
t
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time
0.9
0.9
0.4
0.4
1.7
1.6
0.8
0.8
150
ns
ns
ns
ns
ps
PLH
PHL
r
R
C
= 100 Ω,
L
L
Differential output signal fall time
1
= 10 pF,
f
See Figure 4
Pulse skew (|t
– t
PHL PLH
|)
500
sk(p)
‡
t
Output skew
Part-to-part skew
80
150
1.5
ps
ns
sk(o)
§
t
sk(pp)
t
t
t
t
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
6.4
5.9
3.5
4.5
15
15
15
15
ns
ns
ns
ns
PZH
PZL
PHZ
PLZ
See Figure 5
†
All typical values are at 25°C and with a 3.3-V supply.
‡
§
t
t
is the magnitude of the time difference between the t
PLH
sk(pp)
or t
of all drivers of a single device with all of their inputs connected together.
sk(o)
PHL
isthemagnitudeofthedifferenceinpropagationdelaytimesbetweenanyspecifiedterminalsofanytwodevicescharacterizedinthisdata
sheet when both devices operate with the same supply voltage, at the same temperature, and have the same test circuits.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
PARAMETER MEASUREMENT INFORMATION
I
OY
Y
Z
I
I
A
V
V
OD
I
OZ
V
OY
GND
V
(V
OY
+ V )/2
OZ
OC
V
I
OZ
Figure 1. Voltage and Current Definitions
3.75 kΩ
Y
V
OD
Input
100 Ω
3.75 kΩ
Z
0 V ≤ V
TEST
≤ 2.4 V
±
Figure 2. VOD Test Circuit
49.9 Ω ± 1% (2 Places)
3 V
0 V
Y
Z
V
I
Input
V
OC(PP)
V
OC(SS)
50 pF
V
OC
V
O
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
r
f
pulse width = 500 ± 10 ns. C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of V
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
L
OC(PP)
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
2 V
Input
t
1.4 V
0.8 V
t
PLH
PHL
Y
Z
Input
100%
80%
V
OD
100 Ω ± 1 %
Output
V
OD(H)
C
= 10 pF
L
0 V
(2 Places)
V
OD(L)
20%
0%
t
t
r
f
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse
r
f
width = 10 ± 0.2 ns. C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
L
Figure 4. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
PARAMETER MEASUREMENT INFORMATION
49.9 Ω ± 1% (2 Places)
Y
0.8 V or 2 V
Z
+
1.2 V
–
C
= 10 pF
Input
L
V
OY
V
OZ
(2 Places)
2 V
1.4 V
Input
0.8 V
t
t
t
PZH
PHZ
PLZ
V
OY
or
1.4 V
1.3 V
V
OZ
1.2 V
t
PZL
1.2 V
1.1 V
1 V
V
OZ
or
V
OY
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
r
f
pulse width = 500 ± 10 ns. C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
L
Figure 5. Enable and Disable Time Circuit and Definitions
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
TYPICAL CHARACTERISTICS
’LVDS391
SUPPLY CURRENT (RMS)
vs
SWITCHING FREQUENCY
60
50
40
30
20
10
0
All outputs loaded and enabled.
V
CC
= 3.6 V
V
CC
= 3.3 V
V
CC
= 3 V
0
50
100
150
200
250
300
f – Frequency – MHz
Figure 6
’LVDS389
’LVDS387
SUPPLY CURRENT (RMS)
vs
SUPPLY CURRENT (RMS)
vs
SWITCHING FREQUENCY
SWITCHING FREQUENCY
110
100
90
240
220
200
180
160
140
120
100
80
V
= 3.6 V
CC
80
V
CC
= 3.6 V
70
V
CC
= 3.3 V
V
CC
= 3.3 V
60
V
CC
= 3 V
V
CC
= 3 V
50
All outputs loaded and enabled.
100 150 200 250 300
All outputs loaded and enabled.
150 200 250 300 350
40
0
50
0
50
100
f – Frequency – MHz
f – Frequency – MHz
Figure 7
Figure 8
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
TYPICAL CHARACTERISTICS
LOW-TO-HIGH PROPAGATION DELAY TIME
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
2.2
2.0
1.8
1.6
1.4
1.2
1.0
V
CC
= 3.6 V
V
= 3 V
CC
V
= 3.3 V
CC
V
= 3 V
CC
V
CC
= 3.3 V
V
= 3.6 V
CC
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
T
A
– Free-Air Temperature – °C
Ta – Free-Air Temperature – °C
Figure 9
Figure 10
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
4
3
3.5
3
V
T
A
= 3.3 V
= 25°C
CC
V
T
A
= 3.3 V
= 25°C
CC
2.5
2
2
1
1.5
1
0.5
0
0
0
2
4
6
–1
–4
–3
–2
0
I
– Low-Level Output Current – mA
I
– High-Level Output Current – mA
OL
OH
Figure 11
Figure 12
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
TIME
V
OY
V
OZ
V
OD
t – Time – ns
Figure 13
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
APPLICATION INFORMATION
Balanced Interconnect
Host
Target
Power
Power
T
Host
Target
DBn
DBn
Controller
Controller
T
T
T
DBn–1
DBn–2
DBn–3
DBn–1
DBn–2
DBn–3
T
T
T
T
DB2
DB1
DB2
DB1
DB0
DB0
TX Clock
RX Clock
SN65LVDS387 or 389
LVDS Receiver(s)
Indicates twisting of the
conductors.
Indicates the line termination
circuit.
T
Figure 14. Typical Application Schematic
Signaling Rate vs Distance
The ultimate data transfer rate over a given cable or trace length involves many variables. Starting with the
capabilities of this LVDS driver to reproduce a data pulse as short as 1.6 ns (a 630 Mbps signaling rate) with
less than 500 ps of pulse distortion, any degradation of this pulse by the transmission media will necessarily
reduce the timing margin at the receiving end of the data link.
The timing uncertainty induced by the transmission media is commonly referred to as jitter and comes from
numerous sources. The characteristics of a particular transmission media can be quantified by using an
eyepattern measurement such as shown in Figure 12, which shows about 340 ps of jitter or 20% of the data
pulse width.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
APPLICATION INFORMATION
height
abs .
jitter
width
unit interval
Figure 15. Typical LVDS Eyepattern
A generally accepted range of jitter at the receiver inputs that allows data recovery is 5% to 20% of the unit
interval (data pulse width). Table 1 shows the signaling rate achieved on various cables and lengths at a 5%
eyepattern jitter with a typical LVDS driver.
Table 1. Signaling Rates for Various Cables for 5% Eyepattern Jitter
†
CABLE
LENGTH
(m)
A
B
C
D
E
F
(Mbps)
(Mbps)
(Mbps)
(Mbps)
(Mbps)
(Mbps)
1
5
240
205
180
200
210
150
240
230
195
270
250
200
180
215
145
230
230
180
10
†
Cable A: CAT 3, specified up to 16 MHz, no shield, outside conductor diameter ( ) 0.52 mm
Cable B: CAT 5, specified up to 100 MHz, no shield, 0.52 mm
Cable C: CAT 5, specified up to 100 MHz, taped over all shield, 0.52 mm
Cable D: CAT 5 (exceeding CAT 5), specified up to 300 MHz, braided over all shield plus taped individual shield for any
pair, 0.64 mm (AWG22)
Cable E: CAT 5 (exceeding CAT 5), specified up to 350 MHz, 0.64 mm (AWG22), no shield
Cable F: CAT 5 (exceeding CAT 5), specified up to 350 MHz, “self-shielded”, 0.64 mm (AWG22)
During synchronous parallel transfers, skew between the data and clock lines will also reduce the timing margin.
This must be accounted for in the system timing budget. Fortunately, the low output skew of this LVDS driver
will generally be a small portion of this budget.
other LVDS products
For other products and applications notes in the LVDS and LVDM product families visit our Web site at
http://www.ti.com/sc/datatran.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–8°
0.044 (1,12)
A
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
MECHANICAL DATA
DBT (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
30 PINS SHOWN
0,27
0,17
M
0,50
30
0,08
16
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
15
0°–8°
0,75
0,50
A
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
28
30
38
44
50
DIM
7,90
7,70
7,90
7,70
9,80
9,60
11,10
10,90
12,60
12,40
A MAX
A MIN
4073252/D 09/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-153
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
MECHANICAL DATA
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
20-Apr-2007
PACKAGING INFORMATION
Orderable Device
SN65LVDS387DGG
SN65LVDS387DGGG4
SN65LVDS387DGGR
SN65LVDS387DGGRG4
SN65LVDS389DBT
SN65LVDS389DBTG4
SN65LVDS389DBTR
SN65LVDS389DBTRG4
SN65LVDS391D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
64
64
64
64
38
38
38
38
16
16
16
16
16
16
16
16
64
64
64
64
38
38
38
38
16
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TSSOP
TSSOP
TSSOP
SM8
DGG
DGG
DGG
DBT
DBT
DBT
DBT
D
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS391DG4
SN65LVDS391DR
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS391DRG4
SN65LVDS391PW
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
SM8
PW
PW
PW
PW
DGG
DGG
DGG
DGG
DBT
DBT
DBT
DBT
D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS391PWG4
SN65LVDS391PWR
SN65LVDS391PWRG4
SN75LVDS387DGG
SN75LVDS387DGGG4
SN75LVDS387DGGR
SN75LVDS387DGGRG4
SN75LVDS389DBT
SN75LVDS389DBTG4
SN75LVDS389DBTR
SN75LVDS389DBTRG4
SN75LVDS391D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SM8
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Apr-2007
Orderable Device
SN75LVDS391DG4
SN75LVDS391DR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75LVDS391DRG4
SN75LVDS391PW
SN75LVDS391PWG4
SN75LVDS391PWR
SN75LVDS391PWRG4
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
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