SN65LVPE502RGET [TI]
Dual Channel USB3.0 Redriver/Equalizer; 双通道USB3.0转接驱动器/均衡器
| 型号： | SN65LVPE502RGET |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual Channel USB3.0 Redriver/Equalizer |
| 文件： | 总24页 (文件大小：1343K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVPE502
www.ti.com
SLLSE29 –APRIL 2010
Dual Channel USB3.0 Redriver/Equalizer
Check for Samples: SN65LVPE502
1
FEATURES
•
Excellent Jitter and Loss Compensation
Capability: to 24"
•
Single Lane USB 3.0 Equalizer/Redriver
–
–
24" of 6 mil Stripline on FR4
•
Selectable Equalization, De-emphasis and
Output Swing Control
12" on Input and 4m, 26AWG USB 3.0 Cable
on Output
•
•
•
•
Integrated Termination
Hot-Plug Capable
Receiver Detect
Low Power:
•
•
Small foot print – 24 Pin (4mm × 4mm) QFN
Package
High Protection Against ESD Transient
–
–
–
HBM: 5,000 V
CDM: 1,500 V
MM: 200 V
–
315mW(TYP), VCC = 3.3V
•
Auto Low Power Modes:
–
–
5mW (TYP) When no Connection Detected
70mW (TYP) When in U2/U3 Mode
APPLICATIONS
•
Notebooks, Desktops, Docking Stations,
Backplane and Cabled Application
DESCRIPTION
The SN65LVPE502 is a dual channel, single lane USB 3.0 redriver and signal conditioner supporting data rates
of 5.0Gbps. The device complies with USB 3.0 spec revision 1.0, supporting electrical idle condition and low
frequency periodic signals (LFPS) for USB 3.0 power management modes.
Programmable EQ, De-Emphasis and Amplitude Swing
The SN65LVPE502 is designed to minimize signal degradation effects such as crosstalk and inter-symbol
interference (ISI) that limits the interconnect distance between two devices. The input stage of each channel
offers selectable equalization settings that can be programmed to match loss in the channel. The differential
outputs provide selectable de-emphasis to compensate for the anticipated distortion USB 3.0 signal will
experience. Level of de-emphasis will depend on the length of interconnect and its characteristics. The
SN65LVPE502 provides a unique way to tailor output de-emphasis on a per channel basis with use of DE and
OS pins. All Rx and Tx equalization settings supported by the device are programmed by six 3-state pins as
shown in Table 2.
Low Power Modes
The device supports three low power modes as described below.
1. Sleep Mode
Initiated anytime EN_RXD undergoes a high to low transition or when device powers up with EN_RXD set
low. In sleep mode both input and output terminations are held at HiZ and device ceases operation to
conserve power. Sleep mode max power consumption is 1mW, entry time is 2µs, device exits sleep mode to
Rx.Detect mode after EN_RXD is driven to VCC, exit time is 100µs max.
2. RX Detect Mode – When no remote device is connected
Anytime SN65LVPE502 detects a break in link (i.e., when upstream device is disconnected) or after powerup
fails to find a remote device, SN65LVPE502 goes to Rx Detect mode and conserves power by shutting down
majority of the internal circuitry. In this mode, input termination for both channels are driven to Hi-Z. In Rx
Detect mode device power is <10mW(TYP) or less than 5% of its normal operating power This feature is
useful in saving system power in mobile applications like notebook PC where battery life is critical.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65LVPE502
SLLSE29 –APRIL 2010
www.ti.com
Anytime an upstream device gets reconnected the redriver automatically senses the connection and goes to
normal operating mode. This operation requires no setting to the device.
3. U2/U3 Mode
With the help of internal timers the device tracks when link enters USB 3.0 low power modes U2 and U3, in
these modes link is in electrical idle state. SN65LVPE502 will selectively turn-off internal circuitry to save on
power. Typical power saving is about 75% lower than normal operating mode. The device will automatically
revert to active mode when signaling activity (LFPS) is detected.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION CONTINUED
Receiver Detection
RX.Detect cycle is performed by first setting Rx termination for each channel to Hi-Z, device then starts sensing
for receiver termination that may be attached at the other end of each TX.
If receiver is detected on both channel:
•
The TX and RX terminations are switched to ZDIFF-TX, ZDIFF-RX, respectively
If no receiver is detected on one or both channels:
•
•
•
The transmitter is pulled to Hi-Z
The channel is put in low power mode
Device attempts to detect Rx termination in 12 ms (TYP) interval until termination is found or the device is put
in sleep mode.
USB Compliance Mode
The device enters USB compliance mode when both EN_RXD and CM pins are set H. This mode is used to test
the transmitter for compliance to voltage and timing specifications per USB 3.0 compliance specs. In this mode
each channel will maintain its low-impedance termination RDC-RX, while auto Rx detect operation in the device is
disabled.
Electrical Idle Support
The electrical idle support is needed for low frequency periodic signaling (LFPS) used in USB 3.0 side band
communication. A link is in an electrical idle state when the TX± voltage is held at a steady constant value like
the common mode voltage. SN65LVPE502 detects an electrical idle state when RX± voltage at the device pin
falls below VRX_IDLE_DIFFpp min. After detection of an idle state in a given channel the device asserts electrical idle
state in its corresponding TX. When RX± voltage exceeds VRX_IDLE_DIFFpp max normal operation is restored and
output start passing input signal. The electrical idle exit and entry time is specified at ≤6 ns.
2
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Main PCB
Redriver
USB
Connector
USB Host
20"
Main PCB
Redriver
Device PCB
Device
Connector
USB Host
Cable
20"
1"-6"
Figure 1. Typical Application
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CM/EN_RXD
Detect
RX1+
TX1+
Receiver/
Equalizer
CHANNEL 1
Driver
RX1-
TX1-
EQ1
EQ2
EQ
V
CNTRL
TX_CM_DC
DE1
DE2
DEMP
CNTRL
TX2+
RX2+
RX2-
Receiver/
Equalizer
CHANNEL 2
Driver
TX2-
V
TX_CM_DC
OS
Detect
.
Cntrl
CM/EN_RXD
OS1
OS2
Figure 2. Data FLow Block Diagram
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BOTTOM VIEW
EQ1 DE1
EN_RXD
VCC
1
OS1
GND
6
SN65LVPE502
NC
NC 24
TX1-
7
RX1-
CH1
RX1+
TX1+
Thermal Pad
(must be soldered to
GND plane)
GND
GND
RX2-
TX2-
CH2
TX2+
12
19
RX2+
13
18
GND EQ2
DE2 OS2
TOP VIEW
VCC
CM
GND EN_RXD OS1
6
DE1 EQ1
VCC
1
SN65LVPE502
NC
24
NC
7
TX1-
TX1+
GND
RX2-
RX2+
RX1-
CH1
RX1+
Thermal Pad
(must be soldered to
GND plane)
GND
TX2-
CH2
TX2+
12
19
18
13
VCC
OS2 DE2 EQ2
GND
CM
Figure 3. Flow-Through Pin-Out
Table 1. Pin Description
PIN
NUMBER
NAME
I/O TYPE
DESCRIPTION
HIGH SPEED DIFFERENTIAL I/O PINS
8
RX1–
RX1+
RX2–
RX2+
TX1–
TX1+
TX2–
TX2+
I, CML
I, CML
I, CML
I, CML
O, CML
O, CML
O, CML
O, CML
9
Non-inverting and inverting CML differential input for CH 1 and CH 2. These pins are tied to
an internal voltage bias by dual termination resistor circuit
20
19
23
22
11
12
Non-inverting and inverting CML differential output for CH 1 and CH 2. These pins are
internally tied to voltage bias by termination resistors
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Table 1. Pin Description (continued)
PIN
DEVICE CONTROL PIN
5
EN_RXD
CM
I, LVCMOS Sets device operation modes per Table 2. Internally pulled to VCC
I, LVCMOS Sets device in compliance mode when pulled to VCC, internally pulled to GND
Pads not internally connected
14
7,24
NC
EQ CONTROL PINS(1)
3,16
2,17
DE1, DE2
I, LVCMOS Selects de-emphasis settings for CH 1 and CH 2 per Table 2. Internally tied to VCC/2
I, LVCMOS Selects equalization settings for CH 1 and CH 2 per Table 2. Internally tied to VCC/2
I, LVCMOS Selects output amplitude for CH 1 and CH 2 per Table 2. Internally tied to VCC/2
EQ1, EQ2
OS1, OS2
4, 15
POWER PINS
1,13
VCC
GND
Power
Power
Positive supply should be 3.3V ± 10%
Supply ground
6,10,18,21
(1) Internally biased to VCC/2 with >200kΩ pull-up/pull-down. When pins are left as NC board leakage at this pin pad must be < 1 µA
otherwise drive to VCC/2 to assert mid-level state.
Table 2. Signal Control Pin Setting
TRANSITION BIT AMPLITUDE
OSx(1)
(TYP mVpp)
NC (default)
1000
870
0
1
1085
EQx(1)
EQUALIZATION dB
NC (default)
0
7
0
1
15
DEx(1)
OSx(1) = NC
OSx(1) = 0
OSx(1) = 1
–4.4 dB
–6.0 dB
–7.6 dB
NC
0
–3.5 dB
–6.0 dB
–8.5 dB
–2.2 dB
–5.2 dB
–8.9 dB
1
EN_RXD
1 (default)
0
DEVICE FUNCTION
Normal operating mode
Sleep mode
CM
0 (default)
1
DEVICE FUNCTION
Normal Mode
Compliance mode
(1) Applies to Channel 1 and Channel 2 at 2.5 GHz.
USB Device
USB Host
Device PCB
Up to 3m
(30AWG)
8"-20"
1"-6"
2"-6"
Figure 4. Redriver Placement Example
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ORDERING INFORMATION(1)
PART MARKING
LVPE502
PART NUMBER
SN65LVPE502RGER
SN65LVPE502RGET
PCAKAGE
24-pin RGE Reel (large)
24-pin RGE Reel (small)
LVPE502
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNITS / VALUES
Supply Voltage Range(2)
Voltage Range
VCC
–0.5 V to 4 V
–0.5 V to 4 V
Differential I/O
Control I/O
–0.5 V to VCC + 0.5V
±5000V
Human Body Model(3)
Charged Device Model(4)
Machine Model(5)
Electrostatic discharge
±1500V
±200V
Continuous power dissipation
See Dissipation Rating Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101-A.
(5) Tested in accordance with JEDEC Standard 22, Test Method A115-A.
PACKAGE CHARACTERIZATION
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
CM, EN_RXD, EQ cntrl pins = NC, K28.5 pattern at 5 Gbps,
VID = 1000 mVpp
PD
Device power dissipation
330 450 mW
Device power dissipation under low
power mode
PSD
EN_RXD= GND
0.3
1
mW
THERMAL INFORMATION
SN65LVPE502
THERMAL METRIC(1)
RGE
UNITS
24 PINS
qJA
Junction-to-ambient thermal resistance(2)
Junction-to-case(top) thermal resistance
46
42
13
0.5
9
(3)
qJC(TOP)
qJB
(4)
Junction-to-board thermal resistance
°C/W
(5)
yJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
(6)
(7)
yJB
qJC(BOTTOM)
Junction-to-case(bottom) thermal resistance
4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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MAX UNIT
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
3
TYP
VCC
Supply Voltage
3.3
3.6
200
85
V
CCOUPLING
AC Coupling Capacitor
Operating free-air temperature
75
0
nF
°C
DEVICE POWER
The SN65LVPE502 is designed to operate from a single 3.3 V supply.
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
DEVICE PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX UNIT
EN_RXD, CM, EQ cntrl = NC,
K28.5 pattern at 5 Gbps, VID = 1000 mVpp
ICC
100
2
120
ICCRx.Detect
ICCsleep
In Rx.Detect mode
5
Supply Current
mA
EN_RXD = GND
0.1
ICCU2-U3
Link in USB low power state
21
Maximum Data Rate
Device Enable Time
5
Gbps
µs
Sleep mode exit time EN_RXD L→ H With
Rx termination present
tENB
100
tDIS
Device Disable Time
Rx.Detect Start Event
Sleep mode entry time EN_RXD H→ L
2
µs
µs
TRX.DETECT
Power-up time
100
CONTROL LOGIC (under recommended operating conditions)
VIH
High level Input Voltage
Low Level Input Voltage
Input Hysteresis
1.4
VCC
0.5
V
V
VIL
–0.3
VHYS
150
mV
OSx, EQx, DEx = VCC
EN_RXD = VCC
CM = VCC
30
1
IIH
High Level Input Current
Low Level Input Current
µA
µA
30
OSx, EQx, DEx = GND
EN_RXD = GND
CM = GND
–30
–30
–1
IIL
RECEIVER AC/DC
Vindiff_pp
AC coupled differential RX peak to peak
signal
RX1, RX2 Input Voltage Swing
100
1200 mVpp
V
VCM_RX
RX1, RX2 Common Mode Voltage
3.3
RX1, RX2 AC Peak common mode
voltage
Measured at Rx pins with termination
enabled
VinCOM_P
150 mVP
ZDC_RX
Zdiff_RX
DC common mode impedance
DC differential input impedance
18
72
26
80
30
Ω
Ω
120
Device in sleep mode Rx termination not
powered. Measured with respect to GND
over 500mV max
ZRX_High_IMP+
DC Input High Impedance
50
85
kΩ
Measured at receiver pin, below minimum
output is squelched, above max input signal
is passed to output
Low Voltage Periodic Signaling (LFPS)
Detect Threshold
VRX-LFPS-DETpp
100
300 mVpp
50 MHz – 1.25 GHz
1.25 GHz – 2.5 GHz
50 MHz – 2.5 GHz
10
6
11
7
RLRX-DIFF
RLRX-CM
Differential Return Loss
dB
dB
Common Mode Return Loss
11
13
8
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TRANSMITTER AC/DC
TEST CONDITIONS
MIN
TYP
MAX UNIT
RL =100Ω +1%, DEx, OSx = NC, Transition
Bit
800
1000
870
1200
RL =100Ω +1%, DEx, OSx = GND
Transition Bit
VTXDIFF_TB_PP
RL =100Ω +1%, DEx, OSx = VCC
Transition Bit
1085
665
Differential peak-to-peak Output
Voltage
(VID = 800, 1200 mVpp, 5Gbps)
mV
RL =100Ω +1%, DEx=NC,
OSx = 0,1,NC Non-Transition Bit
RL =100Ω +1%, DEx=0,
OSx = 0,1,NC Non-Transition Bit
VTXDIFF_NTB_PP
510
RL =100Ω +1%, DEx=1
OSx = 0,1,NC Non-Transition Bit
375
–3.0
–3.5
–6.0
–8.5
0.85
90
–4.0
dB
OS1,2 = NC (for OS1,2 = 1 and 0 see
Table 2)
De-Emphasis Level
TDE
De-Emphasis Width
UI
Zdiff_TX
ZCM_TX
DC Differential Impedance
DC Common Mode Impedance
72
18
9
120
30
Ω
Ω
Measured w.r.t to AC ground over 0-500mV
f = 50 MHz – 1.25 GHz
23
10
RLdiff_TX
Differential Return Loss
dB
f = 1.25 GHz – 2.5 GHz
6
7
RLCM_TX
Common Mode Return Loss
f = 50 MHz – 2.5 GHz
11
12
dB
mA
V
ITX_SC
TX short circuit current
TX± shorted to GND
60
VTX_CM_DC
VTX_CM_AC_Active
Transmitter DC common-mode voltage
TX AC common mode voltage active
2.0
0
2.6
30
3.0
100 mVpp
Electrical idle differential peak to peak
output voltage
VTX_idle_diff-AC-pp
VTX_CM_DeltaU1-U0
VTX_idle_diff-DC
Vdetect
HPF to remove DC
10
200
10
mV
mV
mV
mV
Absolute delta of DC CM voltage
during active and idle states
35
DC Electrical idle differential output
voltage
Voltage must be low pass filtered to remove
any AC component
0
Voltage change to allow receiver
detect
Positive voltage to sense receiver
termination
600
tR,tF
Output Rise/Fall time
30
50
ps
ps
20%-80% of differential voltage measure 1"
from the output pin
tRF_MM
Output Rise/Fall time mismatch
20
350
6
De-Emphasis = –3.5dB (CH 0 and CH 1).
Propagation delay between 50% level at
input and output See Figure 5
Tdiff_LH, Tdiff_HL
Differential Propagation Delay
290
ps
tidleEntry tidleExit
CTX
Idle entry and exit times
See Figure 6
At 2.5 GHz
4
ns
Tx input capacitance to GND
1.25
pF
EQUALIZATION
(1)(2)
TTX-EYE
Total Jitter (Tj) at point A
Deterministic Jitter (Dj)
Random Jitter (Rj)
0.14
0.06
0.08
0.14
0.06
0.08
0.5
0.3 UIpp(3)
(2)
DJTX
Device setting: OS1 = L, DE1 = H, EQ1 = L
Device setting: OS2 = H, DE2 = H, EQ2 = L
(2)(4)
RJTX
0.2
(1) (2)
TTX-EYE
Total Jitter (Tj) at point B
Deterministic Jitter (Dj)
Random Jitter (Rj)
0.5
0.3 UIpp(3)
(2)
DJTX
(2)(4)
RJTX
0.2
(1) Includes Rj at 10-12
(2) Measured at the end of reference channel in Figure 8 with K28.5 pattern, VID=1000mVpp, 5Gbps, –3.5dB DE from source.
(3) UI = 200ps
(4) Rj calculated as 14.069 times the RMS random jitter for 10-12 BER
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IN
T
T
diff_HL
diff_LH
OUT
Figure 5. Propagation Delay
vertical spacer
vertical spacer
IN+
V
V
EID_TH
CM
IN-
t
idleExit
t
idleEntry
OUT+
V
CM
OUT-
Figure 6. Electrical Idle Mode Exit and Entry Delay
vertical spacer
vertical spacer
80 %
20 %
t
t
r
f
Figure 7. Output RIse and Fall Times
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Jitter
Measurement
CH1
SN65LVPE502
A
1
2
AWG*
CH1
Up to 3m
(30AWG)
1"-6"
20"
4"
B
AWG*
CH2
*Source Jitter Measurements
Total Jitter
(ps)
21pp
Deterministic Jitter
Random Jitter
8pp
Jitter
Measurement
CH2
0.95 rms
Figure 8. Jitter Measurement Setup
vertical spacer
vertical spacer
1-bit
tDE
1 to N bits
1 to N bits
1-bit
EQx = NC
-3.5dB
-6dB
EQx = 0
-8.5dB
EQx = 1
V
CM
VTXDIFF_NTB_PP
VTXDIFF_TB_PP
tDE
Figure 9. Output De-Emphasis Levels OSx = NC
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Typical Eye Diagram and Performance Curves
Input Signal Characteristics: Data Rate = 5 Gbps, VID = 1000 mVpp, DE = -3.5 dB, Pattern = K28.5 Device
Operating Conditions: VCC = 3.3 V, Temp = 25°C
Input Trace Length Held Constant and Output Cable Length Varied
Figure 10. Input Trace = 12 Inches, 6 mil and Output USB 3 Cable Length = 1 M
vertical spacer
vertical spacer
Figure 11. Input Trace = 12 Inches, 6 mil and Output USB 3 Cable Length = 2 M
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Figure 12. Input Trace = 12 Inches, 6 mil and Output USB 3 Cable Length = 3 M
vertical spacer
vertical spacer
Figure 13. Input Trace = 12 Inches, 6 mil and Output USB 3 Cable Length = 4 M
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25
20
15
10
5
Output Deterministic Jitter vs
Output USB3.0 Cable Length With Fixed 12” Input Trace
0
1
1.5
2
2.5
3
3.5
4
Output USB Cable Length - m
Figure 14. Jitter Performance Over Different Cable Lengths
Input Trace Length Held Constant and Output Trace Varied
Figure 15. Input Trace = 4 Inches, 6 mil and Output Trace = 4 Inches, 6 mil
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Figure 16. Input Trace = 4 Inches, 6 mil and Output Trace = 8 Inches, 6 mil
vertical spacer
vertical spacer
Figure 17. Input Trace = 4 Inches, 6 mil and Output Trace = 12 Inches, 6 mil
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SLLSE29 –APRIL 2010
www.ti.com
Figure 18. Input Trace = 4 Inches, 6 mil and Output Trace = 16 Inches, 6 mil
vertical spacer
vertical spacer
Figure 19. Input Trace = 4 Inches, 6 mil and Output Trace = 20 Inches, 6 mil
16
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Product Folder Link(s): SN65LVPE502
SN65LVPE502
www.ti.com
SLLSE29 –APRIL 2010
10
9
8
7
6
5
4
3
2
1
0
Output Deterministic Jitter vs
Output Trace Length With Fixed 4” Input Trace
4
6
8
10
12
14
16
18
20
6 mil Output Trace Length - Inches
Figure 20. Jitter Performance Over Different Output Trace Lengths
vertical spacer
vertical spacer
Output Trace Length Held Constant and Input Trace Length Varied
Figure 21. Input Trace = 4 Inches, 6 mil and Output Trace = 4 Inches, 6 mil
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Product Folder Link(s): SN65LVPE502
SN65LVPE502
SLLSE29 –APRIL 2010
www.ti.com
Figure 22. Input Trace = 8 Inches, 6 mil and Output Trace = 4 Inches, 6 mil
vertical spacer
vertical spacer
Figure 23. Input Trace = 12 Inches, 6 mil and Output Trace = 4 Inches, 6 mil
18
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SN65LVPE502
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SLLSE29 –APRIL 2010
Figure 24. Input Trace = 16 Inches, 6 mil and Output Trace = 4 Inches, 6 mil
vertical spacer
vertical spacer
Figure 25. Input Trace = 20 Inches, 6 mil and Output Trace = 4 Inches, 6 mil
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Product Folder Link(s): SN65LVPE502
SN65LVPE502
SLLSE29 –APRIL 2010
www.ti.com
Figure 26. Input Trace = 28 Inches, 6 mil and Output Trace = 4 Inches, 6 mil
vertical spacer
vertical spacer
Figure 27. Input Trace = 32 Inches, 6 mil and Output Trace = 4 Inches, 6 mil
20
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): SN65LVPE502
SN65LVPE502
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SLLSE29 –APRIL 2010
14
12
10
8
6
4
2
Output Deterministic Jitter vs
Input Trace Length With Fixed 4” Output Trace
0
4
9
14
19
6 mil Input Trace Length - Inches
24
29
Figure 28. Jitter Performance Over Different Input Trace Lengths
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Product Folder Link(s): SN65LVPE502
PACKAGE OPTION ADDENDUM
www.ti.com
26-Apr-2010
PACKAGING INFORMATION
Orderable Device
SN65LVPE502RGER
SN65LVPE502RGET
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
VQFN
RGE
24
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
VQFN
RGE
24
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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