SN65MLVD205ADRG4 [TI]
MULTIPOINT-LVDS LINE DRIVER AND RECEIVER; 多点LVDS线路驱动器和接收器
| 型号： | SN65MLVD205ADRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MULTIPOINT-LVDS LINE DRIVER AND RECEIVER |
| 文件： | 总26页 (文件大小：548K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65MLVD200A, SN65MLVD202A
SN65MLVD204A, SN65MLVD205A
www.ti.com
SLLS573–DECEMBER 2003
MULTIPOINT-LVDS LINE DRIVER AND RECEIVER
FEATURES
DESCRIPTION
•
Low-Voltage Differential 30-Ω to 55-Ω Line
Drivers and Receivers for Signaling Rates
Up to 100 Mbps, Clock Frequencies up to
50 MHz
The SN65MLVD200A, 202A, 204A, and 205A are
multipoint-low-voltage differential (M-LVDS) line
drivers and receivers, which are optimized to operate
at signaling rates up to 100 Mbps. All parts comply
with the multipoint low-voltage differential signaling
(M-LVDS) standard TIA/EIA-899. These circuits are
similar to their TIA/EIA-644 standard compliant LVDS
counterparts, with added features to address
multipoint applications. The driver output has been
designed to support multipoint buses presenting
loads as low as 30 Ω, and incorporates controlled
transition times to allow for stubs off of the backbone
transmission line.
(1)
•
•
Type-1 Receivers Incorporate 25 mV of
Hysteresis (200A, 202A)
Type-2 Receivers Provide an Offset(100 mV)
Threshold to Detect Open-Circuit and Idle-Bus
Conditions (204A, 205A)
•
Meets or Exceeds the M-LVDS Standard
TIA/EIA-899 for Multipoint Data Interchange
•
•
Power Up/Down Glitch Free
These devices have Type-1 and Type-2 receivers
that detect the bus state with as little as 50 mV of
Controlled Driver Output Voltage Transition
Times for Improved Signal Quality
differential input voltage over
a common-mode
•
–1 V to 3.4 V Common-Mode Voltage Range
Allows Data Transfer With 2 V of Ground
Noise
voltage range of –1 V to 3.4 V. The Type-1 receivers
exhibit 25 mV of differential input voltage hysteresis
to prevent output oscillations with slowly changing
signals or loss of input. Type-2 receivers include an
offset threshold to provide a known output state
under open-circuit, idle-bus, and other fault
conditions.
•
•
Bus Pins High Impedance When Disabled or
VCC ≤ 1.5 V
200-Mbps Devices Available (SN65MLVD201,
203, 206, 207)
The SN65MLVD200A, 202A, 204A, and 205A have
enhancements over their predecessors. Improved
features include better controlled slew rate on the
driver output to help minimize reflections while
improving overall signal integrity (SI) resulting in
better jitter performance. Additionally, 8-kV ESD
protection on the bus pins for more robustness. The
same footprint definition was maintained making for
•
•
Bus Pin ESD Protection Exceeds 8 kV
Package in 8-Pin SOIC (200A, 204A) and
14-Pin SOIC (202A, 205A)
•
Improved Alternatives to the SN65MLVD200,
202, 204, and 205
APPLICATIONS
•
an easy drop-in replacement for
performance upgrade.
a
system
Low-Power High-Speed Short-Reach
Alternative to TIA/EIA-485
Backplane or Cabled Multipoint Data and
Clock Transmission
The devices are characterized for operation from
–40°C to 85°C.
•
•
•
•
Cellular Base Stations
Central-Office Switches
Network Switches and Routers
(1) The signaling rate of a line, is the number of voltage
transitions that are made per second expressed in the nits
bps (bits per second).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–TBD, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65MLVD200A, SN65MLVD202A
SN65MLVD204A, SN65MLVD205A
www.ti.com
SLLS573–DECEMBER 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
LOGIC DIAGRAM (POSITIVE LOGIC)
SN65MLVD200A, SN65MLVD204A
SN65MLVD202A, SN65MLVD205A
9
3
4
Y
Z
DE
D
5
D
DE
RE
10
4
3
2
1
RE
R
12
11
A
B
6
7
2
A
B
R
ORDERING INFORMATION
PART NUMBER(1)
SN65MLVD200AD
SM65MLVD202AD
SN65MLVD204AD
SM65MLVD205AD
FOOTPRINT
SN75176
RECEIVER TYPE
Type 1
PACKAGE MARKING
MF200A
SN75ALS180
SN75176
Type 1
MLVD202A
MF204A
Type 2
SN75ALS180
Type 2
MLVD205A
(1) Available tape and reeled. To order a tape and reeled part, add the suffix R to the part number (e.g., SN65MLVD200ADR).
PACKAGE DISSIPATION RATINGS
T
A ≤ 25°C
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
PACKAGE
POWER RATING
D(8)
532 mW
4.6 mW/°C
8.2 mW/°C
254 mW
450 mw
D(14)
940 mW
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
SN65MLVD200A,
202A, 204A, and 205A
Supply voltage range(2), VCC
D, DE, RE
–0.5 V to 4 V
–0.5 V to 4 V
–1.8 V to 4 V
–4 V to 6 V
Input voltage range
Output voltage range
Electrostatic discharge
A, B (200A, 204A)
A, B (202A, 205A)
R
–0.3 V to 4 V
–1.8 V to 4 V
±8 kV
Y, Z, A, or B
A, B, Y, and Z
All pins
Human Body Model(3)
±4 kV
Charged-Device Model(4)
All pins
±1500 V
Continuous power dissipation
Storage temperature range
See Dissipation Rating Table
–65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
2
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SN65MLVD204A, SN65MLVD205A
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SLLS573–DECEMBER 2003
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
VCC
VIH
VIL
Supply voltage
3
2
3.3
50
3.6
VCC
0.8
V
V
V
V
V
Ω
High-level input voltage
Low-level input voltage
GND
–1.4
0.05
30
Voltage at any bus terminal VA, VB, VY or VZ
Magnitude of differential input voltage
Differential load resistance
Signaling rate
3.8
|VID
|
VCC
RL
1/tUI
TA
100 Mbps
Operating free-air temperature
–40
85
°C
DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
(
(1)
TYP
PARAMETER
Driver only
TEST CONDITIONS
MIN
MAX
UNIT
mA
)
RE and DE at VCC, RL = 50 Ω, All others open
RE at VCC, DE at 0 V, RL = No Load, All others open
RE at 0 V, DE at VCC, RL = 50 Ω, All others open
RE at 0 V, DE at 0 V, All others open
13
1
22
4
Both disabled
Both enabled
Receiver only
ICC
Supply current
16
4
24
13
RL = 50 Ω, Input to D is a 50-MHz 50% duty cycle square
wave, DE = high, RE = low, TA = 85°C
PD
Device power dissipation
94
mW
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
3
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SN65MLVD200A, SN65MLVD202A
SN65MLVD204A, SN65MLVD205A
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SLLS573–DECEMBER 2003
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN(1) TYP(2)
MAX UNIT
|VAB| or
Differential output voltage magnitude
480
650
mV
|VYZ
|
See Figure 2
∆|VAB| or Change in differential output voltage magnitude
–50
0.8
50
1.2
50
mV
V
∆|VYZ
|
between logic states
VOS(SS)
∆VOS(SS)
VOS(PP)
Steady-state common-mode output voltage
Change in steady-state common-mode output
voltage between logic states
See Figure 3
–50
mV
mV
V
Peak-to-peak common-mode output voltage
150
2.4
VY(OC) or
VA(OC)
Maximum steady-state open-circuit output voltage
0
0
See Figure 7
See Figure 5
VZ(OC) or
VB(OC)
Maximum steady-state open-circuit output voltage
2.4
V
VP(H)
VP(L)
IIH
Voltage overshoot, low-to-high level output
Voltage overshoot, high-to-low level output
High-level input current (D, DE)
1.2 VSS
V
V
–0.2 VSS
VIH = 2 V to VCC
VIL = GND to 0.8 V
See Figure 4
0
0
10
10
24
µA
µA
mA
IIL
Low-level input current (D, DE)
|IOS
IOZ
IO(OFF)
|
Differential short-circuit output current magnitude
–1.4 V ≤ (VY or VZ) ≤ 3.8 V,
Other output = 1.2 V
High-impedance state output current (driver only)
Power-off output current
–15
–10
10
10
µA
µA
–1.4 V ≤ (VY or VZ) ≤ 3.8 V, Other
output = 1.2 V, 0 V ≤ VCC≤ 1.5 V
VI = 0.4 sin(30E6πt) + 0.5 V,(3)
Other input at 1.2 V, driver
disabled
CY or CZ Output capacitance
3
pF
pF
(3)
VAB = 0.4 sin(30E6πt) V,
CYZ
Differential output capacitance
Output capacitance balance, (CY/CZ)
2.5
Driver disabled
CY/Z
0.99
1.01
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) All typical values are at 25°C and with a 3.3-V supply voltage.
(3) HP4194A impedance analyzer (or equivalent)
4
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SN65MLVD204A, SN65MLVD205A
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SLLS573–DECEMBER 2003
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX
UNIT
Type 1
50
VIT+
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
mV
Type 2
Type 1
Type 2
Type 1
Type 2
150
–50
50
25
0
See Figure 9, Table 1 and Table
2
VIT-
mV
mV
VHYS
Differential input voltage hysteresis, (VIT+– VIT–)
VOH
VOL
IIH
High-level output voltage
Low-level output voltage
IOH = –8 mA
2.4
V
IOL = 8 mA
0.4
V
High-level input current (RE)
Low-level input current (RE)
High-impedance output current
VIH = 2 V to VCC
VIL = GND to 0.8 V
VO = 0 V or 3.6 V
–10
–10
–10
0
0
µA
µA
µA
IIL
IOZ
15
CA or
CB
VI = 0.4 sin(30E6πt) + 0.5 V,(2)
Other input at 1.2 V
VAB = 0.4 sin(30E6πt) V(2)
Input capacitance
3
pF
pF
CAB
Differential input capacitance
2.5
CA/B
Input capacitance balance, (CA/CB)
0.99
1.01
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) HP4194A impedance analyzer (or equivalent)
BUS INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
VB = 1.2 V,
VB = 1.2 V
MIN TYP(1) MAX
UNIT
VA = 3.8 V,
0
–20
–32
0
32
20
0
Receiver or transceiver with driver disabled
input current
IA
VA = 0 V or 2.4 V,
VA = -1.4 V,
µA
VB = 1.2 V
VB = 3.8 V,
VA = 1.2 V
32
20
0
Receiver or transceiver with driver disabled
input current
IB
VB = 0 V or 2.4 V,
VB = -1.4 V,
VA = 1.2 V
–20
–32
µA
µA
µA
VA = 1.2 V
Receiver or transceiver with driver disabled
differential input current (IA– IB)
IAB
VA = VB,
1.4 ≤ VA ≤ 3.8 V
-4
4
VA = 3.8 V,
VB = 1.2 V,
VB = 1.2 V,
VB= 1.2 V,
VA = 1.2 V,
VA = 1.2 V,
VA = 1.2 V,
0 V ≤ VCC ≤ 1.5 V
0
–20
–32
0
32
20
0
IA(OFF)
Receiver or transceiver power-off input current VA = 0 V or 2.4 V,
0 V ≤ VCC ≤ 1.5 V
0 V ≤ VCC ≤ 1.5 V
0 V ≤ VCC ≤ 1.5 V
0 V ≤ VCC ≤ 1.5 V
0 V ≤ VCC ≤ 1.5 V
VA = -1.4 V,
VB = 3.8 V,
32
20
0
IB(OFF)
Receiver or transceiver power-off input current VB = 0 V or 2.4 V,
VB = -1.4 V,
–20
–32
µA
Receiver input or transceiver power-off
differential input current (IA– IB)
IAB(OFF)
CA
VA = VB, 0 V ≤ VCC ≤ 1.5 V, –1.4 ≤ VA ≤ 3.8 V
VA = 0.4 sin (30E6πt) + 0.5 V(2), VB =1.2 V
VB = 0.4 sin (30E6πt) + 0.5 V(2), VA =1.2 V
VAB = 0.4 sin (30E6πt)V(2)
–4
4
µA
pF
pF
pF
Transceiver with driver disabled input
capacitance
5
5
Transceiver with driver disabled input
capacitance
CB
Transceiver with driver disabled differential
input capacitance
CAB
CA/B
3
Transceiver with driver disabled input
capacitance balance, (CA/CB)
0.99
1.01
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) HP4194A impedance analyzer (or equivalent)
5
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SN65MLVD204A, SN65MLVD205A
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SLLS573–DECEMBER 2003
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX UNIT
tpLH
tpHL
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time
2
2
2
2
2.5
2.5
2.6
2.6
30
3.5
3.5
3.2
3.2
150
0.9
3
ns
ns
ns
ns
ps
ns
ps
ps
ns
ns
ns
ns
See Figure 5
tf
Differential output signal fall time
tsk(p)
Pulse skew (|tpHL– tpLH|)
tsk(pp) Part-to-part skew
tjit(per) Period jitter, rms (1 standard deviation)(2)
50 MHz clock input(3)
100 Mbps 215-1 PRBS input(5)
2
55
4
tjit(pp)
tPHZ
tPLZ
tPZH
tPZL
Peak-to-peak jitter(2)(4)
150
7
Disable time, high-level-to-high-impedance output
Disable time, low-level-to-high-impedance output
Enable time, high-impedance-to-high-level output
Enable time, high-impedance-to-low-level output
4
7
See Figure 6
4
7
4
7
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(3) tr = tf = 0.5 ns (10% to 90%), measured over 30 k samples.
(4) Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).
(5) tr = tf = 0.5 ns (10% to 90%), measured over 100 k samples.
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
TYP(1)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
(1)
tPLH
tPHL
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Output signal rise time
2
2
1
1
3.6
3.6
6
6
ns
ns
ns
ns
ps
ps
ns
ps
ps
ps
ns
ns
ns
ns
2.3
2.3
300
500
1
tf
Output signal fall time
CL = 15 pF, See Figure 10
Type 1
Type 2
100
300
tsk(p)
Pulse skew (|tpHL– tpLH|)
tsk(pp) Part-to-part skew(2)
tjit(per) Period jitter, rms (1 standard deviation)(3)
50 MHz clock input(4)
4
200
225
6
7
Type 1
Type 2
700
800
10
tjit(pp)
Peak-to-peak jitter(3)(5)
100 Mbps 215–1 PRBS input(6)
tPHZ
tPLZ
tPZH
tPZL
Disable time, high-level-to-high-impedance output
Disable time, low-level-to-high-impedance output
Enable time, high-impedance-to-high-level output
Enable time, high-impedance-to-low-level output
6
10
See Figure 11
10
10
15
15
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) HP4194A impedance analyzer (or equivalent)
(3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(4) VID = 200 mVpp (LVD200A, 202A), VID = 400 mVpp (LVD204A, 205A), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 30 k
samples.
(5) Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).
(6) VID = 200 mVpp (LVD200A, 202A), VID = 400 mVpp (LVD204A, 205A), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 100 k
samples.
6
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SLLS573–DECEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
I
or I
A
Y
A/Y
B/Z
I
I
D
V
AB
or V
YZ
I
B
or I
Z
V
A
or V
Y
V
I
V
OS
V
B
or V
Z
V
A
+ V
2
V
Y
+ V
2
B
Z
or
Figure 1. Driver Voltage and Current Definitions
3.32 kΩ
A/Y
+
-1 V ≤ V
≤ 3.4 V
V
AB
or V
YZ
49.9 Ω
D
test
_
B/Z
3.32 kΩ
A. All resistors are 1% tolerance.
Figure 2. Differential Output Voltage Test Circuit
A/Y
B/Z
R1
≈ 1.3 V
≈ 0.7 V
24.9 Ω
A/Y
B/Z
C1
1 pF
D
V
nV
OS(SS)
OS(PP)
V
OS
C3
2.5 pF
R2
24.9 Ω
V
OS(SS)
C2
1 pF
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse frequency = 1
MHz, duty cycle = 50 ± 5%.
B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, ±1%, and located within 2 cm of the D.U.T.
D. The measurement of VOS(PP) is made on test equipment with a -3 dB bandwidth of at least 1 GHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
I
OS
A/Y
B/Z
0 V or V
CC
+
V
-
-1 V or 3.4 V
Test
Figure 4. Driver Short-Circuit Test Circuit
7
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SLLS573–DECEMBER 2003
PARAMETER MEASUREMENT INFORMATION (continued)
A/Y
C1
1 pF
C3
0.5 pF
R1
50 Ω
Output
D
B/Z
C2
1 pF
V
V
CC
/2
CC
Input
0 V
t
t
pHL
pLH
V
SS
0.9V
SS
V
P(H)
Output
0 V
V
P(L)
0.1V
SS
0 V
SS
t
f
t
r
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 1 MHz,
duty cycle = 50 ± 5%.
B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a -3 dB bandwidth of at least 1 GHz.
Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
R1
24.9 Ω
A/Y
C1
1 pF
D
C4
0.5 pF
0 V or V
Output
CC
C3
2.5 pF
C2
1 pF
B/Z
R2
24.9 Ω
DE
V
V
CC
/2
CC
DE
0 V
t
t
t
pZH
pHZ
0.6 V
0.1 V
Output With
D at V
0 V
CC
t
pZL
pLZ
Output With
D at 0 V
0 V
-0.1 V
-0.6 V
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 1 MHz,
duty cycle = 50 ± 5%.
B. C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a -3 dB bandwidth of at least 1 GHz.
Figure 6. Driver Enable and Disable Time Circuit and Definitions
8
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SLLS573–DECEMBER 2003
PARAMETER MEASUREMENT INFORMATION (continued)
A/Y
0 V or V
CC
B/Z
V , V , V or V
Z
1.62 kΩ , ±1%
A
B
Y
Figure 7. Maximum Steady State Output Voltage
V
V
CC
CLOCK
INPUT
/2
CC
0 V
1/f0
Period Jitter
IDEAL
OUTPUT
V
V
CC
0 V
Z
PRBS INPUT
/2
CC
V
A
-V or V -V
B
Y
1/f0
0 V
ACTUAL
OUTPUT
Peak to Peak Jitter
0 V
Z
V
-V or V -V
B Y Z
A
V
A
-V or V -V
B Y
OUTPUT 0 V Diff
-V or V -V
t
c(n)
V
t
=
t
-1/f0
A
B
Y
Z
jit(per)
c(n)
t
jit(pp)
A. All input pulses are supplied by an Agilent 81250 Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 50 MHz 50 ±1% duty cycle clock input.
D. Peak-to-peak jitter is measured using a 100Mbps 215–1 PRBS input.
Figure 8. Driver Jitter Measurement Waveforms
I
A
A
B
I
O
R
V
ID
V
O
V
CM
V
A
I
B
(V + V )/2
V
B
A
B
Figure 9. Receiver Voltage and Current Definitions
9
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Table 1. Type-1 Receiver Input Threshold Test Voltages
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON-
MODE INPUT VOLTAGE
APPLIED VOLTAGES
RECEIVER
(1)OUTPUT
VIA
VIB
VID
VIC
1.200
1.200
3.4
2.400
0.000
3.425
3.375
–0.975
–1.025
0.000
2.400
3.335
3.425
–1.025
–0.975
2.400
–2.400
0.050
–0.050
0.050
–0.050
H
L
H
L
3.4
–1
H
L
–1
(1) H= high level, L = low level, output state assumes receiver is enabled (RE = L)
Table 2. Type-2 Receiver Input Threshold Test Voltages
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON-
MODE INPUT VOLTAGE
APPLIED VOLTAGES
RECEIVER
OUTPUT(1)
VIA
VIB
VID
VIC
1.200
1.200
3.4
2.400
0.000
3.475
3.425
–0.925
–0.975
0.000
2.400
3.325
3.375
–1.075
–1.025
2.400
–2.400
0.150
0.050
0.150
0.050
H
L
H
L
3.4
–1
H
L
–1
(1) H= high level, L = low level, output state assumes receiver is enabled (RE = L)
V
ID
V
A
C
L
V
O
15 pF
V
B
V
1.2 V
1.0 V
A
V
B
V
ID
0.2 V
0 V
-0.2 V
t
t
pLH
pHL
V
OH
V
O
90%
10%
V
V
/2
CC
OL
t
f
t
r
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz,
duty cycle = 50 ± 5%. CL is a combination of a 20%-tolerance, low-loss ceramic, surface-mount capacitor and fixture
capacitance within 2 cm of the D.U.T.
B. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 10. Receiver Timing Test Circuit and Waveforms
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R
L
B
A
1.2 V
499 Ω
R
+
C
L
V
TEST
V
O
_
Inputs
RE
15 pF
V
CC
V
TEST
1 V
A
V
V
CC
RE
/2
/2
CC
0 V
t
t
pLZ
pZL
V
CC
V
CC
Output
V
R
V
V
+0.5 V
OL
OL
TEST
0 V
1.4 V
A
V
V
CC
RE
/2
CC
0 V
t
t
pHZ
pZH
V
V
V
OH
-0.5 V
OH
V
O
/2
CC
0 V
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz,
duty cycle = 50 ± 5%.
B. RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T.
C. CL is the instrumentation and fixture capacitance within 2 cm of the DUT and ±20%.
Figure 11. Receiver Enable/Disable Time Test Circuit and Waveforms
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INPUTS
-V
CLOCK INPUT
V
A
V
IC
B
0.2 V - Type 1
0.4 V - Type 2
1 V
V
A
-V
B
1/f0
Period Jitter
V
OH
IDEAL
OUTPUT
V
A
V /2
CC
PRBS INPUT
V
OL
1/f0
V
B
V
OH
ACTUAL
OUTPUT
Peak to Peak Jitter
V
/2
CC
V
OH
V
OL
OUTPUT
V
/2
t
CC
c(n)
t
=
t
-1/f0
V
OL
jit(per)
c(n)
t
jit(pp)
A. All input pulses are supplied by an Agilent 8304A Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 50 MHz 50 ±1% duty cycle clock input.
D. Peak-to-peak jitter is measured using a 100 Mbps 215-1 PRBS input.
Figure 12. Receiver Jitter Measurement Waveforms
PIN ASSIGNMENTS
SN65MLVD200AD (Marked as MF200A)
SN65MLVD204AD (Marked as MF204A)
(TOP VIEW)
SN65MLVD202AD (Marked as MLVD202A)
SN65MLVD205AD (Marked as MLVD205A)
(TOP VIEW)
R
RE
DE
D
V
B
A
1
2
3
4
8
7
6
5
NC
R
RE
V
V
A
B
Z
Y
1
2
3
4
5
6
7
14
13
12
11
10
9
CC
CC
CC
GND
DE
D
GND
GND
8
NC
NC - No internal connection
12
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SLLS573–DECEMBER 2003
DEVICE FUNCTION TABLES
TYPE-1 RECEIVER (200A, 202A)
TYPE-2 RECEIVER (204A, 205A)
INPUTS
= V - V
OUTPUT
R
INPUTS
= V - V
OUTPUT
R
RE
RE
V
ID
V
ID
A
B
A
B
L
L
H
?
L
Z
Z
L
L
H
?
L
Z
Z
V
≥ 50 mV
V
≥ 150 mV
ID
ID
-50 mV < V < 50 mV
50 mV < V < 150 mV
ID
ID
V
ID
≤ -50 mV
L
V
≤ 50 mV
L
ID
X
X
H
X
X
H
Open
Open
Open Circuit
?
Open Circuit
L
L
L
DRIVER
INPUT ENABLE
OUTPUTS
A OR Y B OR Z
D
DE
L
H
H
H
OPEN
L
L
H
L
Z
Z
H
L
H
Z
Z
H
OPEN
X
X
H = high level, L = low level, Z = high impedance, X = Don’t care, ? = indeterminate
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
DRIVER OUTPUT
DRIVER INPUT AND DRIVER ENABLE
RECEIVER ENABLE
V
CC
V
CC
V
CC
360 kΩ
400 Ω
400 Ω
D or DE
7 V
A/Y or B/Z
RE
7 V
360 kΩ
RECEIVER INPUT
RECEIVER OUTPUT
V
CC
V
CC
100 kΩ
250 kΩ
100 kΩ
250 kΩ
10 Ω
10 Ω
R
A
B
200 kΩ
200 kΩ
7 V
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
FREQUENCY
30
25
20
15
10
20
15
10
V
= 3.3 V
CC
f = 50 MHz
Tx
V
ID
V
IC
= 200 mV
= 1 V
Tx
Rx
Rx
V
= 3.3 V
= 200 mV
= 1 V
5
0
CC
V
ID
V
IC
5
0
T
A
= 25°C
10
20
30
40
50
−40
−15
10
35
60
85
T
A
− Free-Air Temperature − °C
f − Frequency − MHz
Figure 13.
Figure 14.
RECEIVER LOW-LEVEL OUTPUT CURRENT
RECEIVER HIGH-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
70
60
0
T
A
= 25°C
T
A
= 25°C
−10
V
CC
= 3.6 V
−20
−30
V
V
= 3.3 V
= 3.0 V
CC
50
40
30
CC
V
CC
= 3.0 V
−40
−50
−60
−70
V
CC
= 3.3 V
20
10
0
V
CC
= 3.6 V
−80
−90
0
1
2
3
4
0
1
2
3
4
V
OH
− High Level Output Voltage − V
V
OL
− Low Level Output Voltage − V
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
DRIVER PROPAGATION DELAY
vs
RECEIVER PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
2.8
4
V
V
V
= 3.3 V
= 200 mV
= 1 V
CC
V
= 3.3 V
CC
ID
IC
f = 1 MHz
= 50 Ω
R
L
3.80
f = 1 MHz
= 15 pF
t
2.6
2.4
2.2
2
C
pHL
L
t
pHL
3.60
3.40
t
pLH
t
pLH
3.20
3
−40
−15
10
35
60
85
−40
−15
10
35
60
85
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 17.
Figure 18.
ADDED DRIVER CYCLE-TO-CYCLE JITTER
ADDED DRIVER PEAK-TO-PEAK JITTER
vs
vs
CLOCK FREQUENCY
SIGNALING RATE
60
52
44
36
28
20
30
24
18
12
6
V
= 3.3 V
= 25°C
-1 PRBS NRZ
CC
V
= 3.3 V
= 25°C
CC
T
A
T
A
15
2
Input = Clock
0
10
20
30
40
50
20
40
60
80
100
Signaling Rate − Mbps
Clock Frequency − MHz
Figure 19.
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
ADDED DRIVER PEAK-TO-PEAK JITTER
ADDED RECEIVER CYCLE-TO-CYCLE JITTER
vs
vs
FREE-AIR TEMPERATURE
CLOCK FREQUENCY
80
72
64
56
48
40
40
34
28
22
16
10
V
= 3.3 V
= 25°C
= 1 V
CC
V
V
= 3.3 V
= 1 V
CC
T
A
IC
Type-1
= 200 mV
V
IC
f = 100 Mbps
15
V
ID
2
-1 PRBS NRZ
Type-2
= 400 mV
V
ID
10
20
30
40
50
−40
−15
10
35
60
85
Clock Frequency − MHz
T
A
− Free-Air Temperature − °C
Figure 21.
Figure 22.
ADDED RECEIVER PEAK-TO-PEAK JITTER
ADDED RECEIVER PEAK-TO-PEAK JITTER
vs
vs
SIGNALING RATE
FREE-AIR TEMPERATURE
300
300
240
180
120
Type-2
= 400 mV
V
T
= 3.3 V
Type-2
ID
CC
V
V
2
= 3.3 V
= 1 V
-1 PRBS NRZ
CC
V
ID
V
= 400 mV
= 255C
A
IC
V
= 1 V
15
IC
15
2
-1 PRBS NRZ
240
180
Type-1
= 200 mV
V
ID
Type-1
= 200 mV
120
60
0
V
ID
60
0
20
40
60
80
100
−40
−15
10
35
60
85
Signaling Rate − Mbps
T
A
− Free-Air Temperature − °C
Figure 23.
Figure 24.
16
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TYPICAL CHARACTERISTICS (continued)
SN65MLVD200A DRIVER OUTPUT EYE PATTERN
vs
100 Mbps, 215-1 PRBS, RL = 50 Ω
Horizontal Scale = 2 ns/div
Figure 25.
SN65MLVD200A RECEIVER OUTPUT EYE PATTERN
vs
100 Mbps, 215-1 PRBS, cL = 15 pF
Horizontal Scale = 2 ns/div
Figure 26.
17
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APPLICATION INFORMATION
COMPARISON OF MLVD TO TIA/EIA-485
Receiver Input Threshold (Failsafe)
The MLVD standard defines a type 1 and type 2 receiver. Type 1 receivers include no provisions for failsafe and
have their differential input voltage thresholds near zero volts. Type 2 receivers have their differential input
voltage thresholds offset from zero volts to detect the absence of a voltage difference. The impact to receiver
output by the offset input can be seen in Table 3 and Figure 27.
Table 3. Receiver Input Voltage Threshold Requirements
RECEIVER TYPE
Type 1
OUTPUT LOW
OUTPUT HIGH
0.05 V ≤ VID ≤ 2.4 V
0.15 V ≤ VID ≤ 2.4 V
–2.4 V ≤ VID ≤ -0.05 V
–2.4 V ≤ VID ≤ 0.05 V
Type 2
Type 1
High
Type 2
High
200
150
100
50
0
Low
-50
-100
Low
Transition Regions
Figure 27. Expanded Graph of Receiver Differential Input Voltage Showing Transition Region
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2007
PACKAGING INFORMATION
Orderable Device
SN65MLVD200AD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65MLVD200ADG4
SN65MLVD200ADR
SN65MLVD200ADRG4
SN65MLVD202AD
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
14
14
14
14
8
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65MLVD202ADG4
SN65MLVD202ADR
SN65MLVD202ADRG4
SN65MLVD204AD
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65MLVD204ADG4
SN65MLVD204ADR
SN65MLVD204ADRG4
SN65MLVD205AD
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
14
14
14
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65MLVD205ADG4
SN65MLVD205ADR
SN65MLVD205ADRG4
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2007
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
(mm)
SN65MLVD200ADR
SN65MLVD202ADR
SN65MLVD204ADR
SN65MLVD205ADR
D
D
D
D
8
14
8
FMX
FMX
FMX
FMX
0
0
0
0
6.4
6.5
6.4
6.5
5.2
9.0
5.2
9.0
2.1
2.1
2.1
2.1
8
8
8
8
12
16
12
16
Q1
Q1
Q1
Q1
14
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN65MLVD200ADR
SN65MLVD202ADR
SN65MLVD204ADR
SN65MLVD205ADR
D
D
D
D
8
14
8
FMX
FMX
FMX
FMX
342.9
342.9
342.9
342.9
336.6
336.6
336.6
336.6
20.6
28.58
20.6
14
28.58
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2007
Pack Materials-Page 3
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