SN74ACT1284DWG4 [TI]
7-BIT BUS INTERFACES WITH 3-STATE OUTPUTS;型号: | SN74ACT1284DWG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | 7-BIT BUS INTERFACES WITH 3-STATE OUTPUTS 驱动 光电二极管 输出元件 接口集成电路 驱动器 |
文件: | 总5页 (文件大小:96K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN54ACT1284, SN74ACT1284
7-BIT BUS INTERFACES
WITH 3-STATE OUTPUTS
SCAS459B – NOVEMBER 1994 – REVISED APRIL 1996
SN54ACT1284 . . . J OR W PACKAGE
SN74ACT1284 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
3-State Outputs Directly Drive Bus Lines
Flow-Through Architecture Optimizes PCB
Layout
Center-Pin V
Minimize High-Speed Switching Noise
and GND Configurations
A1
A2
A3
B1
B2
B3
B4
V
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
CC
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
A4
GND
GND
A5
A6
A7
CC
V
CC
Designed for the IEEE 1284-I (Level 1 Type)
and IEEE 1284-II (Level 2 Type) Electrical
Specifications
B5
13 B6
12 B7
Package Options Include Plastic
11
DIR
HD
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
DIP (N) Packages, Ceramic Chip Carriers
(FK), Flat (W), and DIP (J) Packages
FK PACKAGE
(TOP VIEW)
description
3
2
1 20 19
18
The ’ACT1284 are designed for asynchronous
two-way communication between data buses.
The control function minimizes external timing
requirements.
B3
B4
V
A4
GND
GND
A5
4
5
6
7
8
17
16
15
14
CC
V
CC
B5
A6
The devices allow data transmission in either the
A-to-B or the B-to-A direction for bits 1, 2, 3, and
4, depending on the logic level at the
direction-control (DIR) input. Bits 5, 6, and 7,
however, always transmit in the A-to-B direction.
9 10 11 12 13
The output drive for each mode is determined by the high drive (HD) control pin. When HD is high, the high drive
is delivered by the totem-pole configuration, and when HD is low, the outputs are open drain. This meets the
drive requirements as specified in the IEEE 1284-I (level 1 type) and the IEEE 1284-II (level 2 type) parallel
peripheral-interface specification.
The SN54ACT1284 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ACT1284 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUT
MODE
DIR
HD
Open drain
Totem pole
Totem pole
Open drain
Totem pole
A to B: Bits 5, 6, 7
B to A: Bits 1, 2, 3, 4
L
L
L
H
H
H
L
B to A: Bits 1, 2, 3, 4 and A to B: Bits 5, 6, 7
A to B: Bits 1, 2, 3, 4, 5, 6, 7
A to B: Bits 1, 2, 3, 4, 5, 6, 7
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT1284, SN74ACT1284
7-BIT BUS INTERFACES
WITH 3-STATE OUTPUTS
SCAS459B – NOVEMBER 1994 – REVISED APRIL 1996
logic diagram (positive logic)
HD
DIR
A1, A2, A3, A4
B1, B2, B3, B4
B5, B6, B7
A5, A6, A7
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
B-port input and output voltage range, V and V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . –2 V to 7 V
A-port input and output voltage range, V and V (see Note 1) . . . . . . . . . . . . . . . . . . . . –0.5 V to V + 0.5 V
I
O
I
O
CC
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The ac input voltage pulsewidth is limited to 20 ns if the input voltage goes more negative than –0.5 V.
3. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT1284, SN74ACT1284
7-BIT BUS INTERFACES
WITH 3-STATE OUTPUTS
SCAS459B – NOVEMBER 1994 – REVISED APRIL 1996
recommended operating conditions
SN54ACT1284 SN74ACT1284
UNIT
MIN
4.7
2
MAX
MIN
4.7
2
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
V
V
V
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
0
0
V
CC
5.5
0
0
V
CC
5.5
Open drain output voltage
HD low
O
B port, HD high
A port
–14
–4
14
4
–14
–4
14
4
I
High-level output current
mA
OH
OL
B port
I
Low-level output current
mA
A port
T
A
Operating free-air temperature
–55
125
0
70
°C
electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage (unless otherwise noted)
SN54ACT1284
SN74ACT1284
†
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
0.4
0.2
2.4
TYP
MAX
MIN
0.4
0.2
2.4
TYP
MAX
5 V
Input
hysteresis
V
V
V
– V for all inputs
IT–
V
hys
IT+
4.7 V
4.7 V
B port
I
I
= –14 mA
OH
MIN
to MAX
= –50 µA
V
CC
–0.2
3.7
V
CC
–0.2
3.7
V
V
OH
OH
OL
A port
I
I
I
I
= –4 mA
=14 mA
= 50 µA
= 4 mA
4.7 V
4.7 V
OH
OL
OL
OL
B port
A port
0.4
0.2
0.4
0.2
V
4.7 V
0.4
0.4
I
I
I
I
V = V
or GND
5.5 V
5.5 V
0 V
±1
±1
µA
µA
µA
mA
pF
pF
Ω
I
I
CC
= V or GND
CC
‡
A or B ports
B port
V
O
±20
±100
1.5
±20
±100
1.5
OZ
V or V ≤ 7 V
I
OFF
CC
O
V = V
I
or GND,
or GND
I
= 0
O
5.5 V
5 V
CC
CC
C
C
Control inputs V = V
4
4
i
I
A or B ports
B port
V
= V
or GND
5 V
12
12
io
O
O
CC
= –20 mA,
Z
I
I = –50 mA
OH
5 V
8
30
8
30
OH
†
‡
For I/O ports, the parameter I
OZ
includes the input leakage current I .
I
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ACT1284 SN74ACT1284
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1
MAX
20
MIN
1
MAX
20
t
t
PLH
Totem pole
A or B
B or A
ns
V/ns
ns
1
20
1
20
PHL
SR
Totem pole
Totem pole
Open drain
B output
0.05
1
0.4
20
0.05
1
0.4
20
t
t
(EN)
pd
HD
A
B
B
(DIS)
1
20
1
20
pd
t , t
r f
120
120
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT1284, SN74ACT1284
7-BIT BUS INTERFACES
WITH 3-STATE OUTPUTS
SCAS459B – NOVEMBER 1994 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
V
CC
From B Output
Under Test
3 V
0 V
Input
(see Note C)
62 Ω
C
= 50 pF
1.5 V
t
1.5 V
t
L
(see Note A)
TP1
Output
(see Note D)
t
PHL
Sink Load
PLH
PHL
33 Ω
V
OH
V
OH
V
OL
+ 1.4 V
V
OH
– 1.4 V
V
OL
V
OL
Source Load
C
t
PLH
62 Ω
VOLTAGE WAVEFORMS MEASURED AT TP1
PROPAGATION DELAY TIMES (A to B)
= 50 pF
L
(see Note A)
A-TO-B LOAD (totem pole)
3 V
0 V
Input
(see Note F)
V
CC
1.5 V
1.5 V
V
OH
OL
2 V
0.8 V
2 V
0.8 V
TP1
V
OL
V
500 Ω
(see Note E)
t
t
f
r
From B Output
VOLTAGE WAVEFORMS MEASURED AT TP1 (B SIDE)
C
= 50 pF
L
(see Note A)
A-TO-B LOAD (open drain)
3 V
0 V
Input
(see Note F)
1.5 V
1.5 V
From A Output
Under Test
t
t
PHL
PLH
V
V
OH
C
= 50 pF
L
500 Ω
Output
50% V
50% V
CC
(see Note A)
CC
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (B to A)
B-TO-A LOAD (totem pole)
NOTES: A. CL includes probe and jig capacitance.
B. The outputs are measured one at a time with one transition per measurement.
C. Input rise and fall times are 3 ns, 150 ns < pulsewidth <10 µs for both low-to-high and high-to-low transitions.
D. Slew rate is defined as 10% and 90% of the transition times.
E. Rise and fall times, open drain, are <120 ns.
F. Input rise and fall times are 3 ns.
Figure 1. Load Circuits and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1998, Texas Instruments Incorporated
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