SN74AHC16240 [TI]
16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS; 16位缓冲器/驱动器，具有三态输出
| 型号： | SN74AHC16240 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
| 文件： | 总8页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54AHC16240, SN74AHC16240
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS326G – MARCH 1996 – REVISED JANUARY 2000
SN54AHC16240 . . . WD PACKAGE
SN74AHC16240 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
EPIC (Enhanced-Performance Implanted
CMOS) Process
1OE
1Y1
1Y2
GND
1Y3
1Y4
1
2
3
4
5
6
7
8
9
48 2OE
47 1A1
46 1A2
45 GND
44 1A3
43 1A4
Operating Range 2-V to 5.5-V V
CC
Distributed V
High-Speed Switching Noise
and GND Pins Minimize
CC
Flow-Through Architecture Optimizes PCB
Layout
V
42
V
CC
CC
Latch-Up Performance Exceeds 250 mA Per
JESD 17
2Y1
2Y2
41 2A1
40 2A2
39 GND
38 2A3
37 2A4
36 3A1
35 3A2
34 GND
33 3A3
32 3A4
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
GND 10
2Y3 11
2Y4 12
3Y1 13
3Y2 14
GND 15
3Y3 16
3Y4 17
description
V
18
31
V
The ’AHC16240 devices are 16-bit buffers and
line drivers designed specifically to improve the
performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented
receivers and transmitters.
CC
CC
4Y1 19
4Y2 20
GND 21
4Y3 22
30 4A1
29 4A2
28 GND
27 4A3
23
24
26
25
4Y4
4OE
4A4
3OE
These devices can be used as four 4-bit buffers,
two8-bitbuffers, orone16-bitbuffer. Theyprovide
inverting outputs and symmetrical active-low
output-enable (OE) inputs.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54AHC16240 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AHC16240 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 4-bit buffer/driver)
INPUTS
OUTPUT
Y
OE
A
H
L
L
L
L
H
Z
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 2000, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC16240, SN74AHC16240
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS326G – MARCH 1996 – REVISED JANUARY 2000
†
logic symbol
1
1OE
EN1
EN2
EN3
EN4
48
2OE
25
3OE
24
4OE
47
1A1
46
2
3
1
1
1
1
2
3
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
1A2
44
5
1A3
43
6
1A4
41
8
2A1
40
9
2A2
38
11
12
13
14
16
17
19
20
22
23
2A3
37
2A4
36
3A1
35
3A2
33
3A3
32
3A4
30
4A1
29
1
4
4A2
27
4A3
26
4A4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC16240, SN74AHC16240
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS326G – MARCH 1996 – REVISED JANUARY 2000
logic diagram (positive logic)
1
25
36
1OE
3OE
3A1
47
2
3
5
6
13
1A1
1Y1
1Y2
1Y3
1Y4
3Y1
46
35
33
32
14
1A2
3A2
3A3
3A4
3Y2
44
16
1A3
3Y3
43
17
1A4
3Y4
48
24
30
2OE
4OE
4A1
41
8
9
19
2A1
2Y1
2Y2
2Y3
2Y4
4Y1
40
29
27
26
20
2A2
4A2
4A3
4A4
4Y2
38
11
12
22
2A3
4Y3
37
23
2A4
4Y4
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through each V
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA
CC
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC16240, SN74AHC16240
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS326G – MARCH 1996 – REVISED JANUARY 2000
recommended operating conditions (see Note 3)
SN54AHC16240 SN74AHC16240
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
V
V
V
V
V
= 2 V
1.5
2.1
3.85
1.5
2.1
3.85
CC
CC
CC
CC
CC
CC
High-level input voltage
= 3 V
V
V
IH
= 5.5 V
= 2 V
0.5
0.9
0.5
0.9
V
IL
Low-level input voltage
= 3 V
= 5.5 V
1.65
5.5
1.65
5.5
V
V
Input voltage
0
0
0
0
V
V
A
I
Output voltage
V
V
CC
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
–50
–4
–8
50
4
–50
–4
–8
50
4
I
High-level output current
Low-level output current
= 3.3 ± 0.3 V
= 5 ± 0.5 V
= 2 V
OH
OL
mA
A
I
= 3.3 ± 0.3 V
= 5 ± 0.5 V
= 3.3 ± 0.3 V
= 5 ± 0.5 V
mA
8
8
100
20
125
100
20
85
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
A
–55
–40
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
2
SN54AHC16240 SN74AHC16240
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
1.9
MAX
MIN
1.9
MAX
MIN
1.9
MAX
2 V
3 V
I
= –50
A
2.9
3
2.9
2.9
OH
V
V
4.5 V
3 V
4.4
4.5
4.4
4.4
V
OH
OL
I
I
= –4 mA
= –8 mA
2.58
3.94
2.48
3.8
2.48
3.8
OH
4.5 V
2 V
OH
0.1
0.1
0.1
0.1
0.1
0.5
0.5
±1*
0.1
0.1
I
= 50
A
3 V
OL
4.5 V
3 V
0.1
0.1
V
I
I
= 4 mA
= 8 mA
0.36
0.36
±0.1
0.44
0.44
±1
OL
4.5 V
0 V to 5.5 V
OL
I
I
V = V
or GND
A
A
I
CC
= V
V
or GND,
O
I
CC
V (OE) = V or V
IH
5.5 V
±0.25
±2.5
±2.5
I
OZ
CC
IL
I
V = V
or GND,
or GND
I = 0
O
5.5 V
5 V
4
40
40
10
A
pF
pF
I
CC
CC
C
C
V = V
2.5
3.5
10
i
I
V
= V or GND
CC
5 V
o
O
* On products compliant to MIL-PRF-38535, this parameter is not production tested at V
= 0 V.
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC16240, SN74AHC16240
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS326G – MARCH 1996 – REVISED JANUARY 2000
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
SN54AHC16240 SN74AHC16240
UNIT
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
MIN
MAX
8.4*
8.4*
MIN
1*
1*
1*
1*
1*
1*
1
MAX
MIN
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
5.3*
10*
1
10
PLH
PHL
PZH
PZL
PHZ
PLZ
PLH
PHL
PZH
PZL
PHZ
PLZ
sk(o)
A
Y
Y
Y
Y
Y
Y
C
C
C
C
C
= 15 pF
= 15 pF
= 15 pF
= 50 pF
= 50 pF
ns
ns
ns
ns
ns
L
L
L
L
L
5.3*
10*
1
10
6.6* 10.6*
6.6* 10.6*
7.8* 11.5*
7.8* 11.5*
7.8 11.9*
12.5*
12.5*
12.5*
12.5*
13.5
13.5
16
1
12.5
12.5
12.5
12.5
13.5
13.5
16
OE
OE
A
1
1
1
1
7.8
9.1
11.9
14.1
14.1
14
1
1
1
1
OE
OE
9.1
1
16
1
16
10.3
10.3
1
16
1
16
C
C
= 50 pF
= 50 pF
ns
ns
L
L
14
1
16
1
16
**
1.5
1.5
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
** On products compliant to MIL-PRF-38535, this parameter does not apply.
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
3.6*
3.6*
4.7*
4.7*
5.2*
5.2*
5.1
SN54AHC16240 SN74AHC16240
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
ns
MIN
MAX
6*
MIN
1*
1*
1*
1*
1*
1*
1
MAX
7*
MIN
1
MAX
6.5
t
t
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
PLH
PHL
PZH
PZL
PHZ
PLZ
sk(o)
A
Y
Y
Y
Y
Y
Y
C
C
C
C
C
= 15 pF
= 15 pF
= 15 pF
= 50 pF
= 50 pF
L
L
L
L
L
6*
7*
1
6.5
7.3*
7.3*
7.2*
7.2*
8
8.5*
8.5*
8.5*
8.5*
9
1
8.5
ns
OE
OE
A
1
8.5
1
8.5
ns
1
8.5
1
8.5
ns
5.1
8
1
9
1
8.5
6.2
9.3
9.3
9.2
9.2
1
10.5
10.5
10.5
10.5
1
10.5
10.5
10.5
10.5
1
ns
OE
OE
6.2
1
1
6.7
1
1
C
C
= 50 pF
= 50 pF
ns
ns
L
L
6.7
1
1
**
1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
** On products compliant to MIL-PRF-38535, this parameter does not apply.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC16240, SN74AHC16240
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS326G – MARCH 1996 – REVISED JANUARY 2000
noise characteristics, V
= 5 V, C = 50 pF, T = 25°C (see Note 4)
CC
L
A
SN74AHC16240
PARAMETER
UNIT
MIN
TYP
0.6
MAX
V
V
V
V
V
Quiet output, maximum dynamic V
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
–0.6
4.6
OL
OH
3.5
1.5
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
No load, f = 1 MHz
TYP
UNIT
C
Power dissipation capacitance
10
pF
pd
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC16240, SN74AHC16240
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS326G – MARCH 1996 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
su
V
CC
V
CC
50% V
50% V
CC
Input
CC
50% V
50% V
CC
Data Input
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
50% V
50% V
50% V
t
Input
CC
CC
CC
CC
0 V
0 V
t
PZL
t
t
t
PLZ
PLH
PHL
Output
Waveform 1
V
OH
≈V
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
(see Note B)
V
OL
+ 0.3 V
CC
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
– 0.3 V
50% V
50% V
50% V
CC
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Copyright 2000, Texas Instruments Incorporated
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