SN74AHCT1G04DBVRE4 [TI]
AHCT/VHCT/VT SERIES, 1-INPUT INVERT GATE, PDSO5, PLASTIC, SOT-23, 5 PIN;
| 型号： | SN74AHCT1G04DBVRE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | AHCT/VHCT/VT SERIES, 1-INPUT INVERT GATE, PDSO5, PLASTIC, SOT-23, 5 PIN 输入元件 光电二极管 逻辑集成电路 |
| 文件： | 总19页 (文件大小：902K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SN74AHCT1G04
SCLS319P –MARCH 1996–REVISED DECEMBER 2014
SN74AHCT1G04 Single Inverter Gate
1 Features
2 Applications
1
•
•
•
•
•
•
Operating Range 4.5-V to 5.5-V
Max tpd of 7.5 ns at 5-V
•
•
•
•
•
•
Notebook PCs
Electronic Points of Sale
Patient Monitoring
Motor Controls: AC Induction
Network Switches
Tests
Low Power Consumption, 10-μA Max ICC
±8-mA Output Drive at 5-V
Inputs are TTL-Voltage Compatible
Latch-Up Performance Exceeds 250 mA Per
JESD 17
3 Description
The SN74AHCT1G04 contains one gate. The device
performs the Boolean function Y = A.
Device Information(1)
PART NUMBER
PACKAGE
SOT-23 (5)
SC-70 (5)
BODY SIZE (NOM)
2.90 mm x 1.60 mm
2.00 mm x 1.30 mm
SN74AHCT1G04
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
A
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AHCT1G04
SCLS319P –MARCH 1996–REVISED DECEMBER 2014
www.ti.com
Table of Contents
9.1 Overview ................................................................... 7
9.2 Functional Block Diagram ......................................... 7
9.3 Feature Description................................................... 7
9.4 Device Functional Modes.......................................... 7
10 Application and Implementation.......................... 8
10.1 Application Information............................................ 8
10.2 Typical Application ................................................. 8
11 Power Supply Recommendations ....................... 9
12 Layout................................................................... 10
12.1 Layout Guidelines ................................................. 10
12.2 Layout Example .................................................... 10
13 Device and Documentation Support ................. 10
13.1 Trademarks........................................................... 10
13.2 Electrostatic Discharge Caution............................ 10
13.3 Glossary................................................................ 10
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Simplified Schematic............................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings ............................................................ 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Switching Characteristics.......................................... 5
7.7 Operating Characteristics.......................................... 5
7.8 Typical Characteristics.............................................. 5
Parameter Measurement Information .................. 6
Detailed Description .............................................. 7
14 Mechanical, Packaging, and Orderable
8
9
Information ........................................................... 10
5 Revision History
Changes from Revision O (October 2013) to Revision P
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
•
Deleted Ordering Information table. ....................................................................................................................................... 1
Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. .......................................... 4
2
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SCLS319P –MARCH 1996–REVISED DECEMBER 2014
6 Pin Configuration and Functions
DBV OR DCK PACKAGE
(TOP VIEW)
1
2
3
5
4
NC
A
V
Y
CC
GND
NC – No internal connection
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
1
NAME
NC
—
I
No Connection
Input A
2
A
3
GND
Y
—
O
—
Ground Pin
Output Y
4
5
VCC
Power Pin
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SCLS319P –MARCH 1996–REVISED DECEMBER 2014
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
MAX
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Output voltage range(2)
7
7
V
VO
IIK
VCC + 0.5
–20
V
Input clamp current
VI < 0
mA
mA
mA
mA
°C
IOK
IO
Output clamp current
VO < 0 or VO > VCC
VO = 0 to VCC
±20
Continuous output current
Continuous current through VCC or GND
Storage temperature range
±25
±50
Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions() is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
1500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions(1)
MIN
MAX
UNIT
V
VCC
VIH
VIL
VI
Supply voltage
4.5
2
5.5
High-level input voltage
Low-level Input voltage
Input voltage
V
0.8
5.5
VCC
–8
V
0
0
V
VO
Output voltage
V
IOH
IOL
High-level output current
Low-level output current
Input Transition rise or fall rate
Operating free-air temperature
mA
mA
ns/V
°C
8
Δt/Δv
TA
20
–40
125
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004)
7.4 Thermal Information
SN74AHCT1G04
THERMAL METRIC(1)
DBV
DCK
UNIT
5 PINS
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
231.3
119.9
60.6
287.6
97.7
65.
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
17.8
2.0
ψJB
60.1
64.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
4
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SCLS319P –MARCH 1996–REVISED DECEMBER 2014
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
TA = 25°C
TYP
–40°C to 85°C
–40°C to 125°C
PARAMETER
TEST CONDITIONS
VCC
4.5 V
4.5 V
UNIT
V
MIN
4.4
MAX
MIN
4.4
MAX
MIN
4.4
MAX
IOH = –50 µA
IOH = –8 mA
IOL = 50 µA
IOL = 8 mA
4.5
VOH
3.94
3.8
3.8
0.1
0.1
0.1
VOL
V
0.36
0.44
0.44
0 V to
5.5 V
II
VI = 5.5 V or GND
±0.1
1
±1
10
±1
10
µA
µA
VI = VCC or
IO = 0
ICC
5.5 V
GND,
One input at 3.4 V, Other
Inputs at VCC or GND
(1)
ΔICC
5.5 V
5 V
1.35
1.5
10
1.5 mA
Ci
VI = VCC or GND
4
10
pF
(1) This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC
.
7.6 Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
TA = 25°C
–40°C to 85°C
MIN MAX
7.5
–40°C to 125°C
MIN MAX
FROM
(INPUT)
TO
(OUTPUT)
OUTPUT
CAPACITANCE
PARAMETER
UNIT
ns
TYP
4.7
4.7
5.5
5.5
MAX
tPLH
tPHL
tPLH
tPHL
1
1
1
1
1
1
1
1
8
8
9
9
A or B
A or B
Y
Y
CL = 15 pF
CL = 50 pF
7.5
8.5
8.5
ns
7.7 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
No load, f = 1 MHz
TYP
UNIT
pF
Cpd
Power dissipation capacitance
14
7.8 Typical Characteristics
6
5
4
3
2
1
TPD in ns
100 150
0
-100
-50
0
50
Temperature (qC)
D001
Figure 1. TPD vs Temperature
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SCLS319P –MARCH 1996–REVISED DECEMBER 2014
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8 Parameter Measurement Information
V
CC
Open
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
From Output
Under Test
GND
Point
t
t
/t
PLH PHL
Open
C
C
L
(see Note A)
t /t
PLZ PZL
V
CC
GND
L
(see Note A)
/t
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
3 V
0 V
1.5 V
Timing Input
t
w
t
h
3 V
t
su
3 V
0 V
1.5 V
1.5 V
Input
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
PLZ
t
t
t
PZL
PLH
PHL
Output
V
≈V
OH
CC
Waveform 1
In-Phase
Output
50% V
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
CC
(see Note B)
V
V
+ 0.3 V
OL
V
OL
OL
t
t
PZH
t
PHL
PLH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
– 0.3 V
OH
50% V
50% V
CC
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output
control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output
control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf
≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit And Voltage Waveforms
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9 Detailed Description
9.1 Overview
The SN74AHCT1G04 device contains one inverter. This device has TTL input levels that allow up translation
from 3.3 V to 5 V.
9.2 Functional Block Diagram
A
Y
Figure 3. Logic Diagram (Positive Logic)
9.3 Feature Description
•
•
VCC is optimized at 5 V
Allows up voltage translation from 3.3 V to 5 V
Inputs accept VIH levels of 2 V
–
•
•
Slow edge rates minimize output ringing
Inputs are TTL-Voltage compatible
9.4 Device Functional Modes
Table 1. Function Table
INPUT
A
OUTPUT
Y
H
L
L
H
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SCLS319P –MARCH 1996–REVISED DECEMBER 2014
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
SN74AHCT1G04 is a low-drive CMOS device that can be used for a multitude of inverting type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The input switching levels have been lowered to accommodate TTL inputs of 0.8 V VILand 2 V VIH.
This feature makes it Ideal for translating up from 3.3 V to 5 V. Figure 5 shows this type of translation.
10.2 Typical Application
3.3-V accessory
5-V regulated
0.1 µF
Figure 4. Typical Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads, so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
–
–
–
For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions(1) table.
For specified High and low levels, see VIH and VIL in the Recommended Operating Conditions(1) table.
Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC
.
2. Recommend Output Conditions
–
–
Load currents should not exceed 25 mA per output and 50 mA total for the part.
Outputs should not be pulled above VCC
.
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004)
8
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Typical Application (continued)
10.2.3 Application Curves
Figure 5. 3.3-V to 5-V Translation
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions(1) table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and
1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
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12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 6 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when
asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.
12.2 Layout Example
V
cc
Input
Unused Input
Output
Output
Unused Input
Input
Figure 6. Layout Diagram
13 Device and Documentation Support
13.1 Trademarks
All trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
10
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Jan-2015
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
74AHCT1G04DBVRE4
74AHCT1G04DBVRG4
74AHCT1G04DBVTE4
74AHCT1G04DBVTG4
74AHCT1G04DCKRE4
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SC70
DBV
5
5
5
5
5
3000
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
B04G
B04G
B04G
B04G
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DBV
DBV
DBV
DCK
3000
250
Call TI
Call TI
250
Call TI
Call TI
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(BC3 ~ BCG ~ BCJ ~
BCL ~ BCS)
74AHCT1G04DCKRG4
74AHCT1G04DCKTG4
SN74AHCT1G04DBVR
ACTIVE
ACTIVE
ACTIVE
SC70
SC70
DCK
DCK
DBV
5
5
5
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
(BC3 ~ BCG ~ BCJ ~
BCL ~ BCS)
Green (RoHS
& no Sb/Br)
(BC3 ~ BCG ~ BCL ~
BCS)
SOT-23
3000
Green (RoHS
& no Sb/Br)
(B042 ~ B043 ~
B04G ~ B04J ~
B04L ~ B04S)
SN74AHCT1G04DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(B042 ~ B043 ~
B04G ~ B04L ~
B04S)
SN74AHCT1G04DCKR
SN74AHCT1G04DCKT
ACTIVE
ACTIVE
SC70
SC70
DCK
DCK
5
5
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
(BC3 ~ BCG ~ BCJ ~
BCL ~ BCS)
Green (RoHS
& no Sb/Br)
(BC3 ~ BCG ~ BCL ~
BCS)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jan-2015
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74AHCT1G04 :
Automotive: SN74AHCT1G04-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Aug-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AHCT1G04DBVR SOT-23
SN74AHCT1G04DBVR SOT-23
SN74AHCT1G04DBVT SOT-23
SN74AHCT1G04DBVT SOT-23
DBV
DBV
DBV
DBV
DCK
DCK
DCK
DCK
DCK
DCK
DCK
5
5
5
5
5
5
5
5
5
5
5
3000
3000
250
180.0
178.0
178.0
178.0
178.0
178.0
180.0
180.0
178.0
178.0
180.0
8.4
9.2
9.0
9.2
9.2
9.0
9.2
8.4
9.2
9.0
9.2
3.23
3.3
3.17
3.2
1.37
1.55
1.37
1.55
1.22
1.2
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
3.23
3.3
3.17
3.2
250
SN74AHCT1G04DCKR
SN74AHCT1G04DCKR
SN74AHCT1G04DCKR
SN74AHCT1G04DCKR
SN74AHCT1G04DCKT
SN74AHCT1G04DCKT
SN74AHCT1G04DCKT
SC70
SC70
SC70
SC70
SC70
SC70
SC70
3000
3000
3000
3000
250
2.4
2.4
2.4
2.5
2.3
2.55
2.3
1.2
2.47
2.4
1.25
1.22
1.2
2.4
250
2.4
2.5
250
2.3
2.55
1.2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Aug-2014
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74AHCT1G04DBVR
SN74AHCT1G04DBVR
SN74AHCT1G04DBVT
SN74AHCT1G04DBVT
SN74AHCT1G04DCKR
SN74AHCT1G04DCKR
SN74AHCT1G04DCKR
SN74AHCT1G04DCKR
SN74AHCT1G04DCKT
SN74AHCT1G04DCKT
SN74AHCT1G04DCKT
SOT-23
SOT-23
SOT-23
SOT-23
SC70
DBV
DBV
DBV
DBV
DCK
DCK
DCK
DCK
DCK
DCK
DCK
5
5
5
5
5
5
5
5
5
5
5
3000
3000
250
202.0
180.0
180.0
180.0
180.0
180.0
205.0
202.0
180.0
180.0
205.0
201.0
180.0
180.0
180.0
180.0
180.0
200.0
201.0
180.0
180.0
200.0
28.0
18.0
18.0
18.0
18.0
18.0
33.0
28.0
18.0
18.0
33.0
250
3000
3000
3000
3000
250
SC70
SC70
SC70
SC70
SC70
250
SC70
250
Pack Materials-Page 2
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相关型号：
SN74AHCT1G04DCKR
The SN74AHCT1G04 contains one gate. The device performs the Boolean function Y = A.
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