SN74ALS29821FN [TI]
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| 型号： | SN74ALS29821FN |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 暂无描述 触发器 输出元件 |
| 文件： | 总6页 (文件大小：92K) |
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SN54ALS29821, SN74ALS29821
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS145B – JANUARY 1986 – REVISED JANUARY 1995
SN54ALS29821 . . . JT PACKAGE
SN74ALS29821 . . . DW OR NT PACKAGE
(TOP VIEW)
• Functionally Equivalent to AMD’s AM29821
• Provide Extra Data Width Necessary for
Wider Address/Data Paths or Buses With
Parity
OE
1D
2D
3D
4D
5D
6D
7D
8D
V
CC
1
2
3
4
5
6
7
8
9
24
• Outputs Have Undershoot-Protection
23 1Q
22 2Q
21 3Q
20 4Q
19 5Q
18 6Q
17 7Q
16 8Q
15 9Q
14 10Q
13 CLK
Circuitry
• Power-Up High-Impedance State
• Buffered Control Inputs Reduce
dc Loading Effects
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic (NT) and Ceramic (JT) 300-mil DIPs
9D 10
10D 11
GND 12
description
These 10-bit edge-triggered D-type flip-flops
feature 3-state outputs designed specifically for
driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for
implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are true to the data (D) input.
A buffered output-enable (OE) input can place the ten outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. The outputs also are in the high-impedance state during power-up and
power-down conditions. The outputs remain in the high-impedance state while the device is powered down. In
the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance
state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54ALS29821 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ALS29821 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
↑
H
L
L
L
L
X
X
X
Q
0
H
Z
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS29821, SN74ALS29821
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS145B – JANUARY 1986 – REVISED JANUARY 1995
†
logic symbol
1
EN
C1
OE
13
CLK
2
23
22
21
20
19
18
17
16
15
1D
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
3
2D
4
3D
5
4D
6
5D
7
6D
8
7D
9
8D
10
9D
11
14
10D
10Q
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
OE
13
CLK
C1
1D
23
2
1Q
1D
To Nine Other Channels
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
I
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, T : SN54ALS29821 . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
A
SN74ALS29821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS29821, SN74ALS29821
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS145B – JANUARY 1986 – REVISED JANUARY 1995
recommended operating conditions
SN54ALS29821
MIN NOM MAX
SN74ALS29821
MIN NOM MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
4.75
2
5
5.25
V
V
CC
High-level input voltage
Low-level input voltage
IH
0.8
–24
48
0.8
–24
48
V
IL
I
I
t
t
t
High-level output current
Low-level output current
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
Operating free-air temperature
mA
mA
ns
ns
ns
°C
OH
OL
w
7
4
7
4
2
0
su
h
2
T
A
–55
125
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS29821
SN74ALS29821
PARAMETER
TEST CONDITIONS
UNIT
V
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
= 4.75 V,
= 4.75 V
I = –18 mA
I
–1.2
–1.2
IK
CC
I
I
I
= –15 mA
= –24 mA
= 48 mA
= 2.4 V
2.4
2
3.3
3.1
2.4
2
3.3
3.1
OH
OH
OL
V
OH
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.75 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
0.35
0.5
50
0.35
0.5
20
V
OL
OZH
OZL
I
I
I
I
I
I
I
I
V
V
µA
µA
mA
µA
mA
mA
mA
O
O
= 0.4 V
–50
0.1
–20
0.1
V = 5.5 V
I
V = 2.7 V
I
20
20
IH
V = 0.4 V
I
–0.5
–250
115
–0.2
–250
115
IL
‡
V
O
= 0
–75
–75
OS
Outputs open
80
80
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS29821, SN74ALS29821
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS145B – JANUARY 1986 – REVISED JANUARY 1995
switching characteristics (see Figure 1)
†
= MIN to MAX ,
V
T
A
CC
= MIN to MAX
†
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
UNIT
SN54ALS29821 SN74ALS29821
MIN
2
MAX
11.5
11.5
21
MIN
2
MAX
10
10
16
16
14
14
20
23
14
12
9
t
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
CLK
CLK
ns
ns
ns
ns
ns
ns
Any Q
Any Q
Any Q
Any Q
Any Q
Any Q
C
= 50 pF
= 300 pF
= 50 pF
= 300 pF
= 50 pF
L
L
L
2
2
2
C
L
2
21
1
17
OE
OE
OE
OE
C
1
17
1
25
C
L
1
29.5
16
1
C
1
14
1
12
C
= 5 pF
L
1
11
9
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS29821, SN74ALS29821
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS145B – JANUARY 1986 – REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
Test Point
V
CC
SWITCH POSITION TABLE
S1
From Output
Under Test
TEST
S1
S2
R
= 180 Ω
L
t
t
Closed
Closed
Open
Closed
Closed
Closed
Closed
Closed
Closed
Open
Closed
Closed
PLH
PHL
PZH
All Diodes
1N916 or 1N3064
R1
1 kΩ
C
L
t
t
(see Note A)
t
PZL
PHZ
S2
t
PLZ
LOAD CIRCUIT
1.5 V
3 V
0
High-Level
Pulse
3 V
1.5 V
1.5 V
1.5 V
Timing Input
0
t
w
t
h
t
su
3 V
0
3 V
0
Low-Level
Pulse
1.5 V
1.5 V
Data Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0
Output
Control
1.5 V
1.5 V
t
PZL
t
PLZ
≈ 4.5 V
≈ 1.5 V
3 V
Input
1.5 V
1.5 V
Waveform 1
(see Note B)
0
1.5 V
t
PHL
t
V
OL
PLH
V
OH
OL
0.5 V
t
In-Phase
Output
PHZ
1.5 V
1.5 V
1.5 V
t
t
PZH
V
V
OH
PLH
t
PHL
Waveform 2
(see Note B)
0.5 V
V
OH
1.5 V
≈ 1.5 V
Out-of-Phase
Output
1.5 V
≈ 0
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
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semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
SN74ALS29821NT
Bus Driver, ALS Series, 1-Func, 10-Bit, True Output, TTL, PDIP24, 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-24
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