SN74ALS29821NT3 [TI]
ALS SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDIP24;
| 型号： | SN74ALS29821NT3 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ALS SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDIP24 驱动 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总11页 (文件大小：247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅ ꢀ ꢆꢇ ꢈ ꢆ ꢉ ꢊꢋ ꢀꢁꢌ ꢃ ꢄ ꢅꢀ ꢆꢇ ꢈꢆ ꢉ
ꢉ ꢍ ꢎꢏꢐ ꢑꢋ ꢏꢒꢀꢎꢐ ꢁꢑ ꢓꢔꢕꢄꢖꢓ ꢋꢕ ꢅꢐ ꢗ ꢎꢕ ꢅꢘ ꢗ ꢀ
ꢙ ꢐꢑ ꢚꢋ ꢛ ꢎꢀꢑꢄꢑ ꢓꢋ ꢘ ꢒꢑ ꢗꢒ ꢑꢀ
SDAS145B − JANUARY 1986 − REVISED JANUARY 1995
SN54ALS29821 . . . JT PACKAGE
SN74ALS29821 . . . DW OR NT PACKAGE
(TOP VIEW)
• Functionally Equivalent to AMD’s AM29821
• Provide Extra Data Width Necessary for
Wider Address/Data Paths or Buses With
Parity
OE
1D
2D
3D
4D
5D
6D
7D
8D
V
CC
1
2
3
4
5
6
7
8
9
24
• Outputs Have Undershoot-Protection
23 1Q
22 2Q
21 3Q
20 4Q
19 5Q
18 6Q
17 7Q
16 8Q
15 9Q
14 10Q
13 CLK
Circuitry
• Power-Up High-Impedance State
• Buffered Control Inputs Reduce
dc Loading Effects
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic (NT) and Ceramic (JT) 300-mil DIPs
9D 10
10D 11
GND 12
description
These 10-bit edge-triggered D-type flip-flops
feature 3-state outputs designed specifically for
driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for
implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are true to the data (D) input.
A buffered output-enable (OE) input can place the ten outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. The outputs also are in the high-impedance state during power-up and
power-down conditions. The outputs remain in the high-impedance state while the device is powered down. In
the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance
state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54ALS29821 is characterized for operation over the full military temperature range of −55°C to 125°C.
The SN74ALS29821 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
↑
D
H
L
H
L
L
↑
L
L
X
X
Q
0
H
X
Z
ꢗ
ꢗ
ꢔ
ꢘ
ꢬ
ꢜ
ꢧ
ꢒ
ꢖ
ꢥ
ꢑ
ꢦ
ꢐ
ꢠ
ꢘ
ꢞ
ꢁ
ꢟ
ꢜ
ꢄ
ꢑ
ꢄ
ꢝ
ꢞ
ꢨ
ꢟ
ꢠ
ꢦ
ꢡ
ꢢ
ꢣ
ꢣ
ꢤ
ꢤ
ꢝ
ꢝ
ꢠ
ꢠ
ꢞ
ꢞ
ꢝ
ꢥ
ꢥ
ꢩ
ꢦ
ꢧ
ꢡ
ꢡ
ꢨ
ꢨ
ꢞ
ꢤ
ꢣ
ꢢ
ꢥ
ꢥ
ꢠ
ꢟ
ꢩ
ꢑꢨ
ꢧ
ꢪ
ꢥ
ꢫ
ꢝ
ꢦ
ꢣ
ꢥ
ꢤ
ꢝ
ꢤ
ꢠ
ꢡ
ꢞ
ꢧ
ꢬ
ꢣ
ꢞ
ꢤ
ꢤ
ꢨ
ꢥ
ꢭ
Copyright 1995, Texas Instruments Incorporated
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ꢨ
ꢡ
ꢤ
ꢮ
ꢤ
ꢨ
ꢡ
ꢠ
ꢟ
ꢯ
ꢣ
ꢐ
ꢞ
ꢢ
ꢨ
ꢥ
ꢤ
ꢣ
ꢞ
ꢬ
ꢣ
ꢡ
ꢬ
ꢰ
ꢣ
ꢤ ꢨ ꢥ ꢤꢝ ꢞꢲ ꢠꢟ ꢣ ꢫꢫ ꢩꢣ ꢡ ꢣ ꢢ ꢨ ꢤ ꢨ ꢡ ꢥ ꢭ
ꢡ
ꢡ
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ꢤ
ꢱ
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ꢗ
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ꢞ
ꢩ
ꢡ
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ꢦ
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ꢥ
ꢝ
ꢞ
ꢲ
ꢬ
ꢠ
ꢨ
ꢥ
ꢞ
ꢠ
ꢤ
ꢞ
ꢨ
ꢦ
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ꢨ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢀꢆ ꢇ ꢈꢆ ꢉ ꢊ ꢋ ꢀꢁ ꢌ ꢃ ꢄꢅ ꢀꢆ ꢇ ꢈ ꢆ ꢉ
ꢉ ꢍꢎ ꢏꢐ ꢑ ꢋ ꢏ ꢒꢀ ꢎꢐ ꢁꢑ ꢓꢔ ꢕꢄꢖ ꢓꢋ ꢕ ꢅꢐ ꢗ ꢎꢕꢅ ꢘ ꢗꢀ
ꢙꢐ ꢑ ꢚ ꢋꢛ ꢎꢀ ꢑꢄꢑꢓ ꢋ ꢘ ꢒꢑ ꢗꢒꢑ ꢀ
SDAS145B − JANUARY 1986 − REVISED JANUARY 1995
†
logic symbol
1
EN
C1
OE
13
CLK
2
23
22
21
20
19
18
17
16
15
1D
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
3
2D
4
3D
5
4D
6
5D
7
6D
8
7D
9
8D
10
9D
11
14
10D
10Q
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
OE
13
CLK
C1
1D
23
2
1Q
1D
To Nine Other Channels
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
I
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, T : SN54ALS29821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
A
SN74ALS29821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁꢂ ꢃ ꢄꢅ ꢀ ꢆꢇ ꢈ ꢆ ꢉ ꢊꢋ ꢀꢁꢌ ꢃ ꢄꢅ ꢀꢆ ꢇꢈ ꢆ ꢉ
ꢉ ꢍ ꢎꢏꢐ ꢑꢋ ꢏꢒꢀꢎꢐ ꢁꢑ ꢓꢔꢕꢄꢖꢓ ꢋꢕ ꢅ ꢐ ꢗꢎ ꢕꢅꢘ ꢗ ꢀ
ꢙ ꢐꢑ ꢚꢋ ꢛ ꢎꢀꢑꢄꢑ ꢓꢋ ꢘ ꢒꢑ ꢗꢒ ꢑꢀ
SDAS145B − JANUARY 1986 − REVISED JANUARY 1995
recommended operating conditions
SN54ALS29821
MIN NOM MAX
SN74ALS29821
MIN NOM MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
4.75
2
5
5.25
V
V
CC
High-level input voltage
Low-level input voltage
IH
0.8
−24
48
0.8
−24
48
V
IL
I
I
t
t
t
High-level output current
Low-level output current
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
Operating free-air temperature
mA
mA
ns
ns
ns
°C
OH
OL
w
7
4
7
4
2
0
su
h
2
T
A
−55
125
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS29821
SN74ALS29821
PARAMETER
TEST CONDITIONS
I = −18 mA
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
IK
V
V
= 4.75 V,
= 4.75 V
−1.2
−1.2
V
CC
I
I
I
I
= −15 mA
= −24 mA
= 48 mA
= 2.4 V
2.4
2
3.3
3.1
2.4
2
3.3
3.1
OH
OH
OL
V
OH
V
CC
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.75 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
0.35
0.5
50
0.35
0.5
20
V
OL
OZH
OZL
I
I
I
I
I
I
I
I
V
V
µA
µA
mA
µA
mA
mA
mA
O
O
= 0.4 V
−50
0.1
−20
0.1
V = 5.5 V
I
V = 2.7 V
I
20
20
IH
V = 0.4 V
I
−0.5
−250
115
−0.2
−250
115
IL
‡
V
O
= 0
−75
−75
OS
Outputs open
80
80
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢀꢆ ꢇ ꢈꢆ ꢉ ꢊ ꢋ ꢀꢁ ꢌ ꢃ ꢄꢅ ꢀꢆ ꢇ ꢈ ꢆ ꢉ
ꢉ ꢍꢎ ꢏꢐ ꢑ ꢋ ꢏ ꢒꢀ ꢎꢐ ꢁꢑ ꢓꢔ ꢕꢄꢖ ꢓꢋ ꢕ ꢅꢐ ꢗ ꢎꢕꢅ ꢘ ꢗꢀ
ꢙꢐ ꢑ ꢚ ꢋꢛ ꢎꢀ ꢑꢄꢑꢓ ꢋ ꢘ ꢒꢑ ꢗꢒꢑ ꢀ
SDAS145B − JANUARY 1986 − REVISED JANUARY 1995
switching characteristics (see Figure 1)
†
= MIN to MAX ,
V
T
A
CC
= MIN to MAX
†
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
UNIT
SN54ALS29821 SN74ALS29821
MIN
2
MAX
11.5
11.5
21
MIN
2
MAX
10
10
16
16
14
14
20
23
14
12
9
t
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
CLK
CLK
OE
ns
ns
ns
ns
ns
ns
Any Q
Any Q
Any Q
Any Q
Any Q
Any Q
C
= 50 pF
= 300 pF
= 50 pF
= 300 pF
= 50 pF
L
L
L
2
2
2
C
L
2
21
1
17
C
1
17
1
25
OE
C
L
1
29.5
16
1
OE
C
1
14
1
12
OE
C = 5 pF
L
1
11
9
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁꢂ ꢃ ꢄꢅ ꢀ ꢆꢇ ꢈ ꢆ ꢉ ꢊꢋ ꢀꢁꢌ ꢃ ꢄꢅ ꢀꢆ ꢇꢈ ꢆ ꢉ
ꢉ ꢍ ꢎꢏꢐ ꢑꢋ ꢏꢒꢀꢎꢐ ꢁꢑ ꢓꢔꢕꢄꢖꢓ ꢋꢕ ꢅ ꢐ ꢗꢎ ꢕꢅꢘ ꢗ ꢀ
ꢙ ꢐꢑ ꢚꢋ ꢛ ꢎꢀꢑꢄꢑ ꢓꢋ ꢘ ꢒꢑ ꢗꢒ ꢑꢀ
SDAS145B − JANUARY 1986 − REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
Test Point
V
CC
SWITCH POSITION TABLE
S1
From Output
Under Test
TEST
S1
S2
R
= 180 Ω
L
t
t
Closed
Closed
Open
Closed
Closed
Closed
Closed
Closed
Closed
Open
Closed
Closed
PLH
PHL
PZH
All Diodes
1N916 or 1N3064
R1
1 kΩ
C
L
t
t
(see Note A)
t
PZL
PHZ
S2
t
PLZ
LOAD CIRCUIT
1.5 V
3 V
0
High-Level
Pulse
3 V
1.5 V
1.5 V
1.5 V
Timing Input
0
t
w
t
h
t
su
3 V
0
3 V
0
Low-Level
Pulse
1.5 V
1.5 V
Data Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0
Output
Control
1.5 V
1.5 V
t
PZL
t
PLZ
≈ 4.5 V
≈ 1.5 V
3 V
Input
1.5 V
1.5 V
Waveform 1
(see Note B)
0
1.5 V
t
PHL
t
V
OL
PLH
V
OH
OL
0.5 V
t
In-Phase
Output
PHZ
1.5 V
1.5 V
1.5 V
t
t
PZH
V
V
OH
PLH
t
PHL
Waveform 2
(see Note B)
0.5 V
V
OH
1.5 V
≈ 1.5 V
Out-of-Phase
Output
1.5 V
≈ 0
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
5962-9061601LA
ACTIVE
CDIP
JT
24
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9061601LA
SNJ54ALS29821J
T
SN74ALS29821DW
SN74ALS29821DWG4
SN74ALS29821NT
SN74ALS29821NTE4
SNJ54ALS29821JT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
PDIP
PDIP
CDIP
DW
DW
NT
NT
JT
24
24
24
24
24
25
25
15
15
1
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
A42
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
0 to 70
0 to 70
ALS29821
Green (RoHS
& no Sb/Br)
ALS29821
Pb-Free
(RoHS)
0 to 70
SN74ALS29821NT
SN74ALS29821NT
Pb-Free
(RoHS)
0 to 70
TBD
-55 to 125
5962-9061601LA
SNJ54ALS29821J
T
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ALS29821, SN74ALS29821 :
Catalog: SN74ALS29821
•
Military: SN54ALS29821
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 2
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
24
28
DIM
13
24
1.280
(32,51) (37,08)
1.460
A MAX
1.240
(31,50) (36,58)
1.440
B
A MIN
B MAX
B MIN
0.300
(7,62)
0.291
(7,39)
1
12
0.070 (1,78)
0.030 (0,76)
0.245
(6,22)
0.285
(7,24)
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.100 (2,54) MAX
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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