SN74ALVCH16952DGVR [TI]
16-Bit Registered Transceiver With 3-State Outputs 56-TVSOP -40 to 85;
| 型号： | SN74ALVCH16952DGVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-Bit Registered Transceiver With 3-State Outputs 56-TVSOP -40 to 85 光电二极管 输出元件 逻辑集成电路 电视 |
| 文件： | 总17页 (文件大小：371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES011E–JULY 1995–REVISED SEPTEMBER 2004
FEATURES
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
•
•
•
Member of the Texas Instruments Widebus™
Family
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
1OEAB
1CLKAB
1CLKENAB
GND
1OEBA
1CLKBA
1CLKENBA
GND
2
3
ESD Protection Exceeds 2000 V Per
4
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
5
1A1
1B1
6
1A2
1B2
•
•
•
Latch-Up Performance Exceeds 500 mA Per
JESD 17
7
V
CC
V
CC
8
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
9
10
11
12
13
14
15
16
17
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21
22
23
24
25
26
27
28
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
DESCRIPTION
This 16-bit registered transceiver is designed for
1.65-V to 3.6-V VCC operation.
The SN74ALVCH16952 contains two sets of D-type
flip-flops for temporary storage of data flowing in
either direction. This device can be used as two 8-bit
transceivers or one 16-bit transceiver. Data on the A
or B bus is stored in the registers on the low-to-high
transition of the clock (CLKAB or CLKBA) input,
provided that the clock-enable (CLKENAB or
CLKENBA) input is low. Taking the output-enable
(OEAB or OEBA) input low accesses the data on
either port.
V
CC
V
CC
2A7
2A8
2B7
2B8
GND
GND
2CLKENAB
2CLKAB
2OEAB
2CLKENBA
2CLKBA
2OEBA
To ensure the high-impedance state during power up
or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16952 is characterized for operation from -40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES011E–JULY 1995–REVISED SEPTEMBER 2004
FUNCTION TABLE(1)
INPUTS
OUTPUT
B
CLKENAB
CLKAB
OEAB
A
X
X
L
(2)
H
X
L
X
L
↑
L
L
L
L
H
B0
(2)
B0
L
H
Z
L
↑
H
X
X
X
(1) A-to-B data flow is shown; B-to-A data flow is similar, but uses
CLKENBA, CLKBA, and OEBA.
(2) Level of B before the indicated steady-state input conditions were
established
2
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES011E–JULY 1995–REVISED SEPTEMBER 2004
LOGIC SYMBOL(1)
56
1OEBA
EN3
54
55
1
G1
1CLKENBA
1CLKBA
1C5
EN4
1OEAB
3
G2
1CLKENAB
1CLKAB
2
2C6
EN9
29
2OEBA
31
30
28
G7
2CLKENBA
2CLKBA
7C11
EN10
2OEAB
26
27
G8
2CLKENAB
2CLKAB
8C12
5
52
1A1
3
5D
4
1B1
6D
6
51
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
1B2
49
8
1B3
48
9
1B4
47
10
12
13
14
15
1B5
45
1B6
44
1B7
43
1B8
42
9
11D
10
2B1
12D
16
17
19
20
21
23
24
41
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2B2
40
2B3
38
2B4
37
2B5
36
2B6
34
2B7
33
2B8
(1)
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
3
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES011E–JULY 1995–REVISED SEPTEMBER 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
3
54
1CLKENAB
1CLKAB
1OEBA
1CLKENBA
2
55
1
1CLKBA
1OEAB
56
One of Eight
Channels
C1
CE
1D
52
5
1B1
1A1
C1
CE
1D
To Seven Other Channels
26
27
29
31
30
28
2CLKENBA
2CLKBA
2CLKENAB
2CLKAB
2OEBA
2OEAB
One of Eight
Channels
C1
CE
1D
42
15
2B1
2A1
C1
CE
1D
To Seven Other Channels
4
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES011E–JULY 1995–REVISED SEPTEMBER 2004
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
-0.5
-0.5
MAX
4.6
UNIT
VCC
VI
Supply voltage range
Input voltage range
V
Except I/O ports(2)
I/O ports(2)(3)
4.6
V
-0.5 VCC + 0.5
VO
IIK
Output voltage range(2)(3)
Input clamp current
-0.5 VCC + 0.5
V
VI < 0
-50
-50
±50
±100
81
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through each VCC or GND
DGG package
DGV package
DL package
θJA
Package thermal impedance(4)
86
°C/W
74
Tstg
Storage temperature range
-65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51.
RECOMMENDED OPERATING CONDITIONS(1)
MIN
MAX UNIT
VCC
Supply voltage
1.65
3.6
V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
0.65 × VCC
VIH
High-level input voltage
1.7
2
V
0.35 × VCC
0.7
0.8
VCC
VCC
-4
VIL
Low-level input voltage
V
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
-12
-12
-24
4
IOH
High-level output current
Low-level output current
mA
mA
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
12
IOL
12
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
10
ns/V
TA
-40
85
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES011E–JULY 1995–REVISED SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP(1) MAX UNIT
IOH = -100 µA
IOH = -4 mA
IOH = -6 mA
1.65 V to 3.6 V VCC - 0.2
1.65 V
2.3 V
1.2
2
VOH
2.3 V
1.7
2.2
2.4
2
V
IOH = -12 mA
2.7 V
3 V
IOH = -24 mA
IOL = 100 µA
IOL = 4 mA
IOL = 6 mA
3 V
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.4
V
VOL
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
VI = VCC or GND
VI = 0.58 V
3 V
0.55
II
3.6 V
±5
µA
µA
1.65 V
1.65 V
2.3 V
25
-25
45
VI = 1.07 V
VI = 0.7 V
II(hold)
VI = 1.7 V
2.3 V
-45
75
VI = 0.8 V
3 V
VI = 2 V
3 V
-75
VI = 0 to 3.6 V(2)
VO = VCC or GND
VI = VCC or GND,
3.6 V
±500
±10
40
(3)
IOZ
3.6 V
µA
µA
µA
pF
pF
ICC
∆ICC
Ci
IO = 0
3.6 V
One input at VCC - 0.6 V,
Other inputs at VCC or GND
3 V to 3.6 V
3.3 V
750
Control inputs VI = VCC or GND
3.5
8.5
Cio A or B ports
VO = VCC or GND
3.3 V
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 1.8 V
VCC = 2.7 V
UNIT
MIN MAX MIN MAX MIN
MAX MIN MAX
(1)
fclock
tw
Clock frequency
Pulse duration
150
150
150
MHz
ns
(1)
CLKEN high
3.3
3.3
1.7
1.2
0.6
1.1
3.3
3.3
1.9
1
3.3
3.3
1.5
1
(1)
(1)
(1)
(1)
(1)
CLK high or low
Data before CLK
CLKEN before CLK
Data after CLK
CLKEN after CLK
tsu
Setup time
Hold time
ns
ns
0.6
0.9
0.8
1.1
th
(1) This information was not available at the time of publication.
6
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES011E–JULY 1995–REVISED SEPTEMBER 2004
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 1.8 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
TYP
MIN
150
1
MAX
MIN
MAX
MIN
150
1
MAX
(1)
fmax
tpd
150
MHz
ns
(1)
(1)
(1)
CLK
A or B
A or B
A or B
4.1
5.4
5.3
4.6
5.3
4.4
3.9
4.4
4
ten
OEBA or OEAB
OEBA or OEAB
1
1
ns
tdis
1
1.1
ns
(1) This information was not available at the time of publication.
OPERATING CHARACTERISTICS
TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
53
TYP
71
(1)
Outputs enabled
Outputs disabled
Power dissipation
capacitance
Cpd
CL = 0,
f = 10 MHz
pF
(1)
34
40
(1) This information was not available at the time of publication.
7
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES011E–JULY 1995–REVISED SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V
2 × V
CC
S1
Open
1 kΩ
From Output
Under Test
TEST
S1
GND
t
pd
Open
C = 30 pF
(see Note A)
L
t
/t
/t
2 × V
CC
GND
PLZ PZL
1 kΩ
t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
CC
V /2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.15 V
CC
V
OL
(see Note B)
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− 0.15 V
V /2
CC
Output
V /2
CC
V /2
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 1. Load Circuit and Voltage Waveforms
8
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES011E–JULY 1995–REVISED SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × V
CC
S1
Open
GND
500 Ω
From Output
Under Test
TEST
S1
t
pd
Open
C = 30 pF
(see Note A)
L
t
/t
/t
2 × V
CC
GND
PLZ PZL
500 Ω
t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
CC
V /2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.15 V
CC
V
OL
(see Note B)
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− 0.15 V
V /2
CC
Output
V /2
CC
V /2
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 2. Load Circuit and Voltage Waveforms
9
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES011E–JULY 1995–REVISED SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6 V
TEST
S1
S1
500 Ω
Open
From Output
Under Test
t
pd
Open
6 V
GND
GND
t
t
/t
PLZ PZL
C = 50 pF
L
/t
PHZ PZH
500 Ω
(see Note A)
t
w
LOAD CIRCUIT
2.7 V
0 V
1.5 V
1.5 V
Input
2.7 V
Timing
Input
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
2.7 V
Data
Input
Output
Control
(low-level
enabling)
1.5 V
1.5 V
2.7 V
0 V
0 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
S1 at 6 V
3 V
+ 0.3 V
2.7 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
OL
V
OL
(see Note B)
t
t
PHZ
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
OH
V
OH
− 0.3 V
1.5 V
Output
1.5 V
1.5 V
0 V
(see Note B)
V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 3. Load Circuit and Voltage Waveforms
10
PACKAGE OPTION ADDENDUM
www.ti.com
24-May-2007
PACKAGING INFORMATION
Orderable Device
74ALVCH16952DGGRG4
74ALVCH16952DGVRE4
74ALVCH16952DGVRG4
74ALVCH16952DLG4
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
56
56
56
56
56
56
56
56
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
TVSOP
SSOP
DGV
DGV
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
74ALVCH16952DLRG4
SN74ALVCH16952DGGR
SN74ALVCH16952DGVR
SN74ALVCH16952DL
SN74ALVCH16952DLR
SSOP
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TVSOP
SSOP
DGG
DGV
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN74ALVCH16952DGGR TSSOP
SN74ALVCH16952DGVR TVSOP
DGG
DGV
DL
56
56
56
2000
2000
1000
330.0
330.0
330.0
24.4
24.4
32.4
8.6
6.8
15.6
11.7
1.8
1.6
3.1
12.0
12.0
16.0
24.0
24.0
32.0
Q1
Q1
Q1
SN74ALVCH16952DLR
SSOP
11.35
18.67
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74ALVCH16952DGGR
SN74ALVCH16952DGVR
SN74ALVCH16952DLR
TSSOP
TVSOP
SSOP
DGG
DGV
DL
56
56
56
2000
2000
1000
346.0
346.0
346.0
346.0
346.0
346.0
41.0
41.0
49.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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