SN74AUC74RGYR [TI]
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET; 双上升沿触发的D型触发器具有清零和预设
| 型号： | SN74AUC74RGYR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET |
| 文件： | 总7页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AUC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCES483 – AUGUST 2003
RGY PACKAGE
(TOP VIEW)
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
I
Supports Partial-Power-Down Mode
off
Operation
1
14
Sub 1-V Operable
1D
1CLK
1PRE
1Q
13 2CLR
12 2D
2
3
4
5
6
Max t of 1.8 ns at 1.8-V
pd
Low Power Consumption, 10-µA Max I
11
10
9
2CLK
2PRE
2Q
CC
8-mA Output Drive at 1.8 V
1Q
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
7
8
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
Thisdualpositive-edge-triggeredD-typeflip-flopisoperationalat0.8-Vto2.7-VV ,butisdesignedspecifically
CC
for 1.65-V to 1.95-V V
operation.
CC
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop
for higher frequencies, the CLR input overrides the PRE input when they are both low.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
–40°C to 85°C QFN – RGY
Tape and reel
SN74AUC74RGYR
MS74
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
L
CLR
CLK
X
D
X
X
H
L
Q
H
L
Q
L
H
L
X
X
H
L
H
H
H
H
↑
H
L
H
↑
H
H
L
X
Q
Q
0
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCES483 – AUGUST 2003
logic diagram, each flip-flop (positive logic)
PRE
C
CLK
C
C
Q
TG
C
C
C
C
D
TG
TG
TG
Q
C
C
C
CLR
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V + 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Continuous current through V
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
JA
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-5.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCES483 – AUGUST 2003
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
V
Supply voltage
0.8
2.7
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0.8 V
V
CC
V
High-level input voltage
= 1.1 V to 1.95 V
= 2.3 V to 2.7 V
= 0.8 V
0.65 × V
V
V
CC
1.7
0
0.35 × V
0.7
V
IL
Low-level input voltage
= 1.1 V to 1.95 V
= 2.3 V to 2.7 V
CC
V
V
Input voltage
0
0
3.6
V
V
I
Output voltage
V
CC
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0.8 V
= 1.1 V
= 1.4 V
= 1.65 V
= 2.3 V
= 0.8 V
= 1.1 V
= 1.4 V
= 1.65 V
= 2.3 V
–0.7
–3
–5
–8
–9
0.7
3
I
High-level output current
Low-level output current
mA
mA
OH
OL
I
5
8
9
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
20
85
ns/V
T
A
–40
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN
V –0.1
CC
TYP
MAX
UNIT
V
CC
I
I
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –0.7 mA
= –3 mA
= –5 mA
= –8 mA
= –9 mA
= 100 µA
= 0.7 mA
= 3 mA
0.8 V to 2.7 V
0.8 V
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
0.55
1.1 V
0.8
1
V
OH
V
1.4 V
1.65 V
2.3 V
1.2
1.8
0.8 V to 2.7 V
0.8 V
0.2
0.25
1.1 V
0.3
0.4
0.45
0.6
5
V
OL
V
= 5 mA
1.4 V
= 8 mA
1.65 V
2.3 V
= 9 mA
I
I
I
V = V or GND
CC
0 to 2.7 V
0
µA
µA
µA
I
I
V or V = 2.7 V
10
off
I
O
V = V
or GND,
or GND
I = 0
O
0.8 V to 2.7 V
2.5 V
10
CC
I
CC
CC
D inputs
V = V
2
I
C
pF
i
Control inputs V = V
or GND
2.5 V
2.5
I
CC
†
All typical values are at T = 25°C.
A
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCES483 – AUGUST 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
V = 1.2 V
CC
0.1 V
V = 1.5 V
CC
0.1 V
V = 1.8 V
CC
0.15 V
V = 2.5 V
CC
0.2 V
V
CC
= 0.8 V
UNIT
TYP
MIN MAX
225
MIN MAX
250
MIN MAX
300
MIN MAX
350
f
t
Clock frequency
100
4.6
6.6
4.8
2.3
0
MHz
clock
CLK high or low
CLR low
1.3
2
0.6
1.5
1.5
0.6
0
0.5
1.5
1.5
0.6
0
0.5
1.5
1.5
0.7
0.3
0.3
0.3
Pulse
duration
ns
w
PRE low
1.8
1
Data
Setup time
before CLK↑
t
t
CLR inactive
PRE inactive
0
ns
ns
su
0
0
0
0.2
0.3
Hold time, data after CLK↑
2.1
0.3
0.3
h
switching characteristics over recommended operating free-air temperature range, C = 15 pF
L
(unless otherwise noted) (see Figure 1)
V
= 1.2 V
V
= 1.5 V
V
= 1.8 V
V
= 2.5 V
CC
0.1 V
CC
0.1 V
CC
0.15 V
CC
0.2 V
V
CC
= 0.8 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
MIN MAX
MIN MAX
MIN TYP MAX
MIN MAX
f
100
9.5
225
250
300
350
MHz
max
CLK
CLR
PRE
1.3
1.5
1.6
4
4.1
4.7
0.7
1.1
1.1
2.5
2.9
2.8
0.5
0.9
0.9
1.2
1.4
1.4
2.1
2.4
2.4
0.5
0.7
0.7
1.4
1.6
1.6
t
pd
10.5
12
ns
Q or Q
switching characteristics over recommended operating free-air temperature range, C = 30 pF
L
(unless otherwise noted) (see Figure 1)
V
= 1.8 V
V
= 2.5 V
CC
0.15 V
CC
0.2 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN TYP MAX
MIN MAX
f
300
350
MHz
max
CLK
CLR
PRE
1.2
1.3
1.3
1.9
2.1
2.1
2.8
3
1
1.1
1.1
2.2
2.4
2.5
t
pd
ns
Q or Q
3.1
operating characteristics, T = 25°C
A
V
= 0.8 V
CC
TYP
V
= 1.2 V
CC
TYP
V
CC
= 1.5 V
V
CC
= 1.8 V
V
CC
= 2.5 V
TEST
PARAMETER
UNIT
CONDITIONS
TYP
TYP
TYP
Power dissipation
capacitance
C
f = 10 MHz
36
36
36
37
41
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCES483 – AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
TEST
S1
S1
R
L
t
t
/t
Open
From Output
Under Test
PLH PHL
t
/t
2 × V
CC
GND
PLZ PZL
/t
PHZ PZH
C
L
R
L
(see Note A)
V
∆
C
L
R
V
CC
L
0.8 V
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
0.1 V
0.1 V
15 pF
1.2 V 0.1 V
1.5 V 0.1 V
1.8 V 0.15 V
2.5 V 0.2 V
1.8 V 0.15 V
2.5 V 0.2 V
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
LOAD CIRCUIT
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
V
CC
Timing Input
V
CC
/2
0 V
t
w
t
t
h
su
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
V
CC
/2
V
CC
/2
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
Input
0 V
0 V
t
t
t
t
t
PHL
/2
PZL
PLZ
+ V
PLH
PHL
Output
Waveform 1
V
V
V
V
OH
CC
V
/2
/2
V
V
/2
/2
V
CC
Output
CC
CC
S1 at 2 × V
(see Note B)
V
V
CC
OL
∆
OL
OL
t
t
t
PLH
/2
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– V
OH
∆
V
CC
V
CC
CC
Output
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, slew rate ≥ 1 V/ns.
O
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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