SN74AVC16245DGG [TI]
16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS; 具有三态输出的16位总线收发器
| 型号： | SN74AVC16245DGG |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS |
| 文件： | 总11页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUARY 2000
Member of the Texas Instruments
Widebus Family
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
I
Supports Partial-Power-Down Mode
off
Operation
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Latch-Up Performance Exceeds 250 mA Per
JESD 78
Less Than 2-ns Maximum Propagation
Delay at 2.5-V and 3.3-V V
CC
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
Dynamic Drive Capability Is Equivalent to
Standard Outputs With I and I of
OH
OL
±24 mA at 2.5-V V
CC
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical V vs I and V
vs I
curves to illustrate the output impedance and drive capability of the
OL
OL
OH
OH
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )
Circuitry Technology and Applications, literature number SCEA009.
3.2
T
= 25°C
T
= 25°C
A
A
Process = Nominal
Process = Nominal
2.8
2.4
2.0
2.8
2.4
2.0
V
= 3.3 V
CC
1.6
1.2
0.8
0.4
1.6
1.2
0.8
0.4
V
= 2.5 V
CC
V
= 1.8 V
CC
V
= 3.3 V
V
= 2.5 V
CC
CC
V
= 1.8 V
CC
–160 –144 –128 –112 –96 –80 –64 –48 –32 –16
– Output Current – mA
0
17
34
51
68
85 102 119 136 153 170
0
I
– Output Current – mA
I
OH
OL
Figure 1. Output Voltage vs Output Current
This 16-bit (dual octal) noninverting bus transceiver is operational at 1.2-V to 3.6-V V , but is designed
CC
specifically for 1.65-V to 3.6-V V
operation.
CC
The SN74AVC16245 is designed for asynchronous communication between data buses. The control-function
implementation minimizes external timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the
A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUARY 2000
description (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16245 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
2
3
4
5
6
7
V
V
CC
CC
8
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V
V
CC
CC
2B5
2B6
GND
2B7
2B8
2A5
2A6
GND
2A7
2A8
2OE
2DIR
FUNCTION TABLE
(each 8-bit transceiver)
INPUTS
OPERATION
OE
DIR
L
L
L
B data to A bus
A data to B bus
Isolation
H
H
X
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUARY 2000
†
logic symbol
48
1
G3
1OE
1DIR
3 EN1 [BA]
3 EN2 [AB]
25
24
G6
2OE
2DIR
6 EN4 [BA]
6 EN5 [AB]
47
2
1
1A1
1B1
2
46
44
43
41
40
38
37
36
3
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
1B2
5
1B3
6
1B4
8
1B5
9
1B6
11
1B7
12
1B8
13
4
2B1
5
35
33
32
30
29
27
26
14
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2B2
16
2B3
17
2B4
19
2B5
20
2B6
22
2B7
23
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
24
36
1
2DIR
2A1
1DIR
48
25
1OE
1B1
2OE
47
1A1
13
2
2B1
To Seven Other Channels
To Seven Other Channels
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUARY 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
Voltage range applied to any input/output
when the output is in the high-impedance or power-off state, V (see Note 1) . . . . . . . . . . –0.5 V to 4.6 V
O
Voltage range applied to any input/output
when the output is in the high or low state, V (see Notes 1 and 2) . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each V
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
MIN
1.4
MAX
UNIT
Operating
3.6
V
Supply voltage
V
CC
IH
Data retention only
1.2
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.2 V
V
CC
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 1.2 V
0.65 × V
CC
V
High-level input voltage
0.65 × V
V
V
CC
1.7
2
GND
0.35 × V
0.35 × V
0.7
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
CC
CC
V
IL
Low-level input voltage
0.8
V
V
Input voltage
0
0
0
3.6
V
V
I
Active state
3-state
V
CC
3.6
Output voltage
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
–2
–4
–8
†
I
Static high-level output current
mA
mA
OHS
OLS
–12
2
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
4
†
I
Static low-level output current
8
12
5
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
= 1.4 V to 3.6 V
ns/V
T
–40
85
°C
A
†
Dynamic drive capability is equivalent to standard outputs with I
OH
and I
of ±24 mA at 2.5-V V . See Figure 1 for V
CC
vs I
and
OL
OL
OL
V
vs I
characteristics. Refer to the TI application reports, AVC Logic Family TechnologyandApplications, literaturenumberSCEA006,
OH
and Dynamic Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at V or GND to ensure proper device operation. Refer to the TI application report,
OH
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
= –100 µA
MIN TYP
V –0.2
CC
MAX
UNIT
V
CC
I
I
I
I
I
I
I
I
I
I
1.4 V to 3.6 V
1.4 V
OHS
OHS
OHS
OHS
OHS
OLS
OLS
OLS
OLS
OLS
= –2 mA,
= –4 mA,
= –8 mA,
= –12 mA,
= 100 µA
= 2 mA,
V
V
V
V
= 0.91 V
= 1.07 V
= 1.7 V
= 2 V
1.05
1.2
IH
IH
IH
IH
V
1.65 V
2.3 V
V
OH
OL
1.75
2.3
3 V
1.4 V to 3.6 V
1.4 V
0.2
0.4
V
IL
V
IL
V
IL
V
IL
= 0.49 V
= 0.57 V
= 0.7 V
= 0.8 V
V
= 4 mA,
1.65 V
2.3 V
0.45
0.55
0.7
V
= 8 mA,
= 12 mA,
3 V
I
I
I
I
Control inputs
V = V or GND
CC
3.6 V
±2.5
±10
±12.5
40
µA
µA
µA
µA
I
I
V or V = 3.6 V
0
off
I
O
‡
V
O
= V
or GND,
V (OE)= V
CC
3.6 V
OZ
CC
I
V = V
or GND,
I = 0
O
3.6 V
CC
I
CC
CC
2.5 V
3
3
9
9
C
C
Control inputs
A or B ports
V = V
I
or GND
pF
pF
i
3.3 V
2.5 V
V
O
= V
or GND
CC
io
3.3 V
†
‡
Typical values are measured at T = 25°C.
A
For I/O ports, the parameter I
OZ
includes the input leakage current.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
V
= 1.5 V
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
CC
± 0.1 V
CC
± 0.15 V
CC
± 0.2 V
CC
± 0.3 V
V
CC
= 1.2 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
t
t
A or B
OE
B or A
A or B
A or B
3.9
8.4
8.4
0.8
4
0.7
3
0.6
1.9
0.5
1.7
ns
ns
ns
pd
en
dis
1.5
2.3
9.2
9.3
1.4
2.2
7
7
1
4.3
4
0.7
1.2
3.7
3.9
1.1
OE
operating characteristics, T = 25°C
A
V
= 1.8 V
CC
TYP
V
CC
= 2.5 V
V = 3.3 V
CC
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
Outputs enabled
Outputs disabled
35
6
38
6
44
7
Power dissipation
capacitance
C
C
= 0,
L
f = 10 MHz
pF
pd
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
= 1.2 V AND 1.5 V ± 0.1 V
CC
2 × V
CC
Open
S1
2 kΩ
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
2 kΩ
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V
CC
/2
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
+ 0.1 V
OL
CC
V
0 V
OL
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
– 0.1 V
V
CC
/2
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 2. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
= 1.8 V ± 0.15 V
V
CC
2 × V
CC
Open
S1
1 kΩ
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
1 kΩ
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 3. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 4. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
= 3.3 V ± 0.3 V
V
CC
2 × V
CC
S1
TEST
S1
500 Ω
Open
From Output
Under Test
t
Open
pd
/t
GND
t
2 × V
CC
GND
PLZ PZL
/t
C
= 30 pF
L
t
PHZ PZH
500 Ω
(see Note A)
t
LOAD CIRCUIT
w
V
CC
V
CC
/2
V
CC
/2
Input
V
CC
Timing
Input
0 V
V
/2
CC
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Data
Input
V
CC
/2
V
CC
/2
V
CC
Output
0 V
Control
(low-level
enabling)
V
CC
/2
V
CC
/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
0 V
t
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
/2
V
+ 0.3 V
S1 at 2 × V
(see Note B)
CC
OL
CC
V
OL
0 V
t
t
t
PZH
PLH
PHL
/2
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
OH
V
– 0.3 V
OH
V
/2
CC
V
CC
/2
V
Output
CC
0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 5. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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