SN74BCT2420FNR [TI]
NuBus ADDRESS/DATA TRANSCEIVERS AND REGISTERS; NuBus总线地址/数据收发器和寄存器
| 型号： | SN74BCT2420FNR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | NuBus ADDRESS/DATA TRANSCEIVERS AND REGISTERS |
| 文件： | 总12页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74BCT2420
NuBus ADDRESS/DATA TRANSCEIVERS AND REGISTERS
SDIS007A – D3159, NOVEMBER 1988 – REVISED JANUARY 1989
FN PACKAGE
(TOP VIEW)
• Designed for NuBus Interface
Applications
• Conforms to ANSI/IEEE Std 1196-1987
• On-Chip Comparator Provides I/D Slot
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
Identification
AEN 10
ID0
ALE
IDEQ
ACLK 11
ID3 12
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
• Multiplexed Real-Time and Latched
Address/Data
SSEQ 13
AD7 14
AD6 15
AD5 16
AD4 17
V
CC
• Designed to Operate With SN74ACT2440
AD15
AD14
AD13
AD12
GND
AD11
AD10
AD9
NuBus Controller
• BiCMOS Design Substantially Reduces
Standby Current
18
19
20
21
22
23
24
25
26
GND
AD3
AD2
AD1
AD0
• Dependable Texas instruments Quality and
Reliability
AD8
ID1
ADEN
DCLK
ID2
description
V
CC
A/D
DLE
DEN
The ’BCT2420 consists of bus transceiver circuits,
D-type flip-flops, latches, and control circuitry
arranged for multiplexed transmission of address
and data information in NuBus applications. An
on-chip comparator has been included to detect
when a NuBus transfer cycle is requesting the
local board. The device conforms to ANSI/IEEE
Std 1196-1987 and operates with Texas instru-
27 28 29 30 31 32 33 34 3536 37 38 39 40 41 42 43
ments SN74ACT2440 NuBus
Controller. In
addition, the device is easily configured around
ASIC or other PAL -based controllers.
The ’BCT2420 was designed using Texas Instruments BiCMOS process, which features bipolar drive
characteristics and greatly reduces the standby power of the device when disabled. This feature is especially
valuable when the device is not performing a NuBus transaction.
The AEN, DEN and ADEN inputs control the transceiver functions. Three 16-bit I/O ports, A15–A0, D15–D0,
and AD15–AD0, provide for address and data transfer. When the NuBus performs a write cycle to the local
board, address information is saved on the rising edge of ACLK. During the last portion of the NuBus write
cycle, data information is saved on the rising edge of DCLK.
When the local board is performing a write to the NuBus , address and data is multiplexed onto the NuBus
via the A/D line. Address and data can be latched by using the ALE and DLE input lines respectively.
The IDEQ output is used to signal that the local board is being requested by the NuBus . This output is typically
fedtotheNuBus controller. IDEQgoesactive(low)whenAD15–AD12arelowandAD11–AD8matchID3–ID0.
IDEQ stays valid until the next address clock (ACLK) occurs. Internal 10-kΩ pullup resistors are included on the
ID3–ID0 inputs.
The SSEQ output is used to signal the local board that super-slot addresses are being requested. This output
is active (low) whenever AD15–AD12 are equal to ID3–AD0, except when ID3–ID0 are all low.
In typical NuBus applications, two devices are required to provide the full 32-bit address/data path. Refer to
the typical NuBus interface diagram on page 9 for additional information.
The SN74BCT2420 is characterized for operation from 0°C to 70°C.
NuBus is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Monolithic Memories Inc.
Copyright 1989, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2420
NuBus ADDRESS/DATA TRANSCEIVERS AND REGISTERS
SDIS007A – D3159, NOVEMBER 1988 – REVISED JANUARY 1989
Function Tables
INPUTS
OUTPUTS
A15–A0 D15–D0
ALE
L
DLE
X
A/D
L
ADEN
AD15–AD0
H
L
X
X
X
H
L
L
L
L
L
L
L
H
L
L
X
L
H
X
X
X
X
X
H
X
L
Q
O
L
X
L
H
H
H
X
X
L
H
X
X
X
H
Q
O
Z
X
X
INPUTS
OUTPUTS
AD15–AD0
ACLK, DCLK
AEN, DEN
A15–A0, D15–DO
H
L
↑
↑
L
L
L
H
X
X
L
X
L
Q
O
L
H
AD15–AD12
AD11–AD8
IDEQ
AD15–AD12
ID3–ID0
SSEQ
EQ ID3–ID0
NE ID3–ID0
X
L
H
H
EQ 0
X
NE 0
NE 0
X
EQ 0
L
H
H
EQ ID3–ID0
NE ID3–ID0
X
NOTE: Symbol ‘Q ’ denotes previous logic state preserved. Symbol ‘Z’ denotes high-impedance state.
O
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2420
NuBus ADDRESS/DATA TRANSCEIVERS AND REGISTERS
SDIS007A – D3159, NOVEMBER 1988 – REVISED JANUARY 1989
†
logic symbol
φ
60
ADDR/DATA XCVR/REG
ID0
0
3
SN74BCT2420
47
44
13
58
ID1
ID2
SSEQ
IDEQ
SSEQ
IDEQ
ID
12
ID3
10
9
AEN
A0
AEN
0
8
7
A1
A2
6
A3
5
4
A4
A5
3
2
A6
A7
ADDR
68
67
A8
A9
22
0
AD0
AD1
66
21
A10
65
64
63
20
19
AD2
AD3
A11
A12
A13
17
16
15
AD4
AD5
AD6
62
61
A14
A15
15
14
48
AD7
AD8
11
26
ADDR/DATA
ACLK
DEN
ACLK
DEN
49
50
AD9
27
AD10
D0
0
28
29
51
53
54
AD11
AD12
AD13
D1
D2
30
31
D3
D4
55
56
AD14
AD15
32
15
D5
33
34
36
D6
D7
D8
DATA
37
D9
38
39
D10
D11
40
D12
41
42
43
D13
D14
D15
15
45
DCLK
DCLK
59
25
ALE
ALE
DLE
DLE
24
ADDR
A/D
DATA
ADEN
46
ADEN
†
This symbol is in accordance with ANSI/IEEE Std. 91-1984.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2420
NuBus ADDRESS/DATA TRANSCEIVERS AND REGISTERS
SDIS007A – D3159, NOVEMBER 1988 – REVISED JANUARY 1989
logic diagram
4
4
4
ID3–ID0
SSEQ
IDEQ
4 x
4
4
4 x
4
A’11-A’8
A’15-A’12
ACLK
AEN
C1
4 x
4 x
8 x
4
4
8
4
4
8
4
4
8
A15–A12
1D
1D
1D
AD15–AD12
AD11–AD8
AD7–AD0
A11–A8
A7–A0
DCLK
16
C1
16
16
16 x
16
16
D15–D0
DEN
1D
ALE
MUX
C1
1D
16 x
16 x
16
16
1
DLE
C1
1D
16
1
A/D
G1
ADEN
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2420
NuBus ADDRESS/DATA TRANSCEIVERS AND REGISTERS
SDIS007A – D3159, NOVEMBER 1988 – REVISED JANUARY 1989
Terminal Functions
PIN NAME
DESCRIPTION
A15–A0
Address bus. This 16-bit I/O port is connected to the local board’s address bus. When information is transferred between this
port and the NuBus port (AD15–AD0), the data is inverted to conform to NuBus specifications.
ACLK
A/D
Address clock. This input saves the address portion of NuBus read or write cycles. Data present at the AD15–AD0 inputs
is clocked into the address register on the low-to-high transition of ACLK.
Address/data select. This input controls the address/data multiplexer. When A/D is driven low, the local address port, A15–A0,
is selected as input to the AD15–AD0 outputs. When A/D is taken high, the local data port, D15–D0, is selected as input to the
AD15–AD0 outputs.
AD15–AD0
ADEN
AEN
Address/data port. This 16-bit active-low I/O port directly interfaces to the NuBus address/data lines. These lines are
multiplexed to carry address information at the beginning of a NuBus cycle and data information later in the cycle.
Address/data output enable. This active-low input enables the AD15–AD0 outputs. When ADEN is taken high, the AD15–AD0
outputs are in the high impedance state, allowing input from the NuBus
.
Address enable. This active-low input enables the local address outputs. A15–A0, to place data onto the local board. When
AEN is taken high, the A15–A0 outputs are in the high-impedance state, allowing input from the local address bus.
ALE
Address latch enable. This active-low input controls the latch that holds the address received from the local address bus,
A15–A0.WhenALEislow, thelatchistransparent. WhenALEistakenhigh, theaddresspresentattheA15–A0inputsislatched
and remains latched while ALE is held high.
D15–D0
DCLK
DEN
Data bus. This 16-bit I/O port is connected to the local board’s data bus. When information is transferred between this port and
the NuBus port (AD15–AD0), the data is inverted to conform to NuBus specifications.
Data clock. This input saves the data portion of NuBus write cycles. Data present at the AD15–AD0 inputs is clocked into
the data register on the low-to-high transition of DCLK.
Data enable. This active-low input enables the local data port outputs, D15–D0, to place data onto the local board. When DEN
is taken high, the D15–D0 outputs are in the high-impedance state, allowing input from the local board.
DLE
Data latch enable. This active-low input controls the latch that holds the data received from the local data bus, D15–D0. When
DLE is low, the latch is transparent. When DLE is taken high, the data present at the D15–D0 inputs is latched and remains
latched while DLE is held high.
ID3–ID0
IDEQ
Card-slot identification. These four inputs accept binary-coded location information for each NuBus slot position on the
backplane. These four lines are typically hard wired logic levels unique to each NuBus slot connector. For convenient
implementation, the inputs have internal 10-kΩ pull up resistors that ensure the logic high level when the inputs are left open
circuited. The internal comparator uses these inputs to identify when the local hardware card is being accessed.
Identification equal. This active-low output is used to signal that the board is being accessed by the NuBus . IDEQ goes low
whenever AD15–AD12 are low and AD11–AD8 match ID3–ID0. Since the internal comparator uses data from the address
register, the address register must be clocked before the local board samples IDEQ. IDEQ is valid for the entire NuBus cycle
after ACLK.
SSEQ
Super-slot equal. This active-low output is used to signal the local board that super-slot addresses are being requested in the
super-slotmode. SSEQ goes low when AD15–AD12 match ID3–ID0 and ID3–ID0 are not all low. Since the internal comparator
uses data from the address register, the address register must be clocked before the local board samples SSEQ. SSEQ is valid
for the entire NuBus cycle after ACLK.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2420
NuBus ADDRESS/DATA TRANSCEIVERS AND REGISTERS
SDIS007A – D3159, NOVEMBER 1988 – REVISED JANUARY 1989
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (all inputs and I/O ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
PARAMETER
MIN NOM
MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
V
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
0.8
–15
2.6
24
Ax, Dx, ADx outputs
I
High-level input current
mA
OH
SSEQ, IDEQ outputs
Ax, Dx, ADx outputs
SSEQ, IDEQ outputs
I
f
Low-level input current
Clock frequency
mA
OL
16
0
12.5
12.5
12.5
5
40
MHz
clock
ACLK, DCLK high
ACLK, DCLK low
ALE, DLE low
t
w
t
su
t
h
Pulse duration
Setup time
ns
ns
ADx before ACLK↑, DCLK↑
Ax before ALE↑
5
Dx before DLE↑
5
ADx after ACLK↑, DCLK↑
Ax after ALE↑
2
Hold time
2
ns
Dx after DLE↑
2
T
A
Operating free-air temperature
0
70°
°C
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2420
NuBus ADDRESS/DATA TRANSCEIVERS AND REGISTERS
SDIS007A – D3159, NOVEMBER 1988 – REVISED JANUARY 1989
electrical characteristics over recommended operating free-air temperature range
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
IK
V
V
V
V
V
V
V
V
V
V
V
= 4.5 V,
–1.2
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
I
= 4.5 V to 5.5 V,
= 4.5 V,
I
= –400 µA
= –3 mA
= –15 mA
= –400 µA
= –2.6 mA
= 12 mA
= 24 mA
= 8 mA
V
–1.5
OH
CC
Ax, Dx, ADx
I
I
2.8
2
3.6
OH
OH
OH
V
OH
= 4.5 V,
V
= 4.5 V to 5.5 V,
= 4.5 V,
I
V
–2
CC
SSEQ, IDEQ
Ax, Dx, ADx
SSEQ, IDEQ
I
I
I
I
I
2.4
3.2
0.25
0.35
0.25
0.35
OH
OL
OL
OL
OL
= 4.5 V,
0.4
0.5
= 4.5 V,
V
OL
V
= 4.5 V,
0.4
= 4.5 V,
= 16 mA
0.5
I
I
= 5.5 V,
V = 5.5 V
I
100
20
µA
µA
I
AEN, DEN, ADEN
ID3–ID0
‡
V
= 5.5 V,
V = 2.7 V
I
–400
–100
–750
–200
–225
160
40
IH
CC
CC
All other inputs
ID3–ID0
‡
I
I
I
V
V
= 5.5 V,
V = 0.4 V
I
µA
mA
mA
IL
All other inputs
§
= 5.5 V,
= 5.5 V,
V
O
= 0 V
–60
OS
CC
CC
Enabled
Disabled
110
30
V
V
V
= 0.5 V,
IL
CC
= 3 V,
Outputs open
IH
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
For I/O ports, the parameters I and I include the off-state output current.
IH
IL
Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2420
NuBus ADDRESS/DATA TRANSCEIVERS AND REGISTERS
SDIS007A – D3159, NOVEMBER 1988 – REVISED JANUARY 1989
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
LOAD CONDITIONS
†
PARAMETER
MIN
40
TYP
MAX
UNIT
MHz
ns
R1, R2, and R
C
LOAD CIRCUIT
L
L
f
t
Maximum clock frequency
max
R1 = 500 Ω,
R2 = 500 Ω
‡
‡
Propagation time, ACLK↑ to Ax (AEN = L)
50 pF
50 pF
S1 Open
9
9
16
pd
R1 = 500 Ω,
R2 = 500 Ω
t
pd
t
pd
t
pd
t
pd
t
pd
t
pd
Propagation time, DCLK↑ to Dx (DEN = L)
Propagation time, Ax to ADx ( ALE = L, A/D = L)
Propagation time, Dx to ADx ( DLE = L, A/D = H)
Propagation time, ALE low to ADx (A/D = L)
Propagation time, DLE low to ADx (A/D = H)
Propagation time, A/D to ADx
S1 Open
16
18
18
18
18
16
ns
ns
ns
ns
ns
ns
R1 = 270 Ω,
R2 = 470 Ω
§
§
§
§
§
300 pF
300 pF
300 pF
300 pF
300 pF
S1 Closed
S1 Closed
S1 Closed
S1 Closed
S1 Closed
10
11
10
11
10
R1 = 270 Ω,
R2 = 470 Ω
R1 = 270 Ω,
R2 = 470 Ω
R1 = 270 Ω,
R2 = 470 Ω
R1 = 270 Ω,
R2 = 470 Ω
t
pd
t
pd
t
pd
t
pd
Propagation time, ACLK to IDEQ
Propagation time, ACLK to SSEQ
Propagation time, IDx to IDEQ
Propagation time, IDx to SSEQ
R
R
R
R
= 500 Ω
= 500 Ω
= 500 Ω
= 500 Ω
50 pF
50 pF
50 pF
50 pF
¶
¶
¶
¶
12
12
12
12
20
18
22
22
ns
ns
ns
ns
L
L
L
L
R1 = 500 Ω,
R2 = 500 Ω
‡
‡
t
t
t
t
t
t
Enable time, AEN to Ax
Enable time, DEN to Dx
Enable time, ADEN to ADx
Disable time, AEN to Ax
Disable time, DEN to Dx
Disable time, ADEN to ADx
50 pF
50 pF
300 pF
50 pF
50 pF
50 pF
10
10
10
6
16
16
18
10
10
10
ns
ns
ns
ns
ns
ns
en
en
en
dis
dis
dis
R1 = 500 Ω,
R2 = 500 Ω
R1 = 270 Ω,
R2 = 470 Ω
§
‡
R1 = 500 Ω,
R2 = 500 Ω
R1 = 500 Ω,
R2 = 500 Ω
‡
§
6
R1 = 270 Ω,
R2 = 470 Ω
6
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
See Parameter Measurement Information for load circuit (3-state outputs, A15–A0, D15–D0) and voltage waveforms.
§See Parameter Measurement Information for load circuit (NuBus Interface, AD15–AD0) and voltage waveforms.
¶See Parameter Measurement Information for load circuit (bi-state totem-pole outputs, SSEQ, IDEQ) and voltage waveforms.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2420
NuBus ADDRESS/DATA TRANSCEIVERS AND REGISTERS
SDIS007A – D3159, NOVEMBER 1988 – REVISED JANUARY 1989
PARAMETER MEASUREMENT INFORMATION
V
CC
V
CC
S1
S1
R1
From Output
Under Test
Test
Point
R1
R
L
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
C
L
(See Note A)
C
R2
R2
L
C
L
(See Note A)
(See Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3–STATE OUTPUTS
A15–A0, D15–D0
LOAD CIRCUIT FOR
NuBus INTERFACE
AD15–AD0
SSEQ, IDEQ
3.5 V
0.3 V
3.5 V
0.3 V
Timing
Input
1.3 V 1.3 V
1.3 V
High-Level
Pulse
t
t
w
t
h
t
su
w
3.5 V
0.3 V
3.5 V
0.3 V
Low-Level
Pulse
Data
Input
1.3 V
1.3 V
1.3 V 1.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Input
3.5 V
1.3 V
1.3 V
Control
(low-level
enabling)
0.3 V
PHL
1.3 V
1.3 V
t
t
PLH
0.3 V
3.5 V
V
OH
t
In-Phase
Output
PZL
1.3 V
1.3 V
1.3 V
t
PLZ
V
OL
Waveform 1
S1 Closed
(see Note B)
t
PLH
t
PHL
1.3 V
V
1.3 V
OH
OL
V
OL
Out-of-Phase
Output
0.3 V
t
PHZ
V
t
PZH
Waveform 2
S1 Open
(see Note B)
V
OH
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.3 V
0.3 V
0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES,3-STATE OUTPUTS
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal condition such that the output is high except when disabled by the output control.
C. C. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2420
NuBus ADDRESS/DATA TRANSCEIVERS AND REGISTERS
SDIS007A – D3159, NOVEMBER 1988 – REVISED JANUARY 1989
APPLICATION INFORMATION
DATA/ADDRESS
INTERFACE
SN74BCT2420
NuBus
CARD-SLOT
SIGNALS
BOARD SPECIFIC
IDEQ
A15/A0
AEN
ACLK
D15/D0
DEN
FUNCTION
32
32
16
16
ID3–ID0
A31/A0
2
PFW
SP
D31/D0
NuBus
CONTROLLER
SN74ACT2440
DCLK
ALE
DLE
ADEN
16
A/D
AD/A1
D
E
C
O
D
E
B
Y
T
E
BT0
BT1
BT2
BT3
DATA/ADDRESS
INTERFACE
SN74BCT2420
IDEQ
IDEQ
A15/A0
AEN
ACLK
D15/D0
DEN
DCLK
ALE
DLE
16
16
AEN
ACLK
NREQ
MRDY
MLREQ
LACK
DEN
DCLK
M
A
S
T
ADEN
I
N
P
U
T
MHOLD
NMREQ
LOCTM0
LOCTM1
SGNTA
SIACK
E
R
AD31–AD0
16
32
A/D
A/D
S
L
A
V
E
S
ADEN
4
4
ID3-0
ARB0-3
CLK
NMRQ
RESET
START
RQST
ACK
ID3-0
ARB0-3
CLK
NMSTR
NSTART
NACK
N
u
B
u
s
NMRQ
RESET
START
RQST
ACK
TM0
TM1
SPV
NLOCK
NLTM0
NLTM1
NCLK
S
T
A
T
U
S
NCLK
NLRST
MDONE
NTM0
2
TM0
TM1
SPV
NTM1
SEREQ
Figure 2. Typical Nubus Interface
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
PLCC
PLCC
Drawing
SN74BCT2420FN
SN74BCT2420FNR
OBSOLETE
OBSOLETE
FN
68
68
TBD
TBD
Call TI
Call TI
Call TI
Call TI
FN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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