SN74CBT6800CDGVR [TI]
具有 –2V 下冲保护的 5V、1:1 (SPST)、10 通道通用 FET 总线开关 | DGV | 24 | -40 to 85;型号: | SN74CBT6800CDGVR |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 –2V 下冲保护的 5V、1:1 (SPST)、10 通道通用 FET 总线开关 | DGV | 24 | -40 to 85 开关 驱动 光电二极管 逻辑集成电路 |
文件: | 总16页 (文件大小:459K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ꢊ ꢉ ꢋꢅꢌ ꢆ ꢍ ꢎꢆ ꢅꢏꢀ ꢀꢐ ꢌ ꢆꢄ ꢑ ꢐ ꢌꢆ ꢑ ꢒꢓꢎ ꢄꢑꢔꢓ ꢕꢎ ꢖ ꢗ ꢏꢆ ꢒ ꢏꢆꢀ
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SCDS138 − OCTOBER 2003
D
D
D
Member of the Texas Instruments
Widebus Family
Undershoot Protection for Off-Isolation on
A and B Ports Up to −2 V
D
V
Operating Range From 4 V to 5.5 V
CC
D
D
D
D
D
Data I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
Control Inputs Can be Driven by TTL or
5-V/3.3-V CMOS Outputs
B-Port Outputs Are Precharged by Bias
Voltage (BIASV) to Minimize Signal
Distortion During Live Insertion and
Hot-Plugging
I
Supports Partial-Power-Down Mode
off
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
D
D
D
Supports PCI Hot Plug
Bidirectional Data Flow, With Near-Zero
Propagation Delay
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
Low ON-State Resistance (r
)
on
Characteristics (r = 3 Ω Typical)
− 1000-V Charged-Device Model (C101)
on
Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
D
Supports Both Digital and Analog
Applications: PCI Interface, Memory
Interleaving, Bus Isolation, Low-Distortion
Signal Gating
(C
= 5.5 pF Typical)
io(OFF)
D
D
Data and Control Inputs Provide
Undershoot Clamp Diodes
Low Power Consumption
(I
= 3 µA Max)
CC
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
1
24
23
22
21
20
19
18
17
16
15
14
13
ON
A1
A2
A3
A4
A5
A6
A7
A8
V
CC
B1
2
3
B2
B3
B4
B5
B6
B7
B8
B9
4
5
6
7
8
9
10
11
12
A9
A10
GND
B10
BIASV
description/ordering information
The SN74CBT6800C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (r ),
on
allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the
SN74CBT6800C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring
that the switch remains in the proper OFF state. The device also precharges the B port to a user-selectable bias
voltage (BIASV) to minimize live-insertion noise.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢉ ꢄ
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ꢘꢋ ꢙ ꢅ ꢏꢀ ꢀꢐ ꢌ ꢆ ꢄꢑ ꢐ ꢌ ꢆꢑ ꢚꢛ ꢋꢙ ꢏꢁ ꢖꢎ ꢓꢀ ꢑꢗ ꢗ ꢆ ꢒꢓꢗ ꢆ ꢎꢄ ꢆꢌ ꢗ ꢁ
SCDS138 − OCTOBER 2003
description/ordering information (continued)
The SN74CBT6800C is a 10-bit bus switch with a single output-enable (ON) input. When ON is low, the 10-bit
bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When
ON is high, the 10-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. The
B port is precharged to BIASV through the equivalent of a 10-kΩ resistor when ON is high, or if the device is
powered down (V
= 0 V).
CC
During insertion (or removal) of a card into (or from) an active bus, the card’s output voltage may be close to
GND. When the connector pins make contact, the card’s parasitic capacitance tries to force the bus signal to
GND, creating a possible glitch on the active bus. This glitching effect can be reduced by using a bus switch
with precharged bias voltage (BIASV) of the bus switch equal to the input threshold voltage level of the receivers
on the active bus. This method will ensure that any glitch produced by insertion (or removal) of the card will not
cross the input threshold region of the receivers on the active bus, minimizing the effects of live-insertion noise.
This device is fully specified for partial-power-down applications using I . The I feature ensures that
off
off
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, ON should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74CBT6800CDW
SN74CBT6800CDWR
SN74CBT6800CDB
SN74CBT6800CDBR
SN74CBT6800CDBQR
SN74CBT6800CPW
SN74CBT6800CPWR
SN74CBT6800CDGVR
SOIC − DW
SSOP − DB
CBT6800C
Tape and reel
Tube
CT6800C
Tape and reel
Tape and reel
Tube
−40°C to 85°C
SSOP (QSOP) − DBQ
CBT6800C
TSSOP − PW
TVSOP − DGV
CT6800C
CT6800C
Tape and reel
Tape and reel
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUT INPUT/OUTPUT
FUNCTION
ON
A
L
B
A port = B port
Disconnect
B port = BIASV
H
Z
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢘ ꢋꢙ ꢅꢏꢀ ꢀꢐ ꢌ ꢆꢄ ꢑ ꢐ ꢌꢆ ꢑ ꢚꢛ ꢋꢙ ꢏꢁꢖ ꢎꢓꢀꢑ ꢗꢗ ꢆ ꢒꢓ ꢗ ꢆꢎ ꢄꢆ ꢌꢗ ꢁ
SCDS138 − OCTOBER 2003
logic diagram (positive logic)
13
BIASV
B1
2
23
14
SW
SW
A1
11
A10
B10
1
ON
simplified schematic, each FET switch (SW)
A
B
Undershoot
Protection Circuit
†
EN
†
EN is the internal enable signal applied to the switch.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢉ ꢄ
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SCDS138 − OCTOBER 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Bias supply voltage range, BIASV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
IN
Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I/O
Control input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK IN
I/OK I/O
I/O port clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
I/O
Continuous current through V
or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 5): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
JA
DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. V and V are used to denote specific conditions for V
I/O
.
I
O
4. I and I are used to denote specific conditions for I .
I
O
I/O
5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 6)
MIN
4
MAX
UNIT
V
V
CC
Supply voltage
5.5
BIASV Bias supply voltage
0
V
V
CC
5.5
V
V
V
High-level control input voltage
Low-level control input voltage
Data input/output voltage
2
V
IH
0
0.8
5.5
85
V
IL
0
V
I/O
T
A
Operating free-air temperature
−40
°C
NOTE 6: All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004. BIASV is a supply voltage, not a control input.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢉꢄ
ꢊ ꢉ ꢋꢅꢌ ꢆ ꢍ ꢎꢆ ꢅꢏꢀ ꢀꢐ ꢌ ꢆꢄ ꢑ ꢐ ꢌꢆ ꢑ ꢒꢓ ꢎꢄꢑꢔꢓ ꢕꢎ ꢖ ꢗ ꢏꢆ ꢒꢏ ꢆꢀ
ꢘ ꢋꢙ ꢅꢏꢀ ꢀꢐ ꢌ ꢆꢄ ꢑ ꢐ ꢌꢆ ꢑ ꢚꢛ ꢋꢙ ꢏꢁꢖ ꢎꢓꢀꢑ ꢗꢗ ꢆ ꢒꢓ ꢗ ꢆꢎ ꢄꢆ ꢌꢗ ꢁ
SCDS138 − OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
Control inputs
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
= 4.5 V,
= 5 V,
I = −18 mA
IN
−1.8
V
IK
CC
0 mA > I ≥ −50 mA,
I
Data inputs
Switch OFF
Switch OFF
−2
V
V
IKU
CC
V
= V
or GND,
IN
CC
I = −10 mA,
I
‡
V
CC
= BIASV = 5 V,
3
V
V
O(USP)
V
IN
= V
or GND,
CC
V
V
= 0 V,
BIASV = V ,
I = 0
O
V −0.1
x
V
x
V
B port
CC
x
O
I
IN
Control inputs
= 5.5 V,
V = V
IN CC
or GND
1
µA
CC
BIASV = 2.4 V,
Switch OFF,
V = V or GND
IN
I
B port
V
= 4.5 V,
0.25
mA
O
CC
V
V
= 0,
O
CC
Switch OFF,
V = V or GND
= 0 to 5.5 V,
O
§
I
I
I
V
V
V
= 5.5 V,
= 0,
10
10
3
µA
µA
µA
OZ
CC
CC
CC
CC
V = 0,
I
IN
V = 0
CC
V
= 0 to 5.5 V,
= 0,
= V or GND,
CC
off
O
I
I
V
I/O
= 5.5 V,
Switch ON or OFF
CC
IN
¶
∆I
Control inputs
Control inputs
A port
V
V
V
V
V
= 5.5 V,
One input at 3.4 V,
Other inputs at V
CC
or GND
2.5
mA
pF
pF
pF
CC
C
C
C
= 3 V or 0
= 3 V or 0,
= 3 V or 0,
4
5.5
in
IN
Switch OFF,
Switch ON,
V
V
= V
= V
or GND
or GND
io(OFF)
io(ON)
I/O
I/O
CC
IN
CC
13.5
IN
CC
= 4 V,
V = 2.4 V,
I
I
O
= −15 mA
8
12
TYP at V
CC
= 4 V
#
I
O
I
O
I
O
= 64 mA
= 30 mA
= −15 mA
3
3
5
6
6
Ω
r
on
V = 0
I
V
CC
= 4.5 V
V = 2.4 V,
I
10
V
†
‡
§
¶
#
and I refer to control inputs. V , V , I , and I refer to data pins.
IN
IN
I
O
I
O
All typical values are at V
= 5 V (unless otherwise noted), T = 25°C.
A
CC
= A-port undershoot static protection.
V
O(USP)
For I/O ports, the parameter I
includes the input leakage current.
OZ
This is the increase in supply current for each input that is at the specified voltage level, rather than V
or GND.
CC
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 5 V
CC
0.5 V
V
= 4 V
CC
TEST
CONDITIONS
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
||
pd
t
A or B
OE
B or A
A or B
0.24
6.2
6.2
5.6
5.6
0.15
5.9
5.9
6.2
6.2
ns
ns
t
t
t
t
1.5
1.5
1.5
1.5
BIASV = GND
BIASV = 3 V
BIASV = GND
BIASV = 3 V
PZH
PZL
PHZ
PLZ
A or B
ns
OE
||
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢉ ꢄ
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ꢘꢋ ꢙ ꢅ ꢏꢀ ꢀꢐ ꢌ ꢆ ꢄꢑ ꢐ ꢌ ꢆꢑ ꢚꢛ ꢋꢙ ꢏꢁ ꢖꢎ ꢓꢀ ꢑꢗ ꢗ ꢆ ꢒꢓꢗ ꢆ ꢎꢄ ꢆꢌ ꢗ ꢁ
SCDS138 − OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
Input Generator
V
IN
50 Ω
50 Ω
V
G1
TEST CIRCUIT
DUT
7 V
Open
GND
Input Generator
50 Ω
S1
R
L
V
V
O
I
50 Ω
V
G2
C
R
L
L
(see Note A)
S1
V
I
V
∆
C
R
V
CC
TEST
L
L
5 V 0.5 V
4 V
Open
Open
500 Ω
500 Ω
V
CC
V
CC
or GND
or GND
50 pF
50 pF
t
pd(s)
5 V 0.5 V
4 V
7 V
7 V
500 Ω
500 Ω
GND
GND
50 pF
50 pF
0.3 V
0.3 V
t
/t
PLZ PZL
5 V 0.5 V
4 V
Open
Open
500 Ω
500 Ω
V
CC
V
CC
50 pF
50 pF
0.3 V
0.3 V
t
/t
PHZ PZH
Output
Control
(V
3 V
0 V
1.5 V
1.5 V
)
IN
t
t
PLZ
PZL
Output
Waveform 1
S1 at 7 V
3.5 V
Output
Control
3 V
0 V
1.5 V
V
V
+ V
1.5 V
1.5 V
OL
∆
(V
IN
)
V
OL
(see Note B)
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
− V
OH
∆
1.5 V
Output
1.5 V
1.5 V
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (t
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
)
pd(s)
C includes probe and jig capacitance.
L
NOTES: A.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
en
. The tpd propagation delay is the calculated RC time constant of the typical ON-state
pd(s)
resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Test Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74CBT6800CDGVR
SN74CBT6800CDGVRE4
SN74CBT6800CDWR
SN74CBT6800CPWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TVSOP
TVSOP
SOIC
DGV
DGV
DW
24
24
24
24
2000 RoHS & Green
2000 RoHS & Green
2000 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
CT6800C
NIPDAU
NIPDAU
NIPDAU
CT6800C
CBT6800C
CT6800C
TSSOP
PW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74CBT6800CDGVR TVSOP
DGV
DW
PW
24
24
24
2000
2000
2000
330.0
330.0
330.0
12.4
24.4
16.4
6.9
10.75 15.7
6.95 8.3
5.6
1.6
2.7
1.6
8.0
12.0
8.0
12.0
24.0
16.0
Q1
Q1
Q1
SN74CBT6800CDWR
SN74CBT6800CPWR
SOIC
TSSOP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74CBT6800CDGVR
SN74CBT6800CDWR
SN74CBT6800CPWR
TVSOP
SOIC
DGV
DW
PW
24
24
24
2000
2000
2000
367.0
350.0
367.0
367.0
350.0
367.0
35.0
43.0
38.0
TSSOP
Pack Materials-Page 2
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
B
13
0.30
24X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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