SN74CBTD3305CDRG4 [TI]

CBT/FST/QS/5C/B SERIES, DUAL 1-BIT DRIVER, TRUE OUTPUT, PDSO8, GREEN, PLASTIC, MS-0012AA, SOIC-8;
SN74CBTD3305CDRG4
型号: SN74CBTD3305CDRG4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

CBT/FST/QS/5C/B SERIES, DUAL 1-BIT DRIVER, TRUE OUTPUT, PDSO8, GREEN, PLASTIC, MS-0012AA, SOIC-8

驱动 光电二极管 输出元件 逻辑集成电路
文件: 总16页 (文件大小:804K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
SN74CBTD3305C  
DUAL FET BUS SWITCH WITH LEVEL SHIFTING  
5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION  
SCDS126A − SEPTEMBER 2003 − REVISED OCTOBER 2003  
D
D
D
D
D
Undershoot Protection for Off-Isolation on  
A and B Ports Up To −2 V  
D
D
D
D
D
Data I/Os Support 0 to 5-V Signaling Levels  
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)  
Integrated Diode to V Provides 5-V Input  
Control Inputs Can be Driven by TTL or  
5-V/3.3-V CMOS Outputs  
CC  
Down To 3.3-V Output Level Shift  
Bidirectional Data Flow, With Near-Zero  
Propagation Delay  
I
off  
Supports Partial-Power-Down Mode  
Operation  
Low ON-State Resistance (r  
)
on  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Characteristics (r = 3 Ω Typical)  
on  
Low Input/Output Capacitance Minimizes  
Loading and Signal Distortion  
ESD Performance Tested Per JESD 22  
− 2000-V Human-Body Model  
(A114-B, Class II)  
(C  
= 5 pF Typical)  
io(OFF)  
− 1000-V Charged-Device Model (C101)  
D
D
Data and Control Inputs Provide  
Undershoot Clamp Diodes  
D
Supports Both Digital and Analog  
Applications: USB Interface, Memory  
Interleaving, Bus Isolation, Low-Distortion  
Signal Gating  
V
CC  
Operating Range From 4.5 V to 5.5 V  
D OR PW PACKAGE  
(TOP VIEW)  
1
2
3
4
1OE  
1A  
1B  
8
7
6
5
VCC  
2OE  
2B  
GND  
2A  
description/ordering information  
The SN74CBTD3305C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (r ),  
on  
allowing for minimal propagation delay. This device features an integrated diode in series with V to provide  
CC  
level shifting for 5-V input down to 3.3-V output levels. Active Undershoot-Protection Circuitry on the A and B  
ports of the SN74CBTD3305C provides protection for undershoot up to −2 V by sensing an undershoot event  
and ensuring that the switch remains in the proper OFF state.  
The SN74CBTD3305C is organized as two 1-bit bus switches with separate output-enable (1OE, 2OE) inputs.  
It can be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is high, the associated 1-bit bus  
switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When  
OE is low, the associated 1-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
Tube  
SN74CBTD3305CD  
SOIC − D  
CC305C  
Tape and reel SN74CBTD3305CDR  
Tube SN74CBTD3305CPW  
Tape and reel SN74CBTD3305CPWR  
−40°C to 85°C  
TSSOP − PW  
CC305C  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright © 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74CBTD3305C  
DUAL FET BUS SWITCH WITH LEVEL SHIFTING  
5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION  
SCDS126A − SEPTEMBER 2003 − REVISED OCTOBER 2003  
description/ordering information (continued)  
This device is fully specified for partial-power-down applications using I . The I feature ensures that  
off  
off  
damaging current will not backflow through the device when it is powered down. The device has isolation during  
power off.  
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a  
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the  
driver.  
FUNCTION TABLE  
(each bus switch)  
INPUT INPUT/OUTPUT  
FUNCTION  
OE  
H
A
B
Z
A port = B port  
Disconnect  
L
logic diagram (positive logic)  
2
1
3
1A  
1B  
SW  
SW  
1OE  
5
7
6
2A  
2B  
2OE  
simplified schematic, each FET switch (SW)  
A
B
Undershoot  
Protection Circuit  
EN  
EN is the internal enable signal applied to the switch.  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74CBTD3305C  
DUAL FET BUS SWITCH WITH LEVEL SHIFTING  
5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION  
SCDS126A − SEPTEMBER 2003 − REVISED OCTOBER 2003  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V  
CC  
Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V  
IN  
Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V  
I/O  
Control input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA  
IK  
IN  
I/O port clamp current, I  
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA  
I/O  
I/OK  
ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA  
I/O  
Continuous current through V or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA  
CC  
Package thermal impedance, θ (see Note 5): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W  
JA  
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
Storage temperature range, T  
stg  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. All voltages are with respect to ground unless otherwise specified.  
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.  
3. V and V are used to denote specific conditions for V .  
I
O
I/O  
4. I and I are used to denote specific conditions for I .  
I
O
I/O  
5. The package thermal impedance is calculated in accordance with JESD 51-7.  
recommended operating conditions (see Notes 6 and 7)  
MIN  
4.5  
2
MAX  
5.5  
5.5  
0.8  
5.5  
85  
UNIT  
V
V
V
V
V
T
Supply voltage  
CC  
High-level control input voltage  
Low-level control input voltage  
Data input/output voltage  
Operating free-air temperature  
V
IH  
0
V
IL  
0
V
I/O  
−40  
°C  
A
NOTES: 6. All unused control inputs of the device must be held at V or GND to ensure proper device operation. Refer to the TI application  
CC  
report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
7. In applications with fast edge rates, multiple outputs switching, and operating at high frequencies, the output may have little or no  
level-shifting effect.  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74CBTD3305C  
DUAL FET BUS SWITCH WITH LEVEL SHIFTING  
5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION  
SCDS126A − SEPTEMBER 2003 − REVISED OCTOBER 2003  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
PARAMETER  
Control inputs  
TEST CONDITIONS  
MIN TYP  
MAX  
UNIT  
V
V
V
V
= 4.5 V,  
= 5 V,  
I = −18 mA  
IN  
−1.8  
V
IK  
CC  
0 mA > I −50 mA,  
I
Data inputs  
Switch OFF  
−2  
V
IKU  
OH  
CC  
V
IN  
= V or GND,  
CC  
V
I
See Figures 4 and 5  
Control inputs  
V
V
V
V
= 5.5 V,  
= 5.5 V,  
= 0,  
V
V
= V or GND  
1
10  
μA  
μA  
μA  
mA  
IN  
CC  
CC  
CC  
CC  
CC  
IN  
CC  
= 0 to 5.5 V,  
Switch OFF,  
O
I
OZ  
V = 0,  
I
V = V or GND  
IN CC  
I
I
V
O
= 0 to 5.5 V,  
V = 0  
I
10  
off  
CC  
I
I/O  
= 0,  
= 5.5 V,  
Switch ON or OFF  
1.5  
2.5  
V
IN  
= V or GND,  
CC  
§
ΔI  
CC  
Control inputs  
Control inputs  
V
V
V
V
= 5.5 V,  
One input at 3.4 V,  
Other inputs at V or GND  
mA  
pF  
pF  
pF  
CC  
C
C
C
= 3 V or 0  
= 3 V or 0,  
= 3 V or 0,  
3.5  
in  
IN  
Switch OFF,  
Switch ON,  
V
V
= V or GND  
5
io(OFF)  
io(ON)  
I/O  
IN  
CC  
= V or GND  
12.5  
I/O  
IN  
CC  
I
O
I
O
I
O
= 64 mA  
= 30 mA  
= −15 mA  
3
3
8
6
6
V = 0  
I
V
CC  
= 4.5 V  
Ω
r
on  
V = 2.4 V,  
I
20  
V
and I refer to control inputs. V , V , I , and I refer to data pins.  
IN I O I O  
IN  
All typical values are at V = 5 V (unless otherwise noted), T = 25°C.  
CC  
A
§
For I/O ports, the parameter I includes the input leakage current.  
OZ  
This is the increase in supply current for each input that is at the specified voltage level, rather than V or GND.  
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by  
the lower of the voltages of the two (A or B) terminals.  
CC  
switching characteristics over recommended operating free-air temperature range (unless  
otherwise noted) (see Figure 3)  
V
= 5 V  
0.5 V  
CC  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
MIN  
MAX  
#
t
t
t
A or B  
OE  
B or A  
A or B  
A or B  
0.15  
4.7  
ns  
ns  
ns  
pd  
en  
dis  
1.5  
1.5  
5.3  
OE  
#
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,  
when driven by an ideal voltage source (zero output impedance).  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74CBTD3305C  
DUAL FET BUS SWITCH WITH LEVEL SHIFTING  
5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION  
SCDS126A − SEPTEMBER 2003 − REVISED OCTOBER 2003  
undershoot characteristics (see Figures 1 and 2)  
PARAMETER  
TEST CONDITIONS  
Switch OFF,  
MIN  
TYP  
−0.3  
MAX  
UNIT  
V
OUTU  
V
CC  
= 5.5 V,  
V
IN  
= V or GND  
2
V
V
CC  
OH  
All typical values are at V = 5 V (unless otherwise noted), T = 25°C.  
CC  
A
V
CC  
11 V  
100 kΩ  
5.5 V  
Input  
(Open  
Socket)  
Input  
Generator  
90 %  
90 %  
10 %  
50 Ω  
2 ns 2 ns  
20 ns  
DUT  
Ax  
Bx  
10 %  
−2 V  
100 kΩ  
10 pF  
V
S
Output  
V
OH  
V
OH  
(V  
OUTU  
)
− 0.3  
Figure 1. Device Test Setup  
Figure 2. Transient Input Voltage (V ) and Output  
I
Voltage (V  
) Waveforms  
OUTU  
(Switch OFF)  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74CBTD3305C  
DUAL FET BUS SWITCH WITH LEVEL SHIFTING  
5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION  
SCDS126A − SEPTEMBER 2003 − REVISED OCTOBER 2003  
PARAMETER MEASUREMENT INFORMATION  
FOR LEVEL SHIFTER  
V
CC  
Input Generator  
V
IN  
50 Ω  
50 Ω  
V
G1  
TEST CIRCUIT  
DUT  
7 V  
Open  
GND  
Input Generator  
50 Ω  
S1  
R
V
V
O
L
I
50 Ω  
V
G2  
C
R
L
L
(see Note A)  
S1  
V
I
V
Δ
C
R
V
CC  
TEST  
L
L
t
pd(s)  
5 V 0.5 V  
5 V 0.5 V  
5 V 0.5 V  
Open  
7 V  
500 Ω  
500 Ω  
500 Ω  
V
CC  
or GND  
50 pF  
50 pF  
50 pF  
t
/t  
PLZ PZL  
GND  
0.3 V  
0.3 V  
t
/t  
PHZ PZH  
Open  
V
CC  
Output  
Control  
(V  
3 V  
0 V  
1.5 V  
1.5 V  
)
IN  
t
t
t
PLZ  
PZL  
PZH  
Output  
Waveform 1  
S1 at 7 V  
3.5 V  
Output  
Control  
3 V  
0 V  
1.5 V  
1.5 V  
V
V
+ V  
Δ
1.5 V  
1.5 V  
OL  
(V  
IN  
)
V
OL  
(see Note B)  
t
PHZ  
t
t
PLH  
PHL  
Output  
Waveform 2  
S1 at Open  
(see Note B)  
V
OH  
V
V
OH  
− V  
Δ
OH  
Output  
1.5 V  
1.5 V  
0 V  
OL  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES (t  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
)
pd(s)  
NOTES: A. C includes probe and jig capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 Ω, t 2.5 ns, t 2.5 ns.  
O
r
f
D. The outputs are measured one at a time with one transition per measurement.  
E.  
F.  
G.  
t
t
t
and t  
and t  
and t  
are the same as t  
are the same as t  
are the same as t  
.
.
PLZ  
PZL  
PLH  
PHZ  
dis  
PZH  
en  
. The tpd propagation delay is the calculated RC time constant of the typical ON-state  
PHL  
pd(s)  
resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).  
H. All parameters and waveforms are not applicable to all devices.  
Figure 3. Test Circuit and Voltage Waveforms  
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74CBTD3305C  
DUAL FET BUS SWITCH WITH LEVEL SHIFTING  
5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION  
SCDS126A − SEPTEMBER 2003 − REVISED OCTOBER 2003  
TYPICAL CHARACTERISTICS  
OUTPUT VOLTAGE HIGH  
OUTPUT VOLTAGE HIGH  
vs  
vs  
SUPPLY VOLTAGE  
SUPPLY VOLTAGE  
4
3.75  
3.5  
4
3.75  
3.5  
T
= 85°C  
T = 25°C  
A
V = V  
I CC  
A
V = V  
I
CC  
100 μA  
100 μA  
6 mA  
12 mA  
6 mA  
12 mA  
3.25  
3.25  
24 mA  
24 mA  
3
3
2.75  
2.75  
2.5  
2.25  
2
2.5  
2.25  
2
1.75  
1.5  
1.75  
1.5  
4.5  
4.75  
5
5.25  
5.5  
5.75  
4.5  
4.75  
5
5.25  
5.5  
5.75  
V
CC  
− Supply Voltage − V  
V
CC  
− Supply Voltage − V  
OUTPUT VOLTAGE HIGH  
vs  
SUPPLY VOLTAGE  
4
3.75  
3.5  
T
= 0°C  
A
V = V  
I
CC  
100 μA  
3.25  
6 mA  
12 mA  
3
24 mA  
2.75  
2.5  
2.25  
2
1.75  
1.5  
4.5  
4.75  
5
5.25  
5.5  
5.75  
V
CC  
− Supply Voltage − V  
Figure 4. V Values  
OH  
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74CBTD3305C  
DUAL FET BUS SWITCH WITH LEVEL SHIFTING  
5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION  
SCDS126A − SEPTEMBER 2003 − REVISED OCTOBER 2003  
TYPICAL CHARACTERISTICS (continued)  
OUTPUT VOLTAGE  
vs  
INPUT VOLTAGE  
3.5  
V
T
= 5 V  
= 25°C  
CC  
100 μA  
6 mA  
12 mA  
A
3
24 mA  
2.5  
2
1.5  
1
5
0
0
1
2
3
4
5
V − Input Voltage − V  
I
Figure 5. Data Output Voltage vs Data Input Voltage  
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Apr-2013  
PACKAGING INFORMATION  
Orderable Device  
SN74CBTD3305CD  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
Top-Side Markings  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4)  
ACTIVE  
SOIC  
SOIC  
D
8
8
8
8
8
8
8
8
8
8
8
75  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Call TI  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Call TI  
CC305C  
SN74CBTD3305CDE4  
SN74CBTD3305CDG4  
SN74CBTD3305CDR  
SN74CBTD3305CDRE4  
SN74CBTD3305CDRG4  
SN74CBTD3305CPW  
SN74CBTD3305CPWE4  
SN74CBTD3305CPWG4  
SN74CBTD3305CPWR  
SN74CBTD3305CPWRE4  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
D
D
75  
Green (RoHS  
& no Sb/Br)  
CC305C  
CC305C  
CC305C  
CC305C  
CC305C  
CC305C  
CC305C  
CC305C  
CC305C  
SOIC  
75  
Green (RoHS  
& no Sb/Br)  
SOIC  
D
2500  
2500  
2500  
150  
Green (RoHS  
& no Sb/Br)  
SOIC  
D
Green (RoHS  
& no Sb/Br)  
SOIC  
D
Green (RoHS  
& no Sb/Br)  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
PW  
PW  
PW  
PW  
PW  
Green (RoHS  
& no Sb/Br)  
150  
Green (RoHS  
& no Sb/Br)  
150  
Green (RoHS  
& no Sb/Br)  
2000  
Green (RoHS  
& no Sb/Br)  
TBD  
SN74CBTD3305CPWRG3  
SN74CBTD3305CPWRG4  
PREVIEW  
TSSOP  
TSSOP  
PW  
PW  
8
8
2000  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
-40 to 85  
-40 to 85  
OBSOLETE  
CC305C  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Apr-2013  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4)  
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a  
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
24-Apr-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
SN74CBTD3305CDR  
SOIC  
D
8
8
8
2500  
2000  
2000  
330.0  
330.0  
330.0  
12.4  
12.4  
12.4  
6.4  
7.0  
7.0  
5.2  
3.6  
3.6  
2.1  
1.6  
1.6  
8.0  
8.0  
8.0  
12.0  
12.0  
12.0  
Q1  
Q1  
Q1  
SN74CBTD3305CPWR TSSOP  
SN74CBTD3305CPWR TSSOP  
PW  
PW  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
24-Apr-2013  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
SN74CBTD3305CDR  
SN74CBTD3305CPWR  
SN74CBTD3305CPWR  
SOIC  
D
8
8
8
2500  
2000  
2000  
340.5  
367.0  
364.0  
338.1  
367.0  
364.0  
20.6  
35.0  
27.0  
TSSOP  
TSSOP  
PW  
PW  
Pack Materials-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other  
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest  
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supplied at the time of order acknowledgment.  
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary  
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and  
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