SN74CBTLV16212DGV [TI]
LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH; 低电压24位FET总线交换开关
| 型号： | SN74CBTLV16212DGV |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH |
| 文件： | 总8页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74CBTLV16212
LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH
SCDS044E – DECEMBER 1997 – REVISED AUGUST 1999
DGG, DGV, OR DL PACKAGE
4-Ω Switch Connection Between Two Ports
(TOP VIEW)
Isolation Under Power-Off Conditions
Break-Before-Make Feature
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
S0
1A1
1A2
2A1
2A2
3A1
3A2
GND
4A1
4A2
5A1
5A2
6A1
6A2
7A1
7A2
S1
S2
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
2
3
1B1
1B2
2B1
2B2
3B1
GND
3B2
4B1
4B2
5B1
5B2
6B1
6B2
7B1
7B2
8B1
GND
8B2
9B1
9B2
10B1
10B2
11B1
11B2
12B1
12B2
4
5
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
6
7
Package Options Include Plastic Thin
Shrink Small-Outline (DGG), Thin Very
Small-Outline (DGV), and 300-mil Shrink
Small-Outline (DL) Packages
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NOTE:
For tape and reel order entry:
The DGGR package is abbreviated to GR, and
the DGVR package is abbreviated to VR.
description
The SN74CBTLV16212 provides 24 bits of
V
CC
high-speed bus switching or exchanging. The low
on-state resistance of the switch allows
connections to be made with minimal propagation
delay.
8A1
GND
8A2
9A1
9A2
10A1
10A2
11A1
11A2
12A1
12A2
The device operates as a 24-bit bus switch or a
12-bit bus exchanger, which provides data
exchanging between the four signal ports via the
data-select (S0, S1, S2) terminals.
The SN74CBTLV16212 is specified by the
break-before-make feature to have no through
current when switching between B ports.
The SN74CBTLV16212 is characterized for
operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTLV16212
LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH
SCDS044E – DECEMBER 1997 – REVISED AUGUST 1999
FUNCTION TABLE
INPUTS
INPUTS/OUTPUTS
FUNCTION
S2
L
S1
L
S0
L
A1
Z
A2
Z
Disconnect
L
L
H
L
B1
B2
Z
Z
A1 port = B1 port
A1 port = B2 port
A2 port = B1 port
A2 port = B2 port
Disconnect
L
H
H
L
Z
L
H
L
B1
B2
Z
H
H
Z
L
H
Z
A1 port = B1 port
A2 port = B2 port
H
H
H
H
L
B1
B2
B2
B1
A1 port = B2 port
A2 port = B1 port
H
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTLV16212
LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH
SCDS044E – DECEMBER 1997 – REVISED AUGUST 1999
logic diagram (positive logic)
2
54
1A1
1B1
SW
SW
SW
3
53
SW
1B2
1A2
27
30
12A1
12B1
SW
SW
SW
28
29
12B2
SW
12A2
1
S0
56
S1
55
S2
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTLV16212
LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH
SCDS044E – DECEMBER 1997 – REVISED AUGUST 1999
simplified schematic, each FET switch
A
B
(OE)
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Package thermal impedance, θ (see Note 2): DGG package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
JA
DGV package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DL package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
MIN
2.3
1.7
2
MAX
UNIT
V
V
Supply voltage
3.6
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
High-level control input voltage
V
IH
0.7
0.8
85
V
IL
Low-level control input voltage
Operating free-air temperature
V
T
A
–40
°C
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTLV16212
LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH
SCDS044E – DECEMBER 1997 – REVISED AUGUST 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
–1.2
±1
UNIT
V
V
V
V
V
V
V
= 3 V,
IK
CC
CC
CC
CC
CC
I
I
I
I
= 3.6 V,
= 0,
V = V or GND
I CC
µA
µA
µA
µA
pF
I
V or V = 0 to 3.6 V
10
off
I
O
= 3.6 V,
= 3.6 V,
I
O
= 0,
V = V
I
or GND
10
CC
CC
‡
∆I
CC
Control inputs
One input at 3 V,
Other inputs at V
or GND
300
CC
C
C
Control inputs V = 3 V or 0
5
8
5
5
i
I
V
O
= 3 V or 0,
OE = V
CC
pF
io(OFF)
I = 64 mA
8
8
I
V = 0
I
V
= 2.3 V,
CC
I = 24 mA
I
TYP at V
= 2.5 V
CC
V = 1.7 V,
I
I = 15 mA
I
27
5
40
7
§
on
Ω
r
I = 64 mA
I
V = 0
I
V
CC
= 3 V
I = 24 mA
I
5
7
V = 2.4 V,
I
I = 15 mA
I
10
15
†
‡
§
All typical values are at V
This is the increase in supply current for each input that is at the specified voltage level rather than V
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
= 3.3 V (unless otherwise noted), T = 25°C.
A
CC
or GND.
CC
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)
V
= 2.5 V
V
= 3.3 V
CC
± 0.2 V
CC
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
0.15
11.1
10.9
8.7
MIN
MAX
0.25
8.8
¶
A or B
B or A
B or A
A or B
A or B
ns
ns
ns
ns
t
t
t
t
pd
pd
en
dis
S
S
S
3
3
1
3
3
2
8.6
8.8
¶
Thepropagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTLV16212
LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH
SCDS044E – DECEMBER 1997 – REVISED AUGUST 1999
PARAMETER MEASUREMENT INFORMATION
V
= 2.5 V ± 0.2 V
CC
2 × V
CC
S1
TEST
S1
Open
500 Ω
From Output
Under Test
t
Open
pd
/t
GND
t
2 × V
CC
GND
PLZ PZL
/t
C
= 30 pF
L
t
PHZ PZH
500 Ω
(see Note A)
V
CC
Output
Control
V
CC
/2
V
CC
/2
LOAD CIRCUIT
0 V
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
V
OH
Output
Waveform 2
S1 at GND
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTLV16212
LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH
SCDS044E – DECEMBER 1997 – REVISED AUGUST 1999
PARAMETER MEASUREMENT INFORMATION
V
= 3.3 V ± 0.3 V
CC
6 V
TEST
S1
S1
500 Ω
Open
GND
From Output
Under Test
t
Open
6 V
pd
t
/t
PLZ PZL
/t
C
= 50 pF
t
GND
L
PHZ PZH
500 Ω
(see Note A)
Output
3 V
0 V
Control
(low-level
enabling)
1.5 V
1.5 V
LOAD CIRCUIT
t
PZL
t
PLZ
Output
Waveform 1
S1 at 6 V
3 V
3 V
0 V
1.5 V
Input
V
+ 0.3 V
1.5 V
1.5 V
OL
V
OL
(see Note B)
t
PHZ
t
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
– 0.3 V
0 V
1.5 V
Output
1.5 V
1.5 V
(see Note B)
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
C includes probe and jig capacitance.
L
ENABLE AND DISABLE TIMES
NOTES: A.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 2. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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Copyright 1999, Texas Instruments Incorporated
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