SN74F175NSR [TI]
QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR; 翻两番D型触发器与Clear
| 型号： | SN74F175NSR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR |
| 文件： | 总12页 (文件大小：360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74F175
QUADRUPLE D-TYPE FLIP-FLOP
WITH CLEAR
SDFS058B – D293, MARCH 1987 – REVISED MAY 2002
D, N, OR NS PACKAGE
(TOP VIEW)
Contains Four Flip-Flops With Double-Rail
Outputs
Buffered Clock and Direct Clear Inputs
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CLR
1Q
1Q
1D
2D
2Q
2Q
GND
CC
Applications Include:
– Buffer/Storage Registers
– Shift Registers
4Q
4Q
4D
3D
3Q
3Q
CLK
– Pattern Generators
description
This positive-edge-triggered flip-flop utilizes TTL
circuitry to implement D-type flip-flop logic with a
direct clear (CLR) input. Information at the data
(D) inputs meeting setup-time requirements is
transferred to outputs on the positive-going edge
of the clock pulse. Clock triggering occurs at a
particular voltage level and is not directly related
to the transition time of the positive-going pulse.
When the clock (CLK) input is at either the high or
low level, the D-input signal has no effect at the
output.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – N
SOIC – D
SOP – NS
Tube
SN74F175N
SN74F175N
Tube
SN74F175D
0°C to 70°C
F175
Tape and reel
Tape and reel
SN74F175DR
SN74F175NSR
74F175
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OUTPUTS
CLR
L
CLK
D
X
H
L
Q
L
Q
H
L
X
↑
H
H
L
H
↑
H
H
L
X
Q
Q
0
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F175
QUADRUPLE D-TYPE FLIP-FLOP
WITH CLEAR
SDFS058B – D293, MARCH 1987 – REVISED MAY 2002
logic diagram (positive logic)
9
CLK
1
CLR
4
2
3
1D
1D
C1
1Q
1Q
R
Two Identical Channels
Not Shown
13
15
14
4D
1D
4Q
4Q
C1
R
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V
I
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA to 5 mA
Voltage range applied to any output in the high state, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
CC
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input voltage ratings may be exceeded if the input current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN NOM
MAX
UNIT
V
V
V
V
Supply voltage
4.5
2
5
5.5
CC
IH
IL
High-level input voltage
Low-level input voltage
Input clamp current
V
0.8
–18
–1
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
Operating free-air temperature
OH
OL
20
T
A
0
70
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F175
QUADRUPLE D-TYPE FLIP-FLOP
WITH CLEAR
SDFS058B – D293, MARCH 1987 – REVISED MAY 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V,
= 4.5 V,
= 4.75 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
–1.2
V
IK
I
I
I
I
= –1 mA
= –1 mA
= 20 mA
2.5
2.7
3.4
0.3
OH
OH
OL
V
OH
OL
0.5
0.1
V
I
I
I
I
I
V = 7 V
I
mA
µA
I
V = 2.7 V
I
20
IH
V = 0.5 V
I
– 0.6
–150
34
mA
mA
mA
IL
‡
V
O
= 0
–60
OS
CC
See Note 4
22.5
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 4:
I
is measured with outputs open, with 4.5 V applied to all data inputs after a momentary ground, followed by 4.5 V applied to CLK.
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
V
T
= 5 V,
= 25°C
CC
A
MIN
MAX
UNIT
MIN
MAX
f
t
Clock frequency
Pulse duration
100
100
MHz
clock
CLK high
CLK low
4
5
5
3
5
1
4
5
5
3
5
1
ns
w
CLR low
High or low
CLR high
High or low
Setup time, data before CLK↑
t
t
ns
ns
su
§
Setup time, inactive state, data before CLK↑
Hold time, data after CLK↑
h
§
Inactive-state setup time also is referred to as recovery time.
switching characteristics (see Figure 1)
V
T
= 5 V,
V
=
CC
A
CC
4.5 V to 5.5 V
FROM
TO
(OUTPUT)
= 25°C
TYP
140
4.6
PARAMETER
(INPUT)
UNIT
MIN
100
3.2
3.2
3.2
3.7
MAX
MIN
100
3.2
3.2
3.2
3.7
MAX
f
MHz
ns
max
PLH
PHL
PLH
PHL
t
t
t
t
6.5
8.5
7.5
9.5
9
CLK
CLR
Q or Q
6.1
6.1
8.5
Q
Q
ns
8.6
11.5
13
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F175
QUADRUPLE D-TYPE FLIP-FLOP
WITH CLEAR
SDFS058B – D293, MARCH 1987 – REVISED MAY 2002
PARAMETER MEASUREMENT INFORMATION
7 V
Open
S1
500 Ω
TEST
S1
From Output
Under Test
C
Test
Point
From Output
Under Test
t
t
/t
Open
7 V
PLH PHL
/t
C
t
L
L
PLZ PZL
/t
500 Ω
500 Ω
(see Note A)
(see Note A)
Open
7 V
PHZ PZH
Open Collector
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
3 V
Timing Input
1.5 V
0 V
t
w
t
h
t
3 V
su
3 V
0 V
1.5 V
1.5 V
Input
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
Input
3 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
0 V
t
PZL
t
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
S1 at 7 V
V
V
≈3.5 V
OH
In-Phase
Output
1.5 V
1.5 V
1.5 V
1.5 V
V
OL
+ 0.3 V
V
OL
OL
(see Note B)
t
PHZ
t
PHL
PLH
t
PZH
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
Out-of-Phase
Output
V
OH
– 0.3 V
1.5 V
1.5 V
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns,
O
r
f
duty cycle = 50%.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
PACKAGING INFORMATION
Orderable Device
SN74F175D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74F175DE4
SN74F175DG4
SN74F175DR
SN74F175DRE4
SN74F175DRG4
SN74F175N
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
D
D
D
D
D
N
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74F175N3
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
16
16
TBD
Call TI
Call TI
SN74F175NE4
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74F175NSR
SN74F175NSRE4
SN74F175NSRG4
ACTIVE
ACTIVE
ACTIVE
SO
SO
SO
NS
NS
NS
16
16
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jun-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jun-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
(mm)
16
SN74F175DR
D
16
16
FMX
MLA
6.5
8.2
10.3
10.5
2.1
2.5
8
16
16
Q1
Q1
SN74F175NSR
NS
330
16
12
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN74F175DR
D
16
16
FMX
MLA
342.9
342.9
336.6
336.6
28.58
28.58
SN74F175NSR
NS
Pack Materials-Page 2
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