SN74F190AN [TI]

Synchronous up/down decade counters 16-PDIP 0 to 70;
SN74F190AN
型号: SN74F190AN
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

Synchronous up/down decade counters 16-PDIP 0 to 70

光电二极管 输出元件 逻辑集成电路 触发器
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SN74F190A  
SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTER  
WITH RESET AND RIPPLE CLOCK  
SDFS026B – D3690, JULY 1990 – REVISED OCTOBER 1993  
D OR N PACKAGE  
(TOP VIEW)  
High-Speed f  
Single Down/Up Count Control Line  
of 125 MHz Typical  
max  
Look-Ahead Circuitry Enhances Speed of  
B
V
A
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC  
Cascaded Counters  
Q
Q
B
A
Fully Synchronous in Count Modes  
CLK  
RCO  
MAX/MIN  
LOAD  
C
Asynchronously Presettable With Load  
CTEN  
D/U  
Control  
Q
C
Package Options Include Plastic  
Small-Outline Packages and Standard  
Plastic 300-mil DIPs  
Q
D
GND  
D
description  
The SN74F190A is a synchronous, 4-bit decade reversible up/down counter. Synchronous counting operation  
is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other  
when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally  
associated with asynchronous (ripple-clock) counters.  
The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock (CLK) input if the  
enable (CTEN) input is low. A high at CTEN inhibits counting. The direction of the count is determined by the  
level of the down/up (D/U) input. When D/U is low, the counter counts up, and when D/U is high, it counts down.  
Thiscounterfeaturesafullyindependentclockcircuit. Changesatthecontrol(CTENandD/U)inputsthatmodify  
the operating mode have no effect on the contents of the counter until clocking occurs. The function of the  
counter is dictated solely by the condition meeting the stable setup and hold times. This counter is fully  
programmable; that is, it may be preset to any number between 0 and 9 by placing a low on the load input and  
entering the desired data at the data inputs. The output changes to agree with the data inputs independent of  
the level of the clock input. This feature allows the counter to be used as a modulo-N divider by simply modifying  
the count length with the preset inputs.  
Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum  
count. The latter output produces a high-level output pulse with a duration approximately equal to one complete  
cycle of the clock while the count is minimum (0) counting down or maximum (9) counting up. The ripple-clock  
(RCO) output produces a low-level output pulse under those same conditions, but only while the clock input is  
low. The counter can easily be cascaded by feeding the ripple-clock output to the enable input of the succeeding  
counter if parallel clocking is used or to the clock input if parallel enabling is used. The maximum/minimum count  
(MAX/MIN) output can be used to accomplish look-ahead for high speed operation.  
The SN74F190A is characterized for operation from 0°C to 70°C.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74F190A  
SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTER  
WITH RESET AND RIPPLE CLOCK  
SDFS026B – D3690, JULY 1990 – REVISED OCTOBER 1993  
logic symbol  
4
CTRDIV10  
CTEN  
D/U  
G1  
12  
13  
5
2(CT=0)Z6  
3(CT=9)Z6  
MAX/MIN  
RCO  
M2 [DOWN]  
M3 [UP]  
14  
CLK  
1,2– / 1,3+  
G4  
6,1,4  
11  
LOAD  
C5  
15  
1
3
2
[1]  
Q
A
A
B
C
D
5D  
[2]  
[3]  
[4]  
Q
B
10  
9
6
7
Q
Q
C
D
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
2–2  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74F190A  
SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTER  
WITH RESET AND RIPPLE CLOCK  
SDFS026B – D3690, JULY 1990 – REVISED OCTOBER 1993  
logic diagram(positive logic)  
12  
MAX/  
MIN  
4
CTEN  
13  
RCO  
5
D/U  
14  
CLK  
11  
LOAD  
15  
A
3
S
Q
A
C1  
1D  
R
1
B
2
S
Q
B
C1  
1D  
R
10  
C
6
S
Q
C
C1  
1D  
R
9
D
7
S
Q
D
C1  
1D  
R
2–3  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74F190A  
SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTER  
WITH RESET AND RIPPLE CLOCK  
SDFS026B – D3690, JULY 1990 – REVISED OCTOBER 1993  
typical load, count, and inhibit sequences  
Illustrated below is the following sequence:  
1. Load (preset) to BCD seven  
2. Count up to eight, nine (maximum), zero, one, and two  
3. Inhibit  
4. Count down to one, zero (minimum), nine, eight, and seven  
LOAD  
A
B
Data  
Inputs  
C
D
CLK  
D/U  
CTEN  
Q
A
B
C
D
Q
Q
Q
MAX/MIN  
RCO  
7
8
9
0
1
2
2
2
1
0
9
8
7
Count Up  
Inhibit  
Count Down  
Load  
2–4  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74F190A  
SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTER  
WITH RESET AND RIPPLE CLOCK  
SDFS026B – D3690, JULY 1990 – REVISED OCTOBER 1993  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V  
I
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 mA to 5 mA  
Voltage applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to V  
CC  
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA  
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 °C to 70 °C  
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTE 1: The input-voltage ratings may be exceeded if the input-current ratings are observed.  
recommended operating conditions  
MIN NOM  
MAX  
UNIT  
V
V
V
V
Supply voltage  
4.5  
2
5
5.5  
CC  
IH  
IL  
High-level input voltage  
Low-level input voltage  
Input clamp current  
V
0.8  
18  
– 1  
20  
70  
V
I
I
I
mA  
mA  
mA  
°C  
IK  
High-level output current  
Low-level output current  
Operating free-air temperature  
OH  
OL  
T
A
0
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
PARAMETER  
TEST CONDITIONS  
I = – 18 mA  
MIN TYP  
MAX  
UNIT  
V
IK  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 4.5 V,  
= 4.5 V,  
= 4.75 V,  
= 4.5 V,  
= 5.5 V,  
= 5.5 V,  
– 1.2  
V
I
I
I
I
= – 1 mA  
= – 1 mA  
= 20 mA  
2.5  
2.7  
3.4  
0.3  
OH  
OH  
OL  
V
V
V
OH  
0.5  
0.1  
V
OL  
I
I
V = 7 V  
I
mA  
µA  
I
IH  
V = 2.7 V  
I
20  
CTEN  
– 1.8  
– 0.6  
– 150  
55  
I
V
= 5.5 V,  
V = 0.5 V  
mA  
IL  
CC  
I
Others  
§
I
I
V
V
= 5.5 V,  
= 5.5 V,  
V = 0  
O
– 60  
mA  
mA  
OS  
CC  
CC  
Outputs open  
40  
CC  
§
All typical values are at V  
= 5 V, T = 25°C.  
A
CC  
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.  
2–5  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74F190A  
SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTER  
WITH RESET AND RIPPLE CLOCK  
SDFS026B – D3690, JULY 1990 – REVISED OCTOBER 1993  
timing requirements  
V
T
= 5 V,  
= 25°C  
V
T
= 4.5 V to 5.5 V,  
CC  
A
CC  
= MIN to MAX  
UNIT  
MHz  
ns  
A
MIN  
0
MAX  
MIN  
0
MAX  
90  
f
t
Clock frequency  
Pulse duration  
90  
clock  
LOAD low  
6
6
CLK high  
4
4
w
CLK low  
7
7
Data before LOAD↑  
CTEN before CLK↑  
D/U before CLK↑  
LOAD inactive before CLK↑  
Data after LOAD↑  
CTEN after CLK↑  
D/U after CLK↑  
4
4
6.5  
15  
10  
2
6.5  
15  
10  
2
t
t
Setup time  
Hold time  
ns  
ns  
su  
1
1
h
0
0
switching characteristics (see Note )  
V
C
R
= 5 V,  
V
C
R
= 4.5 V to 5.5 V,  
= 50 pF,  
CC  
L
L
CC  
L
L
= 50 pF,  
= 500 ,  
= 25°C  
FROM  
PARAMETER  
TO  
(OUTPUT)  
= 500,  
= MIN to MAX  
UNIT  
(INPUT)  
T
A
T
A
MIN  
90  
2.5  
5
TYP  
MAX  
MIN  
90  
2
MAX  
f
MHz  
ns  
max  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
4.8  
7
8
11.5  
12.5  
11  
8.5  
12  
CLK  
CLK  
Any Q  
MAX/MIN  
RCO  
5
6.5  
6
9.4  
8.9  
5.2  
4.8  
5.7  
5
6
13  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
6
12  
2.5  
3
7.5  
7.5  
7
2
8
CLK  
2.5  
2
8
2
7.8  
8
CTEN  
RCO  
3
7.5  
16  
3
8
13  
8
17.8  
11  
D/U  
RCO  
4.5  
4
8.1  
7.9  
7.5  
4.7  
8.9  
10.5  
10  
10.5  
9.8  
9.5  
7
4
3
11.3  
10  
D/U  
MAX/MIN  
Any Q  
3
3
2
1.5  
6.5  
5
7.5  
13  
A, B, C, or D  
A, B, C, or D  
A, B, C, or D  
LOAD  
6.5  
5.5  
6.5  
6
12  
13.6  
13  
15.4  
14  
MAX/MIN  
RCO  
6
15  
18.6  
13.5  
9.8  
12.1  
15.2  
14  
6
21.1  
15  
6
9.5  
7.7  
9.9  
12.3  
11.7  
16.8  
11.6  
6
4.5  
5.5  
5.5  
6
4
11.4  
13.1  
17  
Any Q  
5
5.5  
6
LOAD  
MAX/MIN  
RCO  
15.6  
23.2  
15.2  
8.5  
7.5  
19.9  
14  
8.5  
7
LOAD  
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.  
NOTE 2: Load circuits and waveforms are shown in Section 1.  
2–6  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
24-Jun-2005  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SN74F190AN  
OBSOLETE  
PDIP  
N
16  
TBD  
Call TI  
Call TI  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
IMPORTANT NOTICE  
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