SN74GTLPH306PWR [TI]
8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER; 8位LVTTL至GTLP总线收发器
| 型号： | SN74GTLPH306PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER |
| 文件： | 总12页 (文件大小：254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74GTLPH306
8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES284E – OCTOBER 1999 – REVISED AUGUST 2001
DGV, DW, OR PW PACKAGE
(TOP VIEW)
TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
OE
DIR
V
B1
1
2
3
4
5
6
7
8
9
24
23
22
21
V
CC
A1
REF
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
A2
A3
A4
GND
A5
A6
B2
20 B3
B4
LVTTL Interfaces Are 5-V Tolerant
Medium-Drive GTLP Outputs (50 mA)
LVTTL Outputs (–24 mA/24 mA)
19
18 GND
17 B5
16 B6
15 B7
14 B8
13 GND
GTLP Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
A7 10
A8 11
I
and Power-Up 3-State Support Hot
GND 12
off
Insertion
Bus Hold on A-Port Data Inputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description
The SN74GTLPH306 is a medium-drive, 8-bit bus transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. The device provides a high-speed interface between cards operating
at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster
than standard LVTTL or TTL) backplane operation is a direct result of GTLP’s reduced output swing (<1 V),
reduced input threshold levels, improved differential input, OEC circuitry, and TI-OPC circuitry. Improved
GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several
backplane models. The medium drive allows incident-wave switching in heavily loaded backplanes with
equivalent load impedance down to 19 Ω.
GTLP is the Texas Instruments (TI ) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard
JESD 8-3. The ac specification of the SN74GTLPH306 is given only at the preferred higher-noise-margin GTLP,
but the user has the flexibility of using this device at either GTL (V = 1.2 V and V
= 0.8 V) or GTLP
TT
REF
(V = 1.5 V and V
= 1 V) signal levels.
TT
REF
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. V
reference voltage.
is the B-port differential input
REF
This device is fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC, TI, and TI-OPC are trademarks of Texas Instruments.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH306
8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES284E – OCTOBER 1999 – REVISED AUGUST 2001
description (continued)
This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated
backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves
signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended.
When V
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to V
CC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74GTLPH306DW
SN74GTLPH306DWR
SN74GTLPH306PWR
SN74GTLPH306DGVR
SOIC – DW
GTLPH306
Tape and reel
Tape and reel
Tape and reel
–40°C to 85°C
TSSOP – PW
TVSOP – DGV
GH306
GH306
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
functional description
The SN74GTLPH306 is an 8-bit bus transceiver and is designed for asynchronous communication between
data buses. The device transmits data from the A port to the B port or from the B port to the A port, depending
on the logic level at the direction-control (DIR) input. OE can be used to disable the device so the buses are
effectively isolated. Data polarity is noninverting.
For A-to-B data flow, when OE is low and DIR is high, the B outputs take on the logic value of the A inputs. When
OE is high, the outputs are in the high-impedance state.
The data flow for B to A is similar to A to B, except OE and DIR are low.
FUNCTION TABLE
INPUTS
OUTPUT
MODE
Isolation
OE
H
DIR
X
Z
L
L
B data to A port
A data to B port
True transparent
L
H
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH306
8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES284E – OCTOBER 1999 – REVISED AUGUST 2001
logic diagram (positive logic)
24
DIR
1
OE
22
3
B1
A1
23
V
REF
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1): A port and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
B port and V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
REF
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Current into any output in the low state, I : A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Current into any A port output in the high state, I (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
Continuous current through each V
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θ (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
IK
I
Output clamp current, I
OK
O
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51-7.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH306
8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES284E – OCTOBER 1999 – REVISED AUGUST 2001
recommended operating conditions (see Notes 4 through 7)
MIN
3.15
1.14
1.35
0.74
0.87
NOM
3.3
1.2
1.5
0.8
1
MAX
3.45
1.26
1.65
0.87
1.1
UNIT
V
V
Supply voltage
V
CC
GTL
Termination voltage
V
V
V
V
V
TT
GTLP
GTL
V
V
V
V
Reference voltage
Input voltage
REF
GTLP
B port
V
TT
5.5
I
Except B port
B port
V
CC
V
+0.05
REF
High-level input voltage
Low-level input voltage
IH
IL
Except B port
B port
2
V
–0.05
REF
Except B port
0.8
–18
–24
24
I
I
Input clamp current
mA
mA
IK
High-level output current
A port
OH
OL
A port
I
Low-level output current
mA
B port
50
∆t/∆v
∆t/∆V
Input transition rise or fall rate
Power-up ramp rate
Outputs enabled
10
ns/V
µs/V
°C
20
CC
T
A
Operating free-air temperature
–40
85
NOTES: 4. All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS V
= 3.3 V first, I/O second, and
CC
V
CC
= 3.3 Vlast,becausetheBIASV
prechargecircuitryisdisabledwhenanyV
CC CC
pinisconnected.ThecontrolandV inputs
REF
can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection
sequence is acceptable, but generally, GND is connected first.
6.
7.
V
V
and R can be adjusted to accommodate backplane impedances if the dc recommended I
ratings are not exceeded.
can be adjusted to optimize noise margins, but normally is two-thirds V . TI-OPC circuitry is enabled in the A-to-B direction
TT
TT OL
REF
TT
and is activated when V > 0.7 V above V
minimize current drain.
. If operated in the A-to-B direction, V
should be set to within 0.6 V of V to
TT
TT
REF REF
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH306
8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES284E – OCTOBER 1999 – REVISED AUGUST 2001
electrical characteristics over recommended operating free-air temperature range for GTLP
(unless otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
V
V
= 3.15 V,
I = –18 mA
–1.2
V
IK
CC
I
= 3.15 V to 3.45 V,
I
I
I
I
I
I
I
I
= –100 µA
= –12 mA
= –24 mA
= 100 µA
= 12 mA
= 24 mA
= 40 mA
= 50 mA
V
–0.2
CC
OH
OH
OH
OL
OL
OL
OL
OL
CC
V
OH
A port
2.4
2
V
V
V
CC
V
CC
V
CC
= 3.15 V
= 3.15 V to 3.45 V,
= 3.15 V
0.2
0.4
0.5
0.4
0.55
±5
A port
B port
V
OL
V
CC
V
CC
= 3.15 V
= 3.45 V
V = 0 or V
I
A-port and
control inputs
CC
‡
I
I
V = 5.5 V
I
±20
±5
µA
V = 0 to 1.5 V
I
B port
§
I
I
I
I
A port
A port
A port
A port
V
CC
V
CC
V
CC
V
CC
= 3.15 V,
= 3.15 V,
= 3.45 V,
= 3.45 V,
V = 0.8 V
75
–75
µA
µA
µA
µA
BHL
BHH
I
¶
V = 2 V
I
#
V = 0 to V
I
500
BHLO
CC
CC
||
V = 0 to V
I
–500
BHHO
Outputs high
Outputs low
20
20
20
V
= 3.45 V, I = 0,
O
CC
I
A or B port
mA
V (A-port or control input) = V
or GND,
CC
I
CC
V (B port) = V or GND
I
TT
Outputs disabled
V
= 3.45 V, One A-port or control input at V
– 0.6 V,
CC
CC
1.5
mA
pF
∆I
CC
Other A-port or control inputs at V
or GND
CC
C
C
Control inputs
A port
V = 3.15 V or 0
I
4.5
7.5
7.5
5
9
9
i
V
= 3.15 V or 0
= 1.5 V or 0
O
O
pF
io
B port
V
†
‡
§
All typical values are at V
= 3.3 V, T = 25°C.
A
I
CC
For I/O ports, the parameter I includes the off-state output leakage current.
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
then raising it to V max.
IL
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
should be measured after lowering V to GND and
IN
IL
BHL
¶
should be measured after raising V to V
IN
and
CC
IH
BHH
then lowering it to V min.
IH
#
||
An external driver must source at least I
to switch this node from low to high.
BHLO
to switch this node from high to low.
An external driver must sink at least I
BHHO
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
hot-insertion specifications for A port over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
MAX
10
UNIT
µA
I
I
I
V
CC
V
CC
V
CC
= 0,
V or V = 0 to 5.5 V
off
I
O
= 0 to 1.5 V,
= 1.5 V to 0,
V
= 0.5 V to 3 V,
OE = 0
OE = 0
±30
±30
µA
OZPU
OZPD
O
O
V
= 0.5 V to 3 V,
µA
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH306
8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES284E – OCTOBER 1999 – REVISED AUGUST 2001
hot-insertion specifications for B port over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
MAX
10
UNIT
µA
I
I
I
V
CC
V
CC
V
CC
= 0,
V or V = 0 to 1.5 V
off
I
O
= 0 to 1.5 V,
= 1.5 V to 0,
V
= 0.5 V to 1.5 V,
OE = 0
OE = 0
±30
±30
µA
OZPU
OZPD
O
O
V
= 0.5 V to 1.5 V,
µA
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, V = 1.5 V and V
= 1 V for GTLP (see Figure 1)
TT
REF
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
MIN TYP
MAX
UNIT
t
t
t
t
t
t
t
t
t
t
t
t
1
1
1
1
7.5
7.5
8
PLH
PHL
en
dis
r
A
B
B
ns
ns
OE
8
Rise time, B outputs (20% to 80%)
2.2
2.1
4.1
3.3
ns
ns
ns
ns
Fall time, B outputs (80% to 20%)
Rise time, A outputs (10% to 90%)
Fall time, A outputs (90% to 10%)
f
r
f
1
1
1
1
7
7
8
8
PLH
PHL
en
dis
B
A
A
ns
ns
OE
†
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH306
8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES284E – OCTOBER 1999 – REVISED AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
1.5 V
25 Ω
6 V
Open
GND
S1
500 Ω
From Output
Under Test
TEST
S1
Open
6 V
From Output
Under Test
Test
Point
t
t
t
/t
PLH PHL
/t
C
= 50 pF
L
500 Ω
PLZ PZL
/t
(see Note A)
C
= 30 pF
(see Note A)
L
GND
PHZ PZH
LOAD CIRCUIT FOR A OUTPUTS
LOAD CIRCUIT FOR B OUTPUTS
3 V
0 V
1.5 V
1.5 V
Input
t
t
PHL
PLH
V
V
OH
1 V
1 V
Output
3 V
OL
Output
Control
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A port to B port)
0 V
3 V
t
t
PLZ
PZL
Output
Waveform 1
S1 at 6 V
1.5 V
0 V
1 V
1 V
1.5 V
Input
V
OL
+ 0.3 V
(see Note B)
V
OL
OH
t
t
PHL
t
t
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
– 0.3 V
1.5 V
1.5 V
Output
1.5 V
V
OL
≈0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to A port)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A port)
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, Z = 50 Ω, t ≈ 2 ns, t ≈ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH306
8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES284E – OCTOBER 1999 – REVISED AUGUST 2001
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The preceding switching characteristics table shows the switching characteristics of the device into a lumped load
(Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation
is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a resistor inductance
capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC
circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC
load, to help the designer better understand the performance of the GTLP device in this typical backplane. See
www.ti.com/sc/gtlp for more information.
1.5 V
1.5 V
Z
O
= 70 Ω
1.5 V
.25”
2”
2”
.25”
19 Ω
Conn.
Conn.
Conn.
Conn.
L
L
= 19 nH
From Output
Under Test
Test
Point
1”
1”
1”
1”
C
= 9 pF
L
Rcvr
Rcvr
Rcvr
Drvr
Slot 1
Slot 2
Slot 9
Slot 10
Figure 2. Medium-Drive Test Backplane
Figure 3. Medium-Drive RLC Network
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, V = 1.5 V and V
= 1 V for GTLP (see Figure 3)
TT
REF
FROM
(INPUT)
TO
(OUTPUT)
†
TYP
PARAMETER
UNIT
t
t
t
t
t
t
3.6
4.1
4.4
4.6
1.2
2.2
PLH
PHL
en
dis
r
A
B
B
ns
ns
OE
Rise time, B outputs (20% to 80%)
Fall time, B outputs (80% to 20%)
ns
ns
f
†
All typical values are at V
= 3.3 V, T = 25°C. All values are derived from TI-SPICE models.
CC
A
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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