SN74GTLPH3245 [TI]

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER; 32位LVTTL至GTLP可调节边沿速率总线收发器


型号：	SN74GTLPH3245
厂家：	TEXAS INSTRUMENTS
描述：	32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER 32位LVTTL至GTLP可调节边沿速率总线收发器总线收发器
文件：	总19页 (文件大小：435K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

www.ti.com

SCES291D–OCTOBER 1999–REVISED JUNE 2005

FEATURES

•

Variable Edge-Rate Control (ERC) Input

Selects GTLP Rise and Fall Times for Optimal

Data-Transfer Rate and Signal Integrity in

Distributed Loads

•

Member of the Texas Instruments Widebus+™

Family

TI-OPC™ Circuitry Limits Ringing on

Unevenly Loaded Backplanes

•

I_off, Power-Up 3-State, and BIAS V_CCSupport

Live Insertion

OEC™ Circuitry Improves Signal Integrity and

Reduces Electromagnetic Interference

•

Bus Hold on A-Port Data Inputs

Distributed V_CCand GND Pins Minimize

High-Speed Switching Noise

Bidirectional Interface Between GTLP Signal

Levels and LVTTL Logic Levels

•

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

•

LVTTL Interfaces Are 5-V Tolerant

High-Drive GTLP Outputs (100 mA)

LVTTL Outputs (–24 mA/24 mA)

DESCRIPTION/ORDERING INFORMATION

The SN74GTLPH3245 is a high-drive, 32-bit bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL

signal-level translation. It is partitioned as four 8-bit transceivers. The device provides a high-speed interface

between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed

(about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP's reduced

output swing (<1 V), reduced input threshold levels, improved differential input, OEC circuitry, and TI-OPC

circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and

tested using several backplane models. The high drive allows incident-wave switching in heavily loaded

backplanes with equivalent load impedance down to 11 Ω.

GTLP is the Texas Instruments (TI™) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard

JESD 8-3. The ac specification of the SN74GTLPH3245 is given only at the preferred higher noise-margin GTLP,

but the user has the flexibility of using this device at either GTL (V_TT= 1.2 V and V_REF= 0.8 V) or GTLP (V_TT

1.5 V and V_REF= 1 V) signal levels.

Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,

but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. V_REFis the B-port differential input

reference voltage.

This device is fully specified for live-insertion applications using I_off, power-up 3-state, and BIAS V_CC. The I_off

circuitry disables the outputs, preventing damaging current backflow through the device when it is powered

down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power

down, which prevents driver conflict. The BIAS V_CCcircuitry precharges and preconditions the B-port input/output

connections, preventing disturbance of active data on the backplane during card insertion or removal, and

permits true live-insertion capability.

This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated

backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal

integrity, which allows adequate noise margin to be maintained at higher frequencies.

High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC

input voltage between GND and V_CCadjusts the B-port output rise and fall times. This allows the designer to

optimize system data-transfer rate and signal integrity to the backplane load.

Active bus-hold circuitry is provided to hold unused or undriven LVTTL data inputs at a valid logic state. Use of

pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When V_CCis between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to V_CC

through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the

driver.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus+, TI-OPC, OEC, TI are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

www.ti.com

SCES291D–OCTOBER 1999–REVISED JUNE 2005

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

ORDERABLE PART NUMBER

TOP-SIDE MARKING

–40°C to 85°C

LFBGA – GKF Tape and reel

SN74GTLPH3245GKFR

GM45

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

www.ti.com

SCES291D–OCTOBER 1999–REVISED JUNE 2005

GKF PACKAGE

(TOP VIEW)

TERMINAL ASSIGNMENTS⁽¹⁾

1B2

1A3

GND

1A6

1A8

1ERC

2A2

2A4

GND

2A6

1A2

1A4

1A5

1A7

GND

2A1

2A3

2A5

2A7

3A1

3A2

3A4

3A5

3A7

GND

4A1

4A3

4A5

4A7

1A1

1B1

1B3

GND

1B6

1B8

1V_REF

2B2

2B4

GND

2B6

1DIR

GND

1V_CC

GND

1V_CC

GND

2A8

1OE

GND

1V_CC

GND

1V_CC

GND

2B8

1B4

1B5

1B7

1BIAS V_CC

2B1

2B3

2B5

2B7

2DIR

3DIR

GND

2V_CC

GND

2V_CC

GND

4A8

2OE

3OE

GND

2V_CC

GND

2V_CC

GND

4B8

3B1

3A3

GND

3A6

3A8

2ERC

4A2

4A4

GND

4A6

3B2

3B3

GND

3B6

3B8

2V_REF

4B2

4B4

GND

4B6

3B4

3B5

3B7

2BIAS V_CC

4B1

4B3

4B5

4DIR

4OE

4B7

(1) NC – No internal connection

SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

www.ti.com

SCES291D–OCTOBER 1999–REVISED JUNE 2005

<BR/>

FUNCTIONAL DESCRIPTION

The SN74GTLPH3245 is a high-drive (100-mA), 32-bit bus transceiver partitioned in four 8-bit segments and is

designed for asynchronous communication between data buses. The device transmits data from the A port to the

B port or from the B port to the A port, depending on the logic level at the direction-control (DIR) input. OE can

be used to disable the device so the buses effectively are isolated. Data polarity is noninverting.

For A-to-B data flow, when OE is low and DIR is high, the B outputs take on the logic value of the A inputs.

When OE is high, the outputs are in the high-impedance state.

The data flow for B to A is similar to that of A to B, except OE and DIR are low.

FUNCTION TABLES

<br/>

OUTPUT CONTROL

INPUTS

OUTPUT

MODE

Isolation

DIR

B data to A port

A data to B port

True transparent

<br/>

B-PORT EDGE-RATE CONTROL (ERC)

INPUT ERC

OUTPUT

B-PORT

EDGE RATE

LOGIC

LEVEL

NOMINAL

VOLTAGE

GND

Slow

Fast

V_CC

SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

www.ti.com

SCES291D–OCTOBER 1999–REVISED JUNE 2005

LOGIC DIAGRAM (POSITIVE LOGIC)⁽¹⁾

1DIR

1OE

1ERC

1A1

1B1

REF

To Seven Other Channels

2DIR

2A1

2OE

2B1

To Seven Other Channels

(1) 1V_CCand 1BIAS V_CCare associated with these channels.

SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

www.ti.com

SCES291D–OCTOBER 1999–REVISED JUNE 2005

LOGIC DIAGRAM (POSITIVE LOGIC) (CONTINUED)⁽¹⁾

3DIR

3OE

2ERC

3B1

3A1

REF

To Seven Other Channels

4DIR

4A1

4OE

4B1

To Seven Other Channels

(1) 2V_CCand 2BIAS V_CCare associated with these channels.

SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

www.ti.com

SCES291D–OCTOBER 1999–REVISED JUNE 2005

Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

V_CC

Supply voltage range

BIAS V_CC

–0.5

4.6

A-port, ERC, and control inputs

–0.5

4.6

V_I

Input voltage range⁽²⁾

B port and V_REF

A port

Voltage range applied to any output in the

high-impedance or power-off state

V_O

B port

4.6

A port

I_O

Current into any output in the low state

B port

200

Current into any A-port output in the high state⁽³⁾

Continuous current through each V_CCor GND

Input clamp current

°C/W

°C

±100

–50

I_IK

V_I< 0

V_O< 0

I_OK

θ_JA

T_stg

Output clamp current

Package thermal impedance⁽⁴⁾

Storage temperature range

–65

150

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(3) This current flows only when the output is in the high state and V_O> V_CC

(4) The package thermal impedance is calculated in accordance with JESD 51-7.

SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

www.ti.com

SCES291D–OCTOBER 1999–REVISED JUNE 2005

Recommended Operating Conditions^(1)(2)(3)(4)

MIN NOM

MAX

UNIT

V_CC

BIAS V_CC

Supply voltage

3.15

3.3

3.45

GTL

1.14

1.35

0.74

0.87

1.2

1.5

0.8

1.26

1.65

0.87

1.1

V_TT

V_REF

V_I

Termination voltage

GTLP

GTL

Reference voltage

Input voltage

GTLP

B port

V_TT

5.5

Except B port

V_CC

B port

V_REF+ 0.05

V_CC– 0.6

V_IH

High-level input voltage

Low-level input voltage

ERC

V_CC

5.5

Except B port and ERC

B port

V_REF– 0.05

V_IL

ERC

GND

0.6

0.8

–18

–24

Except B port and ERC

I_IK

Input clamp current

I_OH

High-level output current

A port

I_OL

Low-level output current

B port

100

∆t/∆v

∆t/∆V_CC

T_A

Input transition rise or fall rate

Power-up ramp rate

Outputs enabled

ns/V

µs/V

°C

Operating free-air temperature

–40

(1) All unused inputs of the device must be held at V_CCor GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

(2) Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS V_CC= 3.3 V first, I/O second, and V_CC= 3.3 V

last, because the BIAS V_CCprecharge circuitry is disabled when any V_CCpin is connected. The control and V_REFinputs can be

connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is

acceptable, but generally, GND is connected first.

(3) V_TTand R_TTcan be adjusted to accommodate backplane impedances if the dc recommended I_OLratings are not exceeded.

(4) V_REFcan be adjusted to optimize noise margins, but normally is two-thirds V_TT. TI-OPC circuitry is enabled in the A-to-B direction and is

activated when V_TT> 0.7 V above V_REF. If operated in the A-to-B direction, V_REFshould be set to within 0.6 V of V_TTto minimize current

drain.

SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

www.ti.com

SCES291D–OCTOBER 1999–REVISED JUNE 2005

Electrical Characteristics

over recommended operating free-air temperature range for GTLP (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP⁽¹⁾

MAX

UNIT

V_IK

V_CC= 3.15 V,

I_I= –18 mA

I_OH= –100 µA

I_OH= –12 mA

I_OH= –24 mA

I_OL= 100 µA

I_OL= 12 mA

I_OL= 24 mA

I_OL= 10 mA

I_OL= 64 mA

I_OL= 100 mA

V_I= 0 or V_CC

V_I= 5.5 V

–1.2

V_CC= 3.15 V to 3.45 V,

V_CC– 0.2

V_OH

A port

2.4

V_CC= 3.15 V

V_CC= 3.15 V to 3.45 V,

V_CC= 3.15 V

0.2

0.4

A port

0.5

V_OL

0.2

B port

V_CC= 3.15 V

V_CC= 3.45 V

0.4

0.55

±10

±20

±10

A-port and

control inputs

I_I⁽²⁾

µA

B port

A port

V_I= 0 to 1.5 V

V_I= 0.8 V

(3)

(4)

I_BHL

I_BHH

V_CC= 3.15 V,

V_CC= 3.45 V,

–75

µA

V_I= 2 V

(5)

I_BHLO

V_I= 0 to V_CC

Outputs high

Outputs low

Outputs disabled

500

(6)

I_BHHO

A port

–500

V_CC= 3.45 V, I_O= 0,

V_I(A-port or control input) = V_CCor GND,

V_I(B port) = V_TTor GND

I_CC

A or B port

V_CC= 3.45 V, One A-port or control input at V_CC– 0.6 V,

Other A-port or control inputs at V_CCor GND

(7)

∆I_CC

1.5

C_i

Control inputs

A port

V_I= 3.15 V or 0

V_O= 3.15 V or 0

V_O= 1.5 V or 0

6.5

9.5

7.5

C_io

B port

(1) All typical values are at V_CC= 3.3 V, T_A= 25°C.

(2) For I/O ports, the parameter I_Iincludes the off-state output leakage current.

(3) The bus-hold circuit can sink at least the minimum low sustaining current at V_ILmax. I_BHLshould be measured after lowering V_INto GND

and then raising it to V_ILmax.

(4) The bus-hold circuit can source at least the minimum high sustaining current at V_IHmin. I_BHHshould be measured after raising V_INto V_CC

and then lowering it to V_IHmin.

(5) An external driver must source at least I_BHLOto switch this node from low to high.

(6) An external driver must sink at least I_BHHOto switch this node from high to low.

(7) This is the increase in supply current for each input that is at the specified TTL voltage level rather than V_CCor GND.

Hot-Insertion Specifications for A Port

over recommended operating free-air temperature range

PARAMETER

I_off

TEST CONDITIONS

BIAS V_CC= 0,

MIN

MAX UNIT

V_CC= 0,

V_Ior V_O= 0 to 5.5 V

OE = 0

±30

µA

I_OZPU

V_CC= 0 to 1.5 V,

V_CC= 1.5 V to 0,

V_O= 0.5 V to 3 V,

I_OZPD

OE = 0

SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

www.ti.com

SCES291D–OCTOBER 1999–REVISED JUNE 2005

Live-Insertion Specifications for B Port

over recommended operating free-air temperature range

PARAMETER

I_off

TEST CONDITIONS

BIAS V_CC= 0,

MIN

MAX UNIT

V_CC= 0,

V_Ior V_O= 0 to 1.5 V

±30

µA

I_OZPU

V_CC= 0 to 1.5 V,

V_CC= 1.5 V to 0,

V_CC= 0 to 3.15 V

V_CC= 3.15 V to 3.45 V

V_CC= 0,

BIAS V_CC= 0,

V_O= 0.5 V to 1.5 V, OE = 0

I_OZPD

I_CC(BIAS V_CC

)

BIAS V_CC= 3.15 V to 3.45 V,

V_O(B port) = 0 to 1.5 V

V_O

I_O

BIAS V_CC= 3.3 V,

I_O= 0

0.95

–1

1.05

V_CC= 0,

BIAS V_CC= 3.15 V to 3.45 V,

V_O(B port) = 0.6 V

µA

Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature,

V_TT= 1.5 V and V_REF= 1 V for GTLP (see Figure 1)

FROM

(INPUT)

(OUTPUT)

PARAMETER

EDGE RATE⁽¹⁾

MIN TYP⁽²⁾

MAX UNIT

t_PLH

t_PHL

t_PLH

t_PHL

t_en

3.9

3.1

2.6

2.1

4.1

7.2

Slow

8.4

5.7

Fast

Slow

Fast

5.8

7.3

t_dis

9.4

t_en

2.9

5.9

t_dis

6.9

Slow

Fast

Slow

Fast

t_r

t_f

Rise time, B outputs (20% to 80%)

Fall time, B outputs (80% to 20%)

1.5

2.5

0.5

1.2

1.1

1.7

t_PLH

t_PHL

t_en

6.7

4.5

6.3

t_dis

5.1

(1) Slow (ERC = GND) and Fast (ERC = V_CC

)

(2) All typical values are at V_CC= 3.3 V, T_A= 25°C.

SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

www.ti.com

SCES291D–OCTOBER 1999–REVISED JUNE 2005

PARAMETER MEASUREMENT INFORMATION

1.5 V

6 V

Open

GND

500 Ω

From Output

Under Test

12.5 Ω

From Output

Under Test

TEST

Open

6 V

Test

Point

C = 50 pF

(see Note A)

PLH PHL

500 Ω

PLZ PZL

C = 30 pF

(see Note A)

GND

PHZ PZH

LOAD CIRCUIT FOR A OUTPUTS

LOAD CIRCUIT FOR B OUTPUTS

3 V

0 V

1.5 V

Input

PHL

PLH

1 V

Output

3 V

Output

Control

1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

(A port to B port)

0 V

3 V

PLZ

PZL

Output

Waveform 1

S1 at 6 V

1.5 V

0 V

1 V

1.5 V

Input

+ 0.3 V

(see Note B)

PHL

PLH

PZH

PHZ

Output

Waveform 2

S1 at GND

− 0.3 V

1.5 V

Output

≈0 V

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

(B port to A port)

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

(A port)

NOTES: A. C includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, Z = 50 Ω, t ≈ 2 ns, t ≈ 2 ns.

D. The outputs are measured one at a time, with one transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

www.ti.com

SCES291D–OCTOBER 1999–REVISED JUNE 2005

Distributed-Load Backplane Switching Characteristics

The preceding switching characteristics table shows the switching characteristics of the device into a lumped

load (Figure 1). However, the designer's backplane application probably is a distributed load. The physical

representation is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a

resistor inductance capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum

performance in this RLC circuit. The following switching characteristics table shows the switching characteristics

of the device into the RLC load, to help the designer better understand the performance of the GTLP device in

this typical backplane. See www.ti.com/sc/gtlp for more information.

1.5 V

= 50 Ω

0.25”

1”

0.25”

Conn.

1”

Rcvr

Drvr

Slot 1

Slot 2

Slot 19

Slot 20

Figure 2. High-Drive Test Backplane

1.5 V

11 Ω

L = 14 nH

From Output

Under Test

Test

Point

C = 18 pF

Figure 3. High-Drive RLC Network

SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

www.ti.com

SCES291D–OCTOBER 1999–REVISED JUNE 2005

Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature,

V_TT= 1.5 V and V_REF= 1 V for GTLP (see Figure 3)

FROM

(INPUT)

(OUTPUT)

PARAMETER

EDGE RATE⁽¹⁾

TYP⁽²⁾

UNIT

t_PLH

t_PHL

t_PLH

t_PHL

t_en

4.9

3.7

5.1

5.4

4.1

Slow

Fast

Slow

Fast

t_dis

t_en

t_dis

Slow

Fast

Slow

Fast

t_r

t_f

Rise time, B outputs (20% to 80%)

Fall time, B outputs (80% to 20%)

1.2

2.5

1.8

(1) Slow (ERC = GND) and Fast (ERC = V_CC

)

(2) All typical values are at V_CC= 3.3 V, T_A= 25°C. All values are derived from TI-SPICE models.

PACKAGE OPTION ADDENDUM

www.ti.com

20-Jul-2011

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

SN74GTLPH3245GKFR

SN74GTLPH3245ZKFR

NRND

BGA

MICROSTAR

GKF

ZKF

114

1000

TBD

SNPB

Level-2-235C-1 YEAR

ACTIVE

LFBGA

Green (RoHS

& no Sb/Br)

SNAGCU Level-3-260C-168 HR

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jul-2011

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

1000

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN74GTLPH3245GKFR BGA MI

GKF

ZKF

114

330.0

24.4

5.8

16.3

1.8

8.0

24.0

CROSTA

SN74GTLPH3245ZKFR LFBGA

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jul-2011

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN74GTLPH3245GKFR BGA MICROSTAR

SN74GTLPH3245ZKFR LFBGA

GKF

ZKF

114

1000

333.2

345.9

31.8

Pack Materials-Page 2

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SN74GTLPH3245 [TI]

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