SN74HC373PWRG4 [TI]
Octal Transparent D-Type Latches With 3-State Outputs 20-TSSOP -40 to 85;型号: | SN74HC373PWRG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | Octal Transparent D-Type Latches With 3-State Outputs 20-TSSOP -40 to 85 驱动 光电二极管 逻辑集成电路 |
文件: | 总23页 (文件大小:1176K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SCLS140D − DECEMBER 1982 − REVISED AUGUST 2003
D
D
Wide Operating Voltage Range of 2 V to 6 V
D
6-mA Output Drive at 5 V
High-Current 3-State True Outputs Can
Drive Up To 15 LSTTL Loads
D
D
Low Input Current of 1 µA Max
Eight High-Current Latches in a Single
Package
D
Low Power Consumption, 80-µA Max I
CC
D
Typical t = 13 ns
pd
D
Full Parallel Access for Loading
SN54HC373 . . . J OR W PACKAGE
SN74HC373 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
SN54HC373 . . . FK PACKAGE
(TOP VIEW)
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
8Q
8D
1
2
3
4
5
6
7
8
9
20
19
18
3
2
1
20 19
18
8D
7D
7Q
2D
2Q
3Q
3D
4D
4
5
6
7
8
17
16
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 LE
15 6Q
14
9 10 11 12 13
6D
GND 10
description/ordering information
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight latches of the ’HC373 devices are transparent D-type latches. While the latch-enable (LE) input is
high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that
were set up at the D inputs.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
Tube of 20
Tube of 25
Reel of 2000
Reel of 2000
Reel of 2000
Tube of 70
Reel of 2000
Reel of 250
Tube of 20
Tube of 85
Tube of 55
SN74HC373N
SN74HC373N
SN74HC373DW
SN74HC373DWR
SN74HC373NSR
SN74HC373DBR
SN74HC373PW
SN74HC373PWR
SN74HC373PWT
SNJ54HC373J
SOIC − DW
HC373
SOP − NS
HC373
HC373
−40°C to 85°C
SSOP − DB
TSSOP − PW
HC373
CDIP − J
CFP − W
LCCC − FK
SNJ54HC373J
SNJ54HC373W
SNJ54HC373FK
−55°C to 125°C
SNJ54HC373W
SNJ54HC373FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
ꢉ ꢗ ꢢ ꢚ ꢙꢥ ꢠꢟ ꢝꢞ ꢟꢙ ꢛꢢ ꢤꢖ ꢜꢗ ꢝ ꢝꢙ ꢬꢔ ꢌꢑ ꢎꢍ ꢭ ꢑꢆꢮꢂ ꢆꢂꢈ ꢜꢤꢤ ꢢꢜ ꢚ ꢜ ꢛꢡ ꢝꢡꢚ ꢞ ꢜ ꢚ ꢡ ꢝꢡ ꢞꢝꢡ ꢥ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢆꢈ ꢀꢁ ꢇ ꢃ ꢄꢅꢆ ꢇ ꢆ
ꢉꢅ ꢊꢋ ꢌ ꢊ ꢍ ꢋꢁ ꢀꢎꢋꢍ ꢏꢁ ꢊ ꢐꢑꢊ ꢒ ꢎꢏ ꢌꢋꢊꢅ ꢄꢏꢀ
ꢓꢔ ꢊ ꢄ ꢆ ꢑꢀꢊꢋꢊ ꢏ ꢉꢕꢊ ꢎ ꢕꢊꢀ
SCLS140D − DECEMBER 1982 − REVISED AUGUST 2003
description/ordering information (continued)
An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or
the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are off.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
logic diagram (positive logic)
1
OE
11
LE
C1
1D
2
1Q
3
1D
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCLS140D − DECEMBER 1982 − REVISED AUGUST 2003
recommended operating conditions (see Note 3)
SN54HC373
MIN NOM
SN74HC373
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
2
1.5
5
6
2
1.5
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
= 4.5 V
= 6 V
3.15
4.2
3.15
4.2
High-level input voltage
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
= 4.5 V
= 6 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
0
0
V
V
V
V
I
CC
CC
Output voltage
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
1000
500
400
125
1000
500
400
85
= 4.5 V
= 6 V
∆t/∆v
Input transition rise/fall time
ns
T
A
Operating free-air temperature
−55
−40
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC373
SN74HC373
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
4.4
I
= −20 µA
OH
5.9
V
V = V or V
IH
V
OH
OL
I
IL
IL
I
I
= −6 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
3.84
5.34
OH
= −7.8 mA
OH
2 V
0.002
0.001
0.001
0.17
0.15
0.1
0.1
0.1
0.1
0.26
0.26
100
0.5
8
0.1
0.1
0.1
0.1
4.5 V
6 V
I
= 20 µA
OL
0.1
0.1
V
V = V or V
V
I
IH
I
I
= 6 mA
4.5 V
6 V
0.4
0.33
0.33
1000
5
OL
= 7.8 mA
0.4
OL
I
I
I
V = V
I
or 0
6 V
1000
10
nA
µA
µA
pF
I
CC
V
O
= V
or 0
6 V
0.01
OZ
CC
CC
V = V
I
or 0,
I
O
= 0
6 V
160
10
80
CC
C
2 V to 6 V
3
10
10
i
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢆꢈ ꢀꢁ ꢇ ꢃ ꢄꢅꢆ ꢇ ꢆ
ꢉꢅ ꢊꢋ ꢌ ꢊ ꢍ ꢋꢁ ꢀꢎꢋꢍ ꢏꢁ ꢊ ꢐꢑꢊ ꢒ ꢎꢏ ꢌꢋꢊꢅ ꢄꢏꢀ
ꢓꢔ ꢊ ꢄ ꢆ ꢑꢀꢊꢋꢊ ꢏ ꢉꢕꢊ ꢎ ꢕꢊꢀ
SCLS140D − DECEMBER 1982 − REVISED AUGUST 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC373
SN74HC373
A
V
UNIT
CC
MIN
80
16
14
50
10
9
MAX
MIN
120
24
MAX
MIN
100
20
MAX
2 V
4.5 V
6 V
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
20
17
2 V
75
63
4.5 V
6 V
15
13
ns
ns
13
11
2 V
20
10
10
26
24
4.5 V
6 V
13
12
13
12
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
58
15
13
73
18
15
65
17
14
50
15
13
28
8
SN54HC373
SN74HC373
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
150
30
MIN
MAX
225
45
MIN
MAX
190
38
2 V
4.5 V
6 V
D
Q
26
38
32
t
pd
ns
2 V
175
35
265
53
220
44
4.5 V
6 V
LE
OE
OE
Any Q
Any Q
Any Q
Any Q
30
45
38
2 V
150
30
225
45
190
38
4.5 V
6 V
t
t
t
ns
ns
ns
en
dis
t
26
38
32
2 V
150
30
225
45
190
38
4.5 V
6 V
26
38
32
2 V
60
90
75
4.5 V
6 V
12
18
15
6
10
15
13
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS140D − DECEMBER 1982 − REVISED AUGUST 2003
switching characteristics over recommended operating free-air temperature range, C = 150 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
82
SN54HC373
SN74HC373
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
200
40
MIN
MAX
300
60
MIN
MAX
250
50
2 V
4.5 V
6 V
22
D
Q
19
34
51
43
t
pd
ns
2 V
100
24
225
45
335
67
285
57
4.5 V
6 V
LE
OE
Any Q
Any Q
Any Q
20
38
57
48
2 V
90
200
40
300
60
250
50
4.5 V
6 V
23
t
t
ns
ns
en
19
34
51
43
2 V
45
210
42
315
63
265
53
4.5 V
6 V
17
t
13
36
53
45
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance per latch
No load
100
pF
pd
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢆꢈ ꢀꢁ ꢇ ꢃ ꢄꢅꢆ ꢇ ꢆ
ꢉꢅ ꢊꢋ ꢌ ꢊ ꢍ ꢋꢁ ꢀꢎꢋꢍ ꢏꢁ ꢊ ꢐꢑꢊ ꢒ ꢎꢏ ꢌꢋꢊꢅ ꢄꢏꢀ
ꢓꢔ ꢊ ꢄ ꢆ ꢑꢀꢊꢋꢊ ꢏ ꢉꢕꢊ ꢎ ꢕꢊꢀ
SCLS140D − DECEMBER 1982 − REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
PARAMETER
R
C
L
S1
S2
L
50 pF
or
150 pF
t
Open
Closed
Closed
Open
PZH
S1
S2
Test
Point
t
t
1 kΩ
1 kΩ
en
R
t
t
t
L
PZL
PHZ
PLZ
From Output
Under Test
Open
Closed
Open
50 pF
C
dis
L
Closed
(see Note A)
50 pF
or
150 pF
t
or t
−−
Open
Open
pd
t
LOAD CIRCUIT
V
CC
Reference
Input
50%
V
CC
0 V
High-Level
Pulse
50%
50%
t
t
h
su
0 V
V
CC
t
Data
Input
w
90%
90%
50%
10%
50%
10%
V
CC
Low-Level
Pulse
0 V
50%
50%
t
t
f
r
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
Output
V
CC
V
CC
Control
(Low-Level
Enabling)
Input
50%
50%
50%
50%
0 V
V
0 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
OH
≈V
CC
50%
≈V
CC
Output
Waveform 1
(See Note B)
In-Phase
Output
90%
t
50%
10%
50%
10%
10%
t
V
OL
V
OL
t
r
f
f
t
t
t
PZH
PHZ
PHL
90%
PLH
V
V
OH
V
Output
Waveform 2
(See Note B)
OH
90%
t
90%
Out-of-
Phase
Output
50%
10%
50%
10%
50%
≈0 V
OL
t
r
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
PHL
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
5962-8407201VRA
ACTIVE
CDIP
CFP
J
20
20
20
1
TBD
TBD
TBD
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
5962-8407201VR
A
SNV54HC373J
5962-8407201VSA
84072012A
ACTIVE
ACTIVE
W
1
1
A42
-55 to 125
-55 to 125
5962-8407201VS
A
SNV54HC373W
LCCC
FK
POST-PLATE
84072012A
SNJ54HC
373FK
8407201RA
8407201SA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CDIP
CFP
J
W
FK
J
20
20
20
20
20
20
20
1
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
8407201RA
SNJ54HC373J
8407201SA
SNJ54HC373W
JM38510/65403B2A
JM38510/65403BRA
M38510/65403B2A
M38510/65403BRA
SN54HC373J
LCCC
CDIP
LCCC
CDIP
CDIP
POST-PLATE
A42
JM38510/
65403B2A
JM38510/
65403BRA
FK
J
POST-PLATE
A42
JM38510/
65403B2A
JM38510/
65403BRA
J
TBD
TBD
A42
SN54HC373J
SN74HC373DBLE
SN74HC373DBR
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
20
20
Call TI
Call TI
-40 to 85
-40 to 85
2000
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
HC373
HC373
HC373
HC373
HC373
SN74HC373DW
SN74HC373DWE4
SN74HC373DWG4
SN74HC373DWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
20
20
20
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
25
Green (RoHS
& no Sb/Br)
25
Green (RoHS
& no Sb/Br)
2000
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
SN74HC373DWRE4
SN74HC373DWRG4
SN74HC373N
ACTIVE
SOIC
SOIC
PDIP
DW
20
20
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
HC373
ACTIVE
ACTIVE
DW
N
2000
20
Green (RoHS
& no Sb/Br)
-40 to 85
HC373
Pb-Free
(RoHS)
-40 to 85
SN74HC373N
SN74HC373N3
SN74HC373NE4
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
20
20
TBD
Call TI
Call TI
-40 to 85
-40 to 85
20
2000
2000
70
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74HC373N
HC373
SN74HC373NSR
SN74HC373NSRE4
SN74HC373PW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SO
NS
NS
20
20
20
20
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
SO
Green (RoHS
& no Sb/Br)
HC373
TSSOP
TSSOP
TSSOP
PW
PW
PW
Green (RoHS
& no Sb/Br)
HC373
SN74HC373PWE4
SN74HC373PWG4
70
Green (RoHS
& no Sb/Br)
HC373
70
Green (RoHS
& no Sb/Br)
HC373
SN74HC373PWLE
SN74HC373PWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
PW
20
20
TBD
Call TI
Call TI
-40 to 85
-40 to 85
2000
2000
2000
250
250
1
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
HC373
HC373
HC373
HC373
HC373
SN74HC373PWRE4
SN74HC373PWRG4
SN74HC373PWT
SN74HC373PWTE4
SNJ54HC373FK
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
LCCC
PW
PW
PW
PW
FK
20
20
20
20
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
POST-PLATE
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-55 to 125
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TBD
84072012A
SNJ54HC
373FK
SNJ54HC373J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
8407201RA
SNJ54HC373J
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Orderable Device
SNJ54HC373W
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
8407201SA
SNJ54HC373W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC373, SN54HC373-SP, SN74HC373 :
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Catalog: SN74HC373, SN54HC373
•
Military: SN54HC373
•
Space: SN54HC373-SP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
•
•
Military - QML certified for Military and Defense Applications
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC373DBR
SN74HC373DWR
SN74HC373NSR
SN74HC373PWR
SN74HC373PWT
SSOP
SOIC
DB
DW
NS
20
20
20
20
20
2000
2000
2000
2000
250
330.0
330.0
330.0
330.0
330.0
16.4
24.4
24.4
16.4
16.4
8.2
10.8
8.2
7.5
13.3
13.0
7.1
2.5
2.7
2.5
1.6
1.6
12.0
12.0
12.0
8.0
16.0
24.0
24.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
SO
TSSOP
TSSOP
PW
PW
6.95
6.95
7.1
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74HC373DBR
SN74HC373DWR
SN74HC373NSR
SN74HC373PWR
SN74HC373PWT
SSOP
SOIC
DB
DW
NS
20
20
20
20
20
2000
2000
2000
2000
250
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
45.0
45.0
38.0
38.0
SO
TSSOP
TSSOP
PW
PW
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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