SN74HC590AN3 [TI]
8-BIT BINARY COUNTERS WITH 3-STATE OUTPUT REGISTERS; 8位二进制计数器具有三态输出寄存器
| 型号： | SN74HC590AN3 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT BINARY COUNTERS WITH 3-STATE OUTPUT REGISTERS |
| 文件： | 总19页 (文件大小：582K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢈ ꢉ ꢀꢁꢊ ꢃꢄ ꢅꢂ ꢆꢇ ꢈ
ꢋ ꢌꢍꢎ ꢏ ꢍꢎ ꢁꢈꢐꢑ ꢅ ꢒꢓ ꢁ ꢏꢔ ꢐꢀ
ꢕ ꢎꢏ ꢄ ꢖ ꢌꢀꢏꢈꢏ ꢔ ꢒ ꢓꢏ ꢗꢓꢏ ꢐꢔꢘ ꢎ ꢀ ꢏꢔ ꢐꢀ
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
D
D
2-V to 6-V V
Operation
D
D
D
D
6-mA Output Drive at 5 V
Low Input Current of 1 µA Max
8-Bit Counter With Register
Counter Has Direct Clear
CC
High-Current 3-State Parallel Register
Outputs Can Drive Up To 15 LSTTL Loads
D
Low Power Consumption, 80-µA Max I
Typical t = 14 ns
pd
CC
D
SN54HC590A . . . J OR W PACKAGE
SN74HC590A . . . D, DW, OR N PACKAGE
(TOP VIEW)
SN54HC590A . . . FK PACKAGE
(TOP VIEW)
Q
Q
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
B
3
2
1
20 19
18
Q
C
D
A
Q
OE
RCLK
NC
CCKEN
CCLK
4
5
6
7
8
D
Q
OE
Q
17
16
15
14
E
Q
RCLK
E
NC
Q
12 CCKEN
F
Q
F
11
10
9
Q
CCLK
CCLR
RCO
G
Q
G
Q
9 10 11 12 13
H
GND
NC − No internal connection
description/ordering information
The ’HC590A devices contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register
has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary
counter features direct clear (CCLR) and count-enable (CCKEN) inputs. A ripple-carry output (RCO) is provided
for cascading. Expansion is accomplished easily for two stages by connecting RCO of the first stage to CCKEN
of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage
to the counter clock (CCLK) input of the following stage.
CCLK and the register clock (RCLK) inputs are positive-edge triggered. If both clocks are connected together,
the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock
enable.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
SOIC − D
Tube of 25
Tube of 40
Reel of 2500
Reel of 250
Tube of 40
Reel of 2000
Tube of 25
Tube of 150
Tube of 55
SN74HC590AN
SN74HC590AD
SN74HC590ADR
SN74HC590ADT
SN74HC590ADW
SN74HC590ADWR
SNJ54HC590AJ
SNJ54HC590AW
SNJ54HC590AFK
SN74HC590AN
HC590A
−40°C to 85°C
SOIC − DW
HC590A
CDIP − J
CFP − W
LCCC - FK
SNJ54HC590AJ
SNJ54HC590AW
SNJ54HC590AFK
−55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
ꢒ ꢛ ꢦ ꢞ ꢝꢩ ꢤꢣ ꢡꢢ ꢣꢝ ꢟꢦ ꢨꢚ ꢠꢛ ꢡ ꢡꢝ ꢰꢎ ꢱꢌ ꢗꢐ ꢲ ꢌꢖꢋꢂ ꢖꢂꢉ ꢠꢨꢨ ꢦꢠ ꢞ ꢠ ꢟꢥ ꢡꢥꢞ ꢢ ꢠ ꢞ ꢥ ꢡꢥ ꢢꢡꢥ ꢩ
ꢤ ꢛꢨ ꢥꢢꢢ ꢝ ꢡꢫꢥ ꢞ ꢭꢚ ꢢꢥ ꢛ ꢝꢡꢥ ꢩꢪ ꢒ ꢛ ꢠꢨ ꢨ ꢝ ꢡꢫꢥ ꢞ ꢦꢞ ꢝ ꢩꢤꢣ ꢡꢢ ꢉ ꢦꢞ ꢝ ꢩꢤꢣ ꢡꢚꢝ ꢛ
ꢦ ꢞ ꢝꢣꢥ ꢢꢢꢚ ꢛꢯ ꢩ ꢝꢥꢢ ꢛ ꢝꢡ ꢛ ꢥꢣꢥꢢ ꢢꢠꢞ ꢚ ꢨꢮ ꢚ ꢛꢣꢨ ꢤ ꢩꢥ ꢡꢥꢢ ꢡꢚꢛ ꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟꢥ ꢡꢥꢞ ꢢ ꢪ
ꢗꢞ ꢝ ꢩꢤꢣ ꢡ ꢢ ꢣ ꢝꢛ ꢜꢝ ꢞ ꢟ ꢡ ꢝ ꢢ ꢦꢥ ꢣ ꢚꢜ ꢚꢣꢠ ꢡꢚ ꢝꢛꢢ ꢦꢥ ꢞ ꢡꢫ ꢥ ꢡꢥ ꢞ ꢟꢢ ꢝꢜ ꢏꢥꢬ ꢠꢢ ꢎꢛꢢ ꢡꢞ ꢤꢟ ꢥꢛꢡ ꢢ
ꢢ ꢡ ꢠ ꢛꢩ ꢠ ꢞꢩ ꢭ ꢠ ꢞꢞ ꢠ ꢛ ꢡꢮꢪ ꢗꢞ ꢝ ꢩꢤꢣ ꢡꢚꢝꢛ ꢦꢞ ꢝꢣ ꢥꢢ ꢢꢚ ꢛꢯ ꢩꢝꢥ ꢢ ꢛꢝꢡ ꢛꢥ ꢣꢥ ꢢꢢ ꢠꢞ ꢚꢨ ꢮ ꢚꢛꢣ ꢨꢤꢩ ꢥ
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢂꢆ ꢇꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢂ ꢆ ꢇ ꢈ
ꢋꢌ ꢍꢎ ꢏ ꢍ ꢎ ꢁꢈ ꢐꢑ ꢅꢒ ꢓꢁ ꢏꢔ ꢐꢀ
ꢕꢎ ꢏ ꢄ ꢖ ꢌꢀꢏꢈꢏ ꢔ ꢒꢓꢏ ꢗꢓ ꢏ ꢐꢔ ꢘ ꢎꢀ ꢏꢔ ꢐꢀ
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
timing diagram
OE
CCLR
CCKEN
CCLK
RCLK
COUNTER
(internal)
Don’t
Care
Hex 01
Hex 02
Hex 03
Hex 04
Hex 05
Hex FD
Hex FE
Hex 05
Hex FF
Hex 00
Hex01
Hex 00
Hex 00
Hi-Z
Don’t
Care
Q −Q
Hex 00
Hex 01
Hex 01
A
H
RCO
TIMING SEQUENCE
1. Clear Counter (asynchronous).
2. Count up: 0x01. Store 0x00 in register.
3. Inhibit counter clock (CCKEN = HIGH). Store 0x01 in register.
4. Count 0x02, 0x03.
5. 3-state the outputs
6. Count up: 0x04
7. Enable outputs.
8. Continue up: 0x05
9. Store 0x05 in register.
10.Continue counting: 0x06...0xFD, 0xFE, 0xFF, 0x00, etc.
11. Store 0x00 in register.
2
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ꢋ ꢌꢍꢎ ꢏ ꢍꢎ ꢁꢈꢐꢑ ꢅ ꢒꢓ ꢁ ꢏꢔ ꢐꢀ
ꢕ ꢎꢏ ꢄ ꢖ ꢌꢀꢏꢈꢏ ꢔ ꢒ ꢓꢏ ꢗꢓꢏ ꢐꢔꢘ ꢎ ꢀ ꢏꢔ ꢐꢀ
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
14
OE
13
RCLK
12
CCKEN
9
RCO
11
CCLK
15
1R
C1
1S
Q
A
T
T
T
10
CCLR
R
R
R
1
1R
C1
1S
Q
Q
Q
B
C
D
2
1R
C1
1S
3
4
5
1R
C1
1S
T
T
T
R
R
R
1R
C1
1S
Q
Q
E
F
1R
C1
1S
6
7
1R
C1
1S
Q
Q
T
T
G
H
R
1R
C1
1S
R
Pin numbers shown are for the D, DW, J, N, and W packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢂꢆ ꢇꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢂ ꢆ ꢇ ꢈ
ꢋꢌ ꢍꢎ ꢏ ꢍ ꢎ ꢁꢈ ꢐꢑ ꢅꢒ ꢓꢁ ꢏꢔ ꢐꢀ
ꢕꢎ ꢏ ꢄ ꢖ ꢌꢀꢏꢈꢏ ꢔ ꢒꢓꢏ ꢗꢓ ꢏ ꢐꢔ ꢘ ꢎꢀ ꢏꢔ ꢐꢀ
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC590A
MIN NOM MAX
SN74HC590A
UNIT
MIN NOM
MAX
V
V
Supply voltage
2
1.5
5
6
2
1.5
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
= 4.5 V
= 6 V
3.15
4.2
3.15
4.2
High-level input voltage
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
= 4.5 V
= 6 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
0
0
V
V
V
V
I
CC
CC
Output voltage
V
CC
O
CC
V
CC
V
CC
V
CC
= 2 V
1000
500
400
125
1000
500
400
85
‡
= 4.5 V
= 6 V
t
Input transition (rise and fall) time
Operating free-air temperature
ns
t
T
A
−55
−40
°C
‡
If this device is used in the threshold region (from V max = 0.5 V to V min = 1.5 V), there is a potential to go into the wrong state from induced
IL IH
grounding, causing double clocking. Operating with the inputs at t = 1000 ns and V
= 2 V does not damage the device; however, functionally,
t
CC
the CCLK and RCLK inputs are not ensured while in the shift, count, or toggle operating modes.
NOTE 3: All unused inputs of the device must be held at V or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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ꢋ ꢌꢍꢎ ꢏ ꢍꢎ ꢁꢈꢐꢑ ꢅ ꢒꢓ ꢁ ꢏꢔ ꢐꢀ
ꢕ ꢎꢏ ꢄ ꢖ ꢌꢀꢏꢈꢏ ꢔ ꢒ ꢓꢏ ꢗꢓꢏ ꢐꢔꢘ ꢎ ꢀ ꢏꢔ ꢐꢀ
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC590A SN74HC590A
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
3.7
5.2
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
4.4
I
= −20 µA
OH
5.9
RCO, I
= −4 mA
= −6 mA
= −5.2 mA
3.98
4.3
4.3
3.84
3.84
5.34
5.34
V
OH
V = V or V
IH IL
V
OH
I
4.5 V
6 V
Q −Q , I
OH
3.98
5.48
5.48
A
H
RCO, I
OH
5.8
Q −Q , I
= −7.8 mA
5.8
A
H
OH
2 V
4.5 V
6 V
0.002
0.001
0.001
0.17
0.17
0.15
0.15
0.1
0.1
0.1
0.1
0.1
0.1
0.1
I
= 20 µA
OL
0.1
0.1
0.1
RCO, I
OL
= 4 mA
= 6 mA
= 5.2 mA
0.26
0.26
0.26
0.26
100
0.5
0.4
0.33
0.33
0.33
0.33
1000
5
V
OL
V = V or V
V
I
IH
IL
4.5 V
6 V
Q −Q , I
OL
0.4
A
H
RCO, I
OL
0.4
Q −Q , I
OL
= 7.8 mA
0.4
A
H
I
I
I
V = V
or 0
6 V
6 V
6 V
1000
10
nA
µA
µA
I
I
CC
V
O
= V
or 0
0.01
OZ
CC
CC
V = V
or 0,
I
O
= 0
8
160
80
I
CC
2 V
to 6 V
C
3
10
10
10
pF
i
5
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ꢀ ꢁꢂ ꢃꢄ ꢅ ꢂꢆ ꢇꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢂ ꢆ ꢇ ꢈ
ꢋꢌ ꢍꢎ ꢏ ꢍ ꢎ ꢁꢈ ꢐꢑ ꢅꢒ ꢓꢁ ꢏꢔ ꢐꢀ
ꢕꢎ ꢏ ꢄ ꢖ ꢌꢀꢏꢈꢏ ꢔ ꢒꢓꢏ ꢗꢓ ꢏ ꢐꢔ ꢘ ꢎꢀ ꢏꢔ ꢐꢀ
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC590A SN74HC590A
A
V
UNIT
CC
MIN
MAX
4
MIN
MAX
2.5
13
MIN
MAX
3.2
16
2 V
4.5 V
6 V
20
f
Clock frequency
Pulse duration
MHz
clock
24
16
19
2 V
125
25
200
38
155
31
4.5 V
6 V
CCLK or RCLK high or low
CCLR low
21
32
26
t
w
ns
2 V
100
20
150
30
125
25
4.5 V
6 V
17
26
21
2 V
100
20
150
30
125
25
4.5 V
6 V
CCKEN low before CCLK↑
CCLR high (inactive) before CCLK↑
17
26
21
2 V
100
20
150
30
125
25
4.5 V
6 V
t
t
Setup time
ns
ns
su
17
26
21
2 V
100
20
150
30
125
25
†
4.5 V
6 V
CCLK↑ before RCLK↑
17
26
21
2 V
50
75
60
Hold time
CCKEN low after CCLK↑
4.5 V
6 V
10
15
12
h
9
13
11
†
This setup time ensures that the register gets stable data from the counter outputs. The clocks may be tied together, in which case the register
is one clock pulse behind the counter.
6
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ꢋ ꢌꢍꢎ ꢏ ꢍꢎ ꢁꢈꢐꢑ ꢅ ꢒꢓ ꢁ ꢏꢔ ꢐꢀ
ꢕ ꢎꢏ ꢄ ꢖ ꢌꢀꢏꢈꢏ ꢔ ꢒ ꢓꢏ ꢗꢓꢏ ꢐꢔꢘ ꢎ ꢀ ꢏꢔ ꢐꢀ
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN54HC590A
FROM
(INPUT)
TO
(OUTPUT)
T
A
= 25°C
TYP
8
PARAMETER
V
UNIT
MHz
ns
CC
MIN
MAX
MIN
4
MAX
2 V
4.5 V
6 V
2.5
13
16
20
24
35
40
80
20
15
70
18
14
70
18
14
80
20
15
80
20
15
38
8
f
t
t
t
t
t
max
2 V
150
31
225
45
4.5 V
6 V
CCLK↑
CCLR↓
RCLK↑
OE↓
RCO
RCO
Q
pd
26
38
2 V
130
28
195
39
4.5 V
6 V
ns
PLH
pd
23
33
2 V
140
31
210
42
4.5 V
6 V
ns
25
36
2 V
125
30
185
37
4.5 V
6 V
Q
ns
en
28
31
2 V
125
30
185
37
4.5 V
6 V
OE↑
Q
ns
dis
28
31
2 V
75
110
22
4.5 V
6 V
15
RCO
Q
6
13
19
*
t
t
ns
2 V
38
8
60
90
4.5 V
6 V
12
18
6
10
15
* This parameter is not production tested for the SN54HC590A.
7
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ꢋꢌ ꢍꢎ ꢏ ꢍ ꢎ ꢁꢈ ꢐꢑ ꢅꢒ ꢓꢁ ꢏꢔ ꢐꢀ
ꢕꢎ ꢏ ꢄ ꢖ ꢌꢀꢏꢈꢏ ꢔ ꢒꢓꢏ ꢗꢓ ꢏ ꢐꢔ ꢘ ꢎꢀ ꢏꢔ ꢐꢀ
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN74HC590A
FROM
(INPUT)
TO
(OUTPUT)
T
A
= 25°C
TYP
8
PARAMETER
V
UNIT
MHz
ns
CC
MIN
MAX
MIN
4
MAX
2 V
4.5 V
6 V
3.2
16
19
20
24
35
40
80
20
15
70
18
14
70
18
14
80
20
15
80
20
15
38
8
f
t
t
t
t
t
max
2 V
150
30
190
38
4.5 V
6 V
CCLK↑
CCLR↓
RCLK↑
OE↓
RCO
RCO
Q
pd
26
33
2 V
130
26
165
33
4.5 V
6 V
ns
PLH
pd
22
28
2 V
140
28
175
35
4.5 V
6 V
ns
24
30
2 V
125
25
155
31
4.5 V
6 V
Q
ns
en
21
26
2 V
125
25
155
31
4.5 V
6 V
OE↑
Q
ns
dis
21
26
2 V
75
95
4.5 V
6 V
15
19
RCO
Q
6
13
16
t
t
ns
2 V
38
8
60
75
4.5 V
6 V
12
15
6
10
13
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢈ ꢉ ꢀꢁꢊ ꢃꢄ ꢅꢂ ꢆꢇ ꢈ
ꢋ ꢌꢍꢎ ꢏ ꢍꢎ ꢁꢈꢐꢑ ꢅ ꢒꢓ ꢁ ꢏꢔ ꢐꢀ
ꢕ ꢎꢏ ꢄ ꢖ ꢌꢀꢏꢈꢏ ꢔ ꢒ ꢓꢏ ꢗꢓꢏ ꢐꢔꢘ ꢎ ꢀ ꢏꢔ ꢐꢀ
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range, C = 150 pF
L
(unless otherwise noted) (see Figure 1)
SN54HC590A
FROM
(INPUT)
TO
(OUTPUT)
T
A
= 25°C
TYP
100
24
PARAMETER
V
UNIT
ns
CC
MIN
MAX
MIN
MAX
300
60
2 V
4.5 V
6 V
447
90
t
t
t
RCLK↑
Q
Q
Q
pd
20
51
77
2 V
90
200
40
300
60
4.5 V
6 V
23
OE
ns
en
19
34
51
2 V
45
210
42
315
63
*
t
4.5 V
6 V
17
ns
13
36
53
* This parameter is not production tested for the SN54HC590A.
switching characteristics over recommended operating free-air temperature range, C = 150 pF
L
(unless otherwise noted) (see Figure 1)
SN74HC590A
FROM
(INPUT)
TO
(OUTPUT)
T
A
= 25°C
TYP
100
24
PARAMETER
V
UNIT
ns
CC
MIN
MAX
MIN
MAX
300
60
2 V
4.5 V
6 V
380
76
t
pd
t
en
t
t
RCLK↑
Q
Q
Q
20
51
65
2 V
90
200
40
250
50
4.5 V
6 V
23
OE
ns
19
34
43
2 V
45
210
42
265
53
4.5 V
6 V
17
ns
13
36
45
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
250
pF
pd
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢂꢆ ꢇꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢂ ꢆ ꢇ ꢈ
ꢋꢌ ꢍꢎ ꢏ ꢍ ꢎ ꢁꢈ ꢐꢑ ꢅꢒ ꢓꢁ ꢏꢔ ꢐꢀ
ꢕꢎ ꢏ ꢄ ꢖ ꢌꢀꢏꢈꢏ ꢔ ꢒꢓꢏ ꢗꢓ ꢏ ꢐꢔ ꢘ ꢎꢀ ꢏꢔ ꢐꢀ
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
PARAMETER
R
C
S1
S2
L
L
50 pF
or
150 pF
S1
S2
t
t
t
t
Open
Closed
PZH
PZL
PHZ
PLZ
Test
Point
t
1 kΩ
en
R
L
Closed
Open
Open
Closed
Open
From Output
Under Test
t
t
1 kΩ
50 pF
C
dis
pd
L
Closed
(see Note A)
50 pF
or
150 pF
or t
−−
Open
Open
t
LOAD CIRCUIT
V
CC
Reference
Input
50%
V
CC
0 V
High-Level
Pulse
50%
50%
50%
t
t
h
su
0 V
V
CC
t
Data
Input
w
90%
90%
50%
10%
50%
10%
V
CC
0 V
Low-Level
Pulse
50%
t
t
f
r
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
V
CC
Output
Input
V
CC
50%
50%
Control
(Low-Level
Enabling)
50%
50%
0 V
V
0 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
OH
In-Phase
Output
90%
≈V
CC
Output
Waveform 1
(See Note B)
≈V
CC
50%
50%
10%
50%
10%
V
OL
10%
t
t
f
r
V
OL
OH
t
t
PLH
PHL
90%
t
t
PZH
PHZ
V
V
OH
90%
Out-of-
Phase
Output
V
50%
10%
50%
10%
Output
Waveform 2
(See Note B)
90%
50%
OL
t
t
≈0 V
f
r
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
PHL
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-89603012A
5962-8960301EA
5962-8960301FA
SN54HC590AJ
SN74HC590AD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
16
16
16
16
1
1
1
1
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
W
J
CDIP
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC590ADE4
SN74HC590ADR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
D
D
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC590ADRE4
SN74HC590ADT
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC590ADTE4
SN74HC590ADW
SN74HC590ADWG4
SN74HC590ADWR
SN74HC590ADWRG4
SN74HC590AN
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
DW
DW
DW
N
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74HC590AN3
SN74HC590ANE4
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
16
16
TBD
Call TI
Call TI
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SNJ54HC590AFK
SNJ54HC590AJ
SNJ54HC590AW
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
16
16
1
1
1
TBD
TBD
TBD
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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