SN74HCT273PWRG4 [TI]
OCTAL D-TYPE FLIP-FLOPS WITH CLEAR; 八路D型触发器与Clear
| 型号： | SN74HCT273PWRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL D-TYPE FLIP-FLOPS WITH CLEAR |
| 文件： | 总17页 (文件大小：776K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢊ ꢀꢁ ꢈꢃ ꢄꢅ ꢆꢇ ꢈꢉ
ꢋ ꢅꢆꢌꢍ ꢎꢏꢆ ꢐꢑ ꢒ ꢓ ꢍ ꢔꢑ ꢏ ꢓꢍꢋ ꢑ ꢀ
ꢕ ꢔꢆꢄ ꢅ ꢍꢒ ꢌꢖ
SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003
D
D
D
D
D
D
Operating Voltage Range of 4.5 V to 5.5 V
Outputs Can Drive Up To 10 LSTTL Loads
D
D
D
D
Inputs Are TTL-Voltage Compatible
Contain Eight D-Type Flip-Flops
Direct Clear Input
Low Power Consumption, 80-µA Max I
CC
Typical t = 12 ns
pd
4-mA Output Drive at 5 V
Applications Include:
− Buffer/Storage Registers
− Shift Registers
Low Input Current of 1 µA Max
− Pattern Generators
SN54HCT273 . . . J OR W PACKAGE
SN74HCT273 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
SN54HCT273 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
3
2
1
20 19
18
4
5
6
7
8
2D
2Q
3Q
3D
4D
8D
7D
7Q
6Q
6D
17
16
15
14
9 10 11 12 13
GND
description/ordering information
These devices are positive-edge-triggered D-type flip-flops with a common enable input. The ’HCT273 devices
are similar to the ’HCT377 devices, but feature a common clear enable (CLR) input instead of a latched clock.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not
directly related to the positive-going pulse. When CLK is at either the high or low level, the D input has no effect
at the output. The circuits are designed to prevent false clocking by transitions at CLR.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
Tube of 20
Tube of 25
Reel of 2000
Reel of 2000
Reel of 2000
Tube of 70
Reel of 2000
Reel of 250
Tube of 20
Tube of 85
Tube of 55
SN74HCT273N
SN74HCT273N
SN74HCT273DW
SN74HCT273DWR
SN74HCT273NSR
SN74HCT273DBR
SN74HCT273PW
SN74HCT273PWR
SN74HCT273PWT
SNJ54HCT273J
SOIC − DW
HCT273
SOP − NS
HCT273
HT273
−40°C to 85°C
SSOP − DB
TSSOP − PW
HT273
CDIP − J
CFP − W
LCCC − FK
SNJ54HCT273J
SNJ54HCT273W
SNJ54HCT273FK
SNJ54HCT273W
SNJ54HCT273FK
−55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
ꢗ ꢁ ꢍꢒꢀꢀ ꢋ ꢆꢄ ꢒꢖꢕ ꢔꢀ ꢒ ꢁ ꢋꢆꢒꢎ ꢘꢙ ꢚꢛ ꢜꢝꢞ ꢟꢠꢡ ꢢꢘ ꢞꢝ ꢢꢘꢣ ꢚꢢꢛ ꢑꢖ ꢋ ꢎ ꢗ ꢅꢆ ꢔꢋ ꢁ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢊ ꢀꢁꢈ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ
ꢋꢅ ꢆꢌ ꢍ ꢎ ꢏꢆ ꢐꢑꢒ ꢓꢍ ꢔ ꢑ ꢏꢓꢍ ꢋꢑ ꢀ
ꢕꢔ ꢆ ꢄ ꢅ ꢍ ꢒꢌ ꢖ
SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
CLR
L
CLK
X
D
X
H
L
L
H
L
H
↑
H
↑
H
L
X
Q
0
logic diagram (positive logic)
1D
2D
3D
4D
5D
13
6D
14
7D
17
8D
18
3
4
7
8
11
CLK
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
R
R
R
R
R
R
R
R
1
CLR
2
5
6
9
12
5Q
15
6Q
16
7Q
19
8Q
1Q
2Q
3Q
4Q
logic diagram, each flip-flop (positive logic)
C
C
D
TG
C
TG
C
Q
C
C
TG
CLK(I)
TG
C
C
C
C
R
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢊ ꢀꢁ ꢈꢃ ꢄꢅ ꢆꢇ ꢈꢉ
ꢋ ꢅꢆꢌꢍ ꢎꢏꢆ ꢐꢑ ꢒ ꢓ ꢍ ꢔꢑ ꢏ ꢓꢍꢋ ꢑ ꢀ
ꢕ ꢔꢆꢄ ꢅ ꢍꢒ ꢌꢖ
SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HCT273
MIN NOM MAX
SN74HCT273
UNIT
MIN NOM
MAX
V
V
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
V
V
= 4.5 V to 5.5 V
= 4.5 V to 5.5 V
CC
0.8
0.8
V
CC
0
0
V
V
0
0
V
V
V
CC
CC
Output voltage
V
O
CC
CC
∆t/∆v
Input transition rise/fall time
Operating free-air temperature
500
125
500
85
ns
°C
T
A
−55
−40
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HCT273 SN74HCT273
A
PARAMETER
TEST CONDITIONS
V
UNIT
V
CC
MIN
TYP
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
I
I
I
= −20 µA
= −4 mA
= 20 µA
= 4 mA
4.5 V
4.5 V
4.5 V
4.5 V
5.5 V
5.5 V
4.4 4.499
OH
OH
OL
OL
V
V
V = V or V
IH
OH
I
IL
3.98
4.30
0.001
0.17
0.1
3.7
3.84
0.1
0.26
100
8
0.1
0.4
0.1
0.33
1000
80
V = V or V
V
OL
I
IH
IL
I
I
V = V
I
or 0
1000
160
nA
I
CC
V = V
I
or 0,
I
O
= 0
µA
CC
CC
One input at 0.5 V or 2.4 V,
Other inputs at 0 or V
‡
∆I
CC
5.5 V
1.4
3
2.4
10
3
2.9
10
mA
pF
CC
4.5 V
to 5.5 V
C
10
i
‡
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or V
.
CC
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ꢞ ꢙꢣ ꢢ ꢭꢡ ꢝꢥ ꢜꢚ ꢛ ꢞ ꢝꢢ ꢘꢚ ꢢꢟꢡ ꢘ ꢙꢡ ꢛ ꢡ ꢦꢥ ꢝꢜ ꢟꢞꢘ ꢛ ꢫ ꢚꢘꢙ ꢝꢟꢘ ꢢꢝꢘ ꢚꢞꢡ ꢩ
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3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢊ ꢀꢁꢈ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ
ꢋꢅ ꢆꢌ ꢍ ꢎ ꢏꢆ ꢐꢑꢒ ꢓꢍ ꢔ ꢑ ꢏꢓꢍ ꢋꢑ ꢀ
ꢕꢔ ꢆ ꢄ ꢅ ꢍ ꢒꢌ ꢖ
SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HCT273 SN74HCT273
A
V
UNIT
CC
MIN
MAX
25
MIN
MAX
16
MIN
MAX
20
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
f
t
Clock frequency
Pulse duration
MHz
clock
28
19
23
20
18
16
14
20
17
20
17
0
30
25
24
20
30
25
30
25
0
25
22
20
17
25
21
25
21
0
CLK high or low
CLR low
ns
w
Data
t
t
Setup time before CLK↑
Hold time data after CLK↑
ns
ns
su
CLR inactive
h
0
0
0
switching characteristics over recommended operating free-air temperature range, V
L
= 5 V 0.5 V,
CC
C = 50 pF (unless otherwise noted) (see Figure 1)
SN54HCT273
= 25°C
FROM
(INPUT)
TO
(OUTPUT)
T
A
PARAMETER
V
UNIT
MAX
CC
MIN
MIN
25
TYP
31
37
15
12
17
15
8
MAX
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
16
19
f
t
t
t
MHz
50
max
28
34
29
15
34
18
19
CLR
CLR
Any
Any
Any
ns
pd
42
50
ns
PHL
t
42
22
ns
21
7
switching characteristics over recommended operating free-air temperature range, V
L
= 5 V 0.5 V,
CC
C = 50 pF (unless otherwise noted) (see Figure 1)
SN74HCT273
= 25°C
FROM
(INPUT)
TO
(OUTPUT)
T
A
PARAMETER
V
UNIT
MAX
CC
MIN
MIN
25
TYP
31
37
15
12
17
15
8
MAX
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
20
23
f
t
t
t
MHz
42
max
28
34
29
34
29
15
14
CLR
CLR
Any
Any
Any
ns
pd
36
42
ns
PHL
t
36
19
ns
17
7
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4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢊ ꢀꢁ ꢈꢃ ꢄꢅ ꢆꢇ ꢈꢉ
ꢋ ꢅꢆꢌꢍ ꢎꢏꢆ ꢐꢑ ꢒ ꢓ ꢍ ꢔꢑ ꢏ ꢓꢍꢋ ꢑ ꢀ
ꢕ ꢔꢆꢄ ꢅ ꢍꢒ ꢌꢖ
SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
30
pF
pd
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
From Output
Under Test
Test
Point
High-Level
1.3 V
1.3 V
1.3 V
Pulse
C
= 50 pF
L
t
w
(see Note A)
3 V
0 V
Low-Level
Pulse
1.3 V
LOAD CIRCUIT
3 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
1.3 V
1.3 V
t
t
PLH
PHL
90%
3 V
V
V
OH
In-Phase
Output
Reference
Input
90%
t
1.3 V
1.3 V
10%
1.3 V
10%
0 V
OL
t
r
f
f
t
t
h
su
t
t
PLH
PHL
90%
3 V
0 V
Out-of-
Phase
Output
V
V
Data
Input
OH
2.7 V
2.7 V
90%
t
1.3 V
0.3 V
1.3 V
0.3 V
1.3 V
10%
1.3 V
10%
OL
t
t
t
r
f
r
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. The outputs are measured one at a time with one input transition per measurement.
D. For clock inputs, f is measured when the input duty cycle is 50%.
max
are the same as t
E.
t
and t
PHL
.
pd
PLH
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SSOP
SSOP
Drawing
SN74HCT273DBLE
SN74HCT273DBR
OBSOLETE
ACTIVE
DB
20
20
TBD
Call TI
Call TI
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HCT273DBRE4
SN74HCT273DBRG4
SN74HCT273DW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
DB
DB
DW
DW
DW
DW
DW
DW
N
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HCT273DWE4
SN74HCT273DWG4
SN74HCT273DWR
SN74HCT273DWRE4
SN74HCT273DWRG4
SN74HCT273N
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74HCT273NE4
SN74HCT273NSR
SN74HCT273NSRE4
SN74HCT273NSRG4
SN74HCT273PW
N
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
NS
NS
NS
PW
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HCT273PWE4
SN74HCT273PWG4
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HCT273PWLE
SN74HCT273PWR
OBSOLETE TSSOP
PW
PW
20
20
TBD
Call TI
Call TI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HCT273PWRE4
SN74HCT273PWRG4
SN74HCT273PWT
PW
PW
PW
PW
PW
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HCT273PWTE4
SN74HCT273PWTG4
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HCT273DBR
SN74HCT273DWR
SN74HCT273NSR
SN74HCT273PWR
SN74HCT273PWT
SSOP
SOIC
DB
DW
NS
20
20
20
20
20
2000
2000
2000
2000
250
330.0
330.0
330.0
330.0
330.0
16.4
24.4
24.4
16.4
16.4
8.2
10.8
8.2
7.5
13.0
13.0
7.1
2.5
2.7
2.5
1.6
1.6
12.0
12.0
12.0
8.0
16.0
24.0
24.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
SO
TSSOP
TSSOP
PW
PW
6.95
6.95
7.1
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74HCT273DBR
SN74HCT273DWR
SN74HCT273NSR
SN74HCT273PWR
SN74HCT273PWT
SSOP
SOIC
DB
DW
NS
20
20
20
20
20
2000
2000
2000
2000
250
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
45.0
45.0
38.0
38.0
SO
TSSOP
TSSOP
PW
PW
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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