SN74LV374ATNS [TI]
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS; 八路边沿触发D型触发器具有三态输出
| 型号： | SN74LV374ATNS |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS |
| 文件： | 总20页 (文件大小：848K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢃ ꢈꢉ ꢀꢁꢇ ꢃꢄꢅ ꢆꢇ ꢃꢈ
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SCLS408H − APRIL 1998 − REVISED APRIL 2005
D
D
D
D
D
2-V to 5.5-V V
Operation
D
D
D
I
Supports Partial-Power-Down Mode
CC
off
Operation
Max t of 9.5 ns at 5 V
pd
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
A
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Typical V
>2.3 V at V
(Output V
Undershoot)
OHV
CC
OH
= 3.3 V, T = 25°C
A
Support Mixed-Mode Voltage Operation on
All Ports
− 1000-V Charged-Device Model (C101)
SN54LV374A . . . FK PACKAGE
SN54LV374A . . . J OR W PACKAGE
SN74LV374A . . . DB, DGV, DW, NS,
OR PW PACKAGE
SN74LV374A . . . RGY PACKAGE
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
3
2
1
20 19
18
1
20
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
1
2
3
4
5
6
7
8
9
20
8D
7D
7Q
2D
2Q
3Q
3D
4D
4
5
6
7
8
19
18
17
16
15
14
13
12
2
3
4
5
6
7
8
9
1Q
1D
2D
2Q
3Q
3D
4D
4Q
8Q
8D
7D
7Q
6Q
6D
5D
5Q
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 CLK
17
16
15 6Q
14
9 10 11 12 13
6D
10
11
GND 10
description/ordering information
The ’LV374A devices are octal edge-triggered D-type flip-flops designed for 2-V to 5.5-V V
operation.
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
QFN − RGY
SOIC − DW
Reel of 1000
Tube of 25
SN74LV374ARGYR
SN74LV374ADW
SN74LV374ADWR
SN74LV374ANSR
SN74LV374ADBR
SN74LV374APW
SN74LV374APWR
SN74LV374APWT
SN74LV374ADGVR
SN74LV374AGQNR
SNJ54LV374AJ
LV374A
LV374A
Reel of 2000
Reel of 2000
Reel of 2000
Tube of 70
SOP − NS
74LV374A
LV374A
LV374A
LV374A
LV374A
LV374A
LV374A
SSOP − DB
−40°C to 85°C
Reel of 2000
Reel of 250
Reel of 2000
Reel of 1000
Tube of 20
TSSOP − PW
TVSOP − DGV
VFBGA − GQN
CDIP − J
SNJ54LV374AJ
SNJ54LV374AW
SNJ54LV374AFK
−55°C to 125°C
CFP − W
Tube of 85
SNJ54LV374AW
SNJ54LV374AFK
LCCC − FK
Tube of 55
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢃꢈ ꢉ ꢀꢁ ꢇꢃ ꢄꢅ ꢆ ꢇꢃ ꢈ
ꢊꢋ ꢌꢈ ꢄ ꢍꢎ ꢏꢍꢐ ꢌꢑ ꢒꢏ ꢏꢍ ꢑꢍ ꢎ ꢎꢐꢌ ꢓ ꢔꢍ ꢕꢄ ꢒ ꢔꢐꢕ ꢄ ꢊ ꢔꢀ
ꢖꢒ ꢌ ꢗ ꢆ ꢐꢀꢌꢈꢌ ꢍ ꢊꢘꢌ ꢔ ꢘꢌꢀ
SCLS408H − APRIL 1998 − REVISED APRIL 2005
description/ordering information (continued)
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D)
inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the devices when they are powered down.
GQN PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
1
1Q
2
3
4
A
B
C
D
E
A
B
C
D
E
OE
7D
2Q
5D
4Q
V
8Q
8D
7Q
6D
5Q
CC
2D
1D
6Q
3Q
4D
3D
GND
CLK
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
↑
D
H
L
H
L
L
↑
L
L
X
X
Q
0
H
X
Z
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢃ ꢈꢉ ꢀꢁ ꢇꢃ ꢄꢅ ꢆꢇ ꢃꢈ
ꢊ ꢋꢌꢈꢄ ꢍꢎꢏ ꢍ ꢐꢌꢑ ꢒꢏ ꢏꢍ ꢑꢍꢎ ꢎꢐꢌ ꢓꢔ ꢍ ꢕ ꢄꢒ ꢔ ꢐꢕ ꢄꢊ ꢔꢀ
ꢖ ꢒꢌ ꢗ ꢆ ꢐꢀꢌꢈꢌ ꢍ ꢊ ꢘꢌ ꢔꢘ ꢌꢀ
SCLS408H − APRIL 1998 − REVISED APRIL 2005
logic diagram (positive logic)
1
OE
11
CLK
C1
1D
2
1Q
3
1D
To Seven Other Channels
Pin numbers shown are for the DB, DGV, DW, FK, J, NS, PW, RGY, and W packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance or
power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
(see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
(see Note 3): GQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢃꢈ ꢉ ꢀꢁ ꢇꢃ ꢄꢅ ꢆ ꢇꢃ ꢈ
ꢊꢋ ꢌꢈ ꢄ ꢍꢎ ꢏꢍꢐ ꢌꢑ ꢒꢏ ꢏꢍ ꢑꢍ ꢎ ꢎꢐꢌ ꢓ ꢔꢍ ꢕꢄ ꢒ ꢔꢐꢕ ꢄ ꢊ ꢔꢀ
ꢖꢒ ꢌ ꢗ ꢆ ꢐꢀꢌꢈꢌ ꢍ ꢊꢘꢌ ꢔ ꢘꢌꢀ
SCLS408H − APRIL 1998 − REVISED APRIL 2005
recommended operating conditions (see Note 5)
SN54LV374A
SN74LV374A
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
V
V
V
V
V
V
V
= 2 V
1.5
1.5
CC
CC
CC
CC
CC
CC
CC
CC
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
V
V
V
× 0.7
CC
CC
CC
CC
CC
CC
High-level input voltage
V
IH
× 0.7
× 0.7
× 0.7
× 0.7
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
× 0.3
× 0.3
V
V
V
× 0.3
× 0.3
× 0.3
CC
CC
CC
CC
CC
CC
V
IL
Low-level input voltage
V
V
V
V
Input voltage
0
0
0
5.5
0
0
0
5.5
I
High or low state
3-state
V
V
CC
5.5
CC
5.5
Output voltage
V
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−2
−50
−2
−8
−16
50
2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
Low-level output current
OH
OL
−8
mA
−16
50
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
8
8
mA
16
16
200
100
20
85
200
100
20
∆t/∆v Input transition rise or fall rate
ns/V
T
Operating free-air temperature
−55
125
−40
°C
A
NOTE 5: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV374A
SN74LV374A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
TYP
MAX
MIN
TYP
MAX
I
I
I
I
I
I
I
I
= −50 µA
= −2 mA
= −8 mA
= −16 mA
= 50 µA
= 2 mA
2 V to 5.5 V
2.3 V
V
−0.1
2
V
CC
−0.1
2
OH
OH
OH
OH
OL
OL
OL
OL
CC
V
V
V
OH
3 V
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
1
0.1
0.4
0.44
0.55
1
V
OL
= 8 mA
3 V
= 16 mA
4.5 V
I
I
I
I
V = 5.5 V or GND
0 to 5.5 V
5.5 V
µA
µA
µA
µA
pF
I
I
V
= V or GND
O CC
or GND,
5
5
OZ
CC
off
V = V
CC
I
O
= 0
5.5 V
20
20
I
V or V = 0 to 5.5 V
0
5
5
I
O
C
V = V
or GND
3.3 V
2.9
2.9
i
I
CC
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4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢃ ꢈꢉ ꢀꢁ ꢇꢃ ꢄꢅ ꢆꢇ ꢃꢈ
ꢊ ꢋꢌꢈꢄ ꢍꢎꢏ ꢍ ꢐꢌꢑ ꢒꢏ ꢏꢍ ꢑꢍꢎ ꢎꢐꢌ ꢓꢔ ꢍ ꢕ ꢄꢒ ꢔ ꢐꢕ ꢄꢊ ꢔꢀ
ꢖ ꢒꢌ ꢗ ꢆ ꢐꢀꢌꢈꢌ ꢍ ꢊ ꢘꢌ ꢔꢘ ꢌꢀ
SCLS408H − APRIL 1998 − REVISED APRIL 2005
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 2.5 V 0.2 V
CC
T
= 25°C
SN54LV374A SN74LV374A
A
UNIT
MIN
6
MAX
MIN
7
MAX
MIN
7
MAX
t
w
t
su
t
h
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
ns
ns
ns
5
5.5
2.5
5.5
2.5
2.5
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V 0.3 V
CC
T
= 25°C
SN54LV374A SN74LV374A
A
UNIT
MIN
5
MAX
MIN
5.5
4.5
2
MAX
MIN
5.5
4.5
2
MAX
t
w
t
su
t
h
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
ns
ns
ns
4.5
2
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
= 25°C
SN54LV374A SN74LV374A
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
t
w
t
su
t
h
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
ns
ns
ns
3
3
3
2
2
2
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
SN54LV374A SN74LV374A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
C
C
= 15 pF
= 50 pF
60*
105*
50*
50
L
L
f
t
MHz
max
50
85
40
1*
1*
1*
40
1
CLK
OE
Q
Q
Q
9.7* 16.3*
8.9* 15.9*
6.3* 12.6*
19*
19*
15*
19
19
15
pd
C
= 15 pF
ns
ns
t
t
t
1
L
en
dis
pd
1
OE
CLK
OE
Q
Q
Q
11.8
10.9
8.2
19.3
18.8
17.3
2
1
1
1
23
22
19
1
1
1
23
22
19
2
t
t
t
en
C
= 50 pF
L
OE
dis
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
ꢔ
ꢑ
ꢊ
ꢎ
ꢘ
ꢋ
ꢌ
ꢔ
ꢑ
ꢍ
ꢅ
ꢒ
ꢍ
ꢖ
ꢛ
ꢣ
ꢥ
ꢞ
ꢦ
ꢡ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢟ
ꢞ
ꢣ
ꢟ
ꢢ
ꢦ
ꢣ
ꢜ
ꢧ
ꢦ
ꢞ
ꢝ
ꢠ
ꢝꢢ ꢜ ꢛ ꢮꢣ ꢧꢚ ꢤ ꢜ ꢢ ꢞꢥ ꢝꢢ ꢯ ꢢ ꢩꢞ ꢧꢡꢢ ꢣꢙꢪ ꢋ ꢚꢤ ꢦꢤ ꢟꢙ ꢢꢦ ꢛꢜ ꢙꢛ ꢟ ꢝꢤ ꢙꢤ ꢤꢣ ꢝ ꢞꢙ ꢚꢢꢦ
ꢟ
ꢙ
ꢜ
ꢛ
ꢣ
ꢙ
ꢚ
ꢢ
ꢥ
ꢞ
ꢦ
ꢡ
ꢤ
ꢙ
ꢛ
ꢯ
ꢢ
ꢞ
ꢦ
ꢜ
ꢧ
ꢢ
ꢟ
ꢛ
ꢥ
ꢛ
ꢟ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢜ
ꢤ
ꢦ
ꢢ
ꢝ
ꢢ
ꢜ
ꢛ
ꢮ
ꢣ
ꢮ
ꢞ
ꢤ
ꢩ
ꢜ
ꢪ
ꢌ
ꢢ
ꢫ
ꢤ
ꢜ
ꢒ
ꢣ
ꢜ
ꢙ
ꢦ
ꢠ
ꢡ
ꢢ
ꢣ
ꢟ ꢚꢤ ꢣ ꢮꢢ ꢞꢦ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢧꢦ ꢞꢝ ꢠꢟꢙ ꢜ ꢬ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢪ
ꢙ
ꢜ
ꢦ
ꢢ
ꢜ
ꢢ
ꢦ
ꢯ
ꢢ
ꢜ
ꢙ
ꢚ
ꢢ
ꢦ
ꢛ
ꢮ
ꢚ
ꢙ
ꢙ
ꢞ
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢃꢈ ꢉ ꢀꢁ ꢇꢃ ꢄꢅ ꢆ ꢇꢃ ꢈ
ꢊꢋ ꢌꢈ ꢄ ꢍꢎ ꢏꢍꢐ ꢌꢑ ꢒꢏ ꢏꢍ ꢑꢍ ꢎ ꢎꢐꢌ ꢓ ꢔꢍ ꢕꢄ ꢒ ꢔꢐꢕ ꢄ ꢊ ꢔꢀ
ꢖꢒ ꢌ ꢗ ꢆ ꢐꢀꢌꢈꢌ ꢍ ꢊꢘꢌ ꢔ ꢘꢌꢀ
SCLS408H − APRIL 1998 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
SN54LV374A SN74LV374A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
80*
55
MAX
MIN
70*
50
MAX
MIN
70
50
1
MAX
C
C
= 15 pF
= 50 pF
150*
110
L
L
f
t
MHz
max
CLK
OE
Q
Q
Q
6.8* 12.7*
6.3* 11*
4.7* 10.5*
1*
15*
13*
15
13
pd
C
= 15 pF
ns
ns
t
t
t
1*
1
1
L
en
dis
pd
1* 12.5*
12.5
OE
CLK
OE
Q
Q
Q
8.3
7.7
5.9
16.2
14.5
14
1
1
1
18.5
16.5
16
1
1
1
18.5
16.5
16
t
t
t
en
C
= 50 pF
L
OE
dis
1.5
1.5
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
205*
170
SN54LV374A SN74LV374A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
130*
85
MAX
MIN
110*
75
MAX
MIN
110
75
MAX
C
C
= 15 pF
= 50 pF
L
L
f
t
MHz
max
CLK
OE
Q
Q
Q
4.9*
8.1*
7.6*
6.8*
1*
9.5*
9*
1
9.5
9
pd
C
= 15 pF
ns
ns
t
t
t
4.6*
3.4*
1*
1*
1
1
L
en
dis
pd
8*
8
OE
CLK
OE
Q
Q
Q
5.9
5.5
4
10.1
9.6
8.8
1
1
1
1
11.5
11
1
1
1
11.5
11
t
t
t
en
C
= 50 pF
L
10
10
1
OE
dis
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
= 3.3 V, C = 50 pF, T = 25°C (see Note 6)
CC
L
A
SN74LV374A
PARAMETER
UNIT
MIN
TYP
0.6
MAX
V
V
V
V
V
Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
0.8
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
−0.5
2.9
−0.8
OL
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
OH
2.31
0.99
NOTE 6: Characteristics are for surface-mount packages only.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
V
TYP
21.1
22.8
UNIT
CC
3.3 V
C
Power dissipation capacitance
Outputs enabled
C
pF
pd
5 V
ꢔ
ꢑ
ꢊ
ꢎ
ꢘ
ꢋ
ꢌ
ꢔ
ꢑ
ꢍ
ꢅ
ꢒ
ꢍ
ꢖ
ꢛ
ꢣ
ꢥ
ꢞ
ꢦ
ꢡ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢟ
ꢞ
ꢣ
ꢟ
ꢢ
ꢦ
ꢣ
ꢜ
ꢧ
ꢦ
ꢞ
ꢝ
ꢠ
ꢟ
ꢝ ꢢ ꢜ ꢛ ꢮ ꢣ ꢧꢚ ꢤ ꢜ ꢢ ꢞꢥ ꢝꢢ ꢯ ꢢ ꢩ ꢞꢧ ꢡꢢ ꢣ ꢙꢪ ꢋ ꢚꢤ ꢦꢤ ꢟꢙ ꢢꢦ ꢛꢜ ꢙꢛ ꢟ ꢝꢤ ꢙꢤ ꢤꢣ ꢝ ꢞꢙ ꢚꢢꢦ
ꢙ
ꢜ
ꢛ
ꢣ
ꢙ
ꢚ
ꢢ
ꢥ
ꢞ
ꢦ
ꢡ
ꢤ
ꢙ
ꢛ
ꢯ
ꢢ
ꢞ
ꢦ
ꢜ
ꢧ
ꢢ
ꢟ
ꢛ
ꢥ
ꢛ
ꢟ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢜ
ꢤ
ꢦ
ꢢ
ꢝ
ꢢ
ꢜ
ꢛ
ꢮ
ꢣ
ꢮ
ꢞ
ꢤ
ꢩ
ꢜ
ꢪ
ꢌ
ꢢ
ꢫ
ꢤ
ꢜ
ꢒ
ꢣ
ꢜ
ꢙ
ꢦ
ꢠ
ꢡ
ꢢ
ꢣ
ꢟ ꢚ ꢤ ꢣ ꢮꢢ ꢞꢦ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠ ꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢧꢦ ꢞ ꢝꢠꢟ ꢙꢜ ꢬ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢪ
ꢙ
ꢜ
ꢦ
ꢢ
ꢜ
ꢢ
ꢦ
ꢯ
ꢢ
ꢜ
ꢙ
ꢚ
ꢢ
ꢦ
ꢛ
ꢮ
ꢚ
ꢙ
ꢙ
ꢞ
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢃ ꢈꢉ ꢀꢁ ꢇꢃ ꢄꢅ ꢆꢇ ꢃꢈ
ꢊ ꢋꢌꢈꢄ ꢍꢎꢏ ꢍ ꢐꢌꢑ ꢒꢏ ꢏꢍ ꢑꢍꢎ ꢎꢐꢌ ꢓꢔ ꢍ ꢕ ꢄꢒ ꢔ ꢐꢕ ꢄꢊ ꢔꢀ
ꢖ ꢒꢌ ꢗ ꢆ ꢐꢀꢌꢈꢌ ꢍ ꢊ ꢘꢌ ꢔꢘ ꢌꢀ
SCLS408H − APRIL 1998 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
su
V
CC
V
CC
50% V
CC
50% V
CC
Input
Input
50% V
CC
50% V
CC
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
CC
V
CC
Output
Control
50% V
CC
50% V
CC
50% V
CC
50% V
CC
0 V
0 V
t
t
PZL
PLZ
t
t
t
PHL
PLH
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
(see Note B)
CC
V
V
+ 0.3 V
OL
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
− 0.3 V
OH
50% V
CC
50% V
50% V
CC
CC
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PLH
are the same as t
.
dis
PLZ
PZL
PHL
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
SN74LV374ADBR
SN74LV374ADBRE4
SN74LV374ADGVR
SN74LV374ADGVRE4
SN74LV374ADW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DB
20
20
20
20
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
TVSOP
TVSOP
SOIC
DB
DGV
DGV
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV374ADWE4
SN74LV374ADWR
SN74LV374ADWRE4
SN74LV374AGQNR
SOIC
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
GQN
1000
TBD
SNPB
Level-1-240C-UNLIM
SN74LV374ANSR
SN74LV374ANSRE4
SN74LV374APW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SO
NS
NS
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
QFN
PW
PW
PW
PW
PW
PW
RGY
RGY
DB
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV374APWE4
SN74LV374APWR
SN74LV374APWRE4
SN74LV374APWT
SN74LV374APWTE4
SN74LV374ARGYR
SN74LV374ARGYRG4
SN74LV374ATDB
SN74LV374ATDBR
SN74LV374ATDW
SN74LV374ATDWR
SN74LV374ATNS
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
QFN
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
SSOP
SSOP
SOIC
SOIC
SO
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
DW
NS
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
Orderable Device
SN74LV374ATNSR
SN74LV374ATPW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SO
NS
20
20
20
20
20
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
QFN
PW
PW
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV374ATPWE4
SN74LV374ATPWR
SN74LV374ATPWRE4
SN74LV374ATPWT
SN74LV374ATPWTE4
SN74LV374ATRGYR
SN74LV374ATRGYRG4
SN74LV374AZQNR
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGY
RGY
ZQN
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
QFN
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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