SN74LVC1G3157-Q1_14 [TI]
SINGLE-POLE DOUBLE-THROW ANALOG SWITCH;
| 型号： | SN74LVC1G3157-Q1_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SINGLE-POLE DOUBLE-THROW ANALOG SWITCH |
| 文件： | 总16页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC1G3157-Q1
www.ti.com ............................................................................................................................................................ SCES463E–JUNE 2003–REVISED APRIL 2008
SINGLE-POLE DOUBLE-THROW ANALOG SWITCH
1
FEATURES
•
Qualified for Automotive Applications
•
•
•
Rail-to-Rail Signal Handling
High Degree of Linearity
•
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
High Speed, Typically 0.5 ns
(VCC = 3 V, CL = 50 pF)
•
•
1.65-V to 5.5-V VCC Operation
•
•
Low On-State Resistance, Typically ≈6 Ω
(VCC = 4.5 V)
Useful for Both Analog and Digital
Applications
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
•
Specified Break-Before-Make Switching
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
1
2
3
6
5
4
B2
GND
B1
S
1
2
3
6
5
4
B2
GND
B1
S
VCC
VCC
A
A
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This single-pole double-throw (SPDT) analog switch is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G3157 can handle both analog and digital signals. The device permits signals with amplitudes of
up to VCC (peak) to be transmitted in either direction.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
1P1G3157QDBVRQ1
TOP-SIDE MARKING
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
Reel of 3000
Reel of 3000
CC50
C50
–40°C to 125°C
1P1G3157QDCKRQ1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
FUNCTION TABLE
CONTROL
INPUTS
ON
CHANNEL
L
B1
B2
H
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2008, Texas Instruments Incorporated
SN74LVC1G3157-Q1
SCES463E–JUNE 2003–REVISED APRIL 2008 ............................................................................................................................................................ www.ti.com
LOGIC DIAGRAM (POSITIVE LOGIC)
1
B2
6
3
4
A
S
B1
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
6.5
UNIT
V
VCC Supply voltage range(2)
VIN
VI/O Switch I/O voltage range(2)(3)(4)(5)
Control input voltage range(2)(3)
6.5
V
VCC + 0.5
–50
V
IIK
Control input clamp current
I/O port diode current
VIN < 0
mA
mA
mA
mA
IIOK
II/O
VI/O < 0
–50
(6)
On-state switch current
VI/O = 0 to VCC
±128
±100
165
Continuous current through VCC or GND
DBV package
DCK package
θJA
Package thermal impedance(7)
Storage temperature range
°C/W
°C
258
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) This value is limited to 5.5 V maximum.
(5) VI, VO, VA, and VBn are used to denote specific conditions for VI/O
(6) II, IO, IA, and IBn are used to denote specific conditions for II/O
(7) The package thermal impedance is calculated in accordance with JESD 51-7.
.
.
2
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Recommended Operating Conditions(1)
MIN
MAX UNIT
VCC
VI/O
VIN
1.65
5.5
VCC
5.5
V
V
V
0
0
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
V
CC × 0.75
VIH
VIL
High-level input voltage, control input
Low-level input voltage, control input
V
V
V
CC × 0.7
V
CC × 0.25
V
CC × 0.3
20
20
Δt/Δv
Input transition rise/fall time
ns/V
10
VCC = 4.5 V to 5.5 V
10
TA
–40
125
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 2003–2008, Texas Instruments Incorporated
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Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VI = 0 V,
VCC
MIN TYP(1)
MAX UNIT
IO = 4 mA
11
15
8
20
50
12
30
1.65 V
VI = 1.65 V,
VI = 0 V,
IO = –4 mA
IO = 8 mA
2.3 V
3 V
VI = 2.3 V,
VI = 0 V,
IO = –8 mA
IO = 24 mA
IO = –24 mA
IO = 30 mA
IO = –30 mA
IO = –30 mA
IA = –4 mA
IA = –8 mA
IA = –24 mA
IA = –30 mA
11
7
See Figure 1
and Figure 2
ron
On-state switch resistance(2)
9.5
20
Ω
VI = 3 V,
9
VI = 0 V,
6
7.5
12
VI = 2.4 V,
VI = 4.5 ,
4.5 V
7
7
15
1.65 V
2.3 V
3 V
140
45
On-state switch resistance
over signal range(2)(3)
0 ≤ VBn ≤ VCC
rrange
Ω
Ω
Ω
(see Figure 1 and Figure 2)
18
4.5 V
1.65 V
2.3 V
3 V
10
VBn = 1.15 V, IA = –4 mA
0.5
0.1
0.1
0.1
110
26
9
Difference in on-state
resistance between
switches(2)(4)(5)
VBn = 1.6 V,
VBn = 2.1 V,
IA = –8 mA
Δron
See Figure 1
IA = –24 mA
VBn = 3.15 V, IA = –30 mA
IA = –4 mA
4.5 V
1.65 V
2.3 V
3 V
IA = –8 mA
On-state resistance
flatness(2)(4)(6)
ron(flat)
0 ≤ VBn ≤ VCC
IA = –24 mA
IA = –30 mA
4.5 V
4
±1
±1(1)
±1
1.65 V
to 5.5 V
(7)
Ioff
Off-state switch leakage current 0 ≤ VI, VO ≤ VCC (see Figure 3)
µA
µA
µA
±0.05
IS(on)
On-state switch leakage current VI = VCC or GND, VO = Open (see Figure 4)
5.5 V
±0.1(1)
±1
0 V
to 5.5 V
IIN
Control input current
0 ≤ VIN ≤ VCC
±0.05
1
±1(1)
10
ICC
Supply current
VIN = VCC or GND
VIN = VCC – 0.6 V
5.5 V
5.5 V
µA
µA
ΔICC
Supply-current change
500
Control input
capacitance
Cin
S
5 V
5 V
2.7
5.2
pF
pF
Switch input/output
capacitance
Cio(off)
Bn
Bn
A
17.3
17.3
Switch input/output
capacitance
Cio(on)
5 V
pF
(1) TA = 25°C
(2) Measured by the voltage drop between I/O pins at the indicated current through the switch. On-state resistance is determined by the
lower of the voltages on the two (A or B) ports.
(3) Specified by design
(4) Δron = ron(max) – ron(min) measured at identical VCC, temperature, and voltage levels
(5) This parameter is characterized, but not tested in production.
(6) Flatness is defined as the difference between the maximum and minimum values of on-state resistance over the specified range of
conditions.
(7) Ioff is the same as IS(off) (off-state switch leakage current).
4
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Analog Switch Characteristics
TA = 25°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
VCC
TYP
300
UNIT
1.65 V
2.3 V
3 V
RL = 50 Ω,
fin = sine wave
(see Figure 6)
300
300
300
–54
–54
–54
–54
–57
–57
–57
–57
3
Frequency response
(switch on)(1)
A or Bn
Bn or A
MHz
4.5 V
1.65 V
2.3 V
3 V
RL = 50 Ω,
fin = 10 MHz (sine wave)
(see Figure 7)
Crosstalk
B1 or B2
B2 or B1
dB
(between switches)(2)
4.5 V
1.65 V
2.3 V
3 V
CL = 5 pF, RL = 50 Ω,
fin = 10 MHz (sine wave)
(see Figure 8)
Feedthrough attenuation
(switch off)(2)
A or Bn
Bn or A
dB
pC
%
4.5 V
3.3 V
5 V
CL = 0.1 nF, RL = 1 MΩ
(see Figure 9)
Charge injection(3)
S
A
7
1.65 V
2.3 V
3 V
0.1
VI = 0.5 Vp-p, RL = 600 Ω,
fin = 600 Hz to 20 kHz
(sine wave)
0.025
0.015
0.01
Total harmonic distortion
A or Bn
Bn or A
(see Figure 10)
4.5 V
(1) Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads –3 dB.
(2) Adjust fin voltage to obtain 0 dBm at input.
(3) Specified by design
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5 and Figure 11)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
(1)
tpd
A or Bn
S
Bn or A
Bn
2
24
13
1.2
14
0.8
7.6
5.3
0.3
5.7
3.8
ns
ns
ns
(2)
ten
7
3
3.5
2
2.5
1.5
0.5
1.7
0.8
0.5
(3)
tdis
7.5
(4)
tB-M
0.5
0.5
(1) tpd is the slower of tPLH or tPHL. Propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and
the specified load capacitance when driven by an ideal voltage source (zero output impedance).
(2) ten is the slower of tPZL or tPZH
.
(3) tdis is the slower of tPLZ or tPHZ
(4) Specified by design
.
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PARAMETER MEASUREMENT INFORMATION
V
CC
SW
1
S
V
IL
2
V
IH
V
CC
S
A
V
IL
or V
IH
1
2
B1
B2
SW
V
O
V = V or GND
I
CC
GND
I
O
VI * VO
+ Ť ŤW
r
on
IO
V
V – V
I
O
Figure 1. On-State Resistance Test Circuit
120
100
80
60
40
20
0
V
CC
= 1.65 V
V
CC
= 2.3 V
V
= 3 V
CC
V
CC
= 4.5 V
0
1
2
3
4
5
V − V
I
Figure 2. Typical ron as a Function of Input Voltage (VI) for VI = 0 to VCC
6
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PARAMETER MEASUREMENT INFORMATION (continued)
V
CC
SW
1
S
V
IL
2
V
IH
V
CC
S
V
IL
or V
IH
1
2
B1
B2
SW
V
O
A
V
I
A
GND
Condition 1: V = GND, V = V
CC
I
O
Condition 2: V = V , V = GND
I
CC
O
Figure 3. Off-State Switch Leakage-Current Test Circuit
V
CC
SW
1
S
V
IL
2
V
IH
V
CC
S
A
V
IL
or V
IH
1
2
B1
B2
SW
V
O
V
= Open
O
V
I
A
GND
V = V or GND
I
CC
Figure 4. On-State Switch Leakage-Current Test Circuit
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PARAMETER MEASUREMENT INFORMATION (continued)
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
PLH PHL
C
L
t
/t
V
LOAD
GND
R
L
PLZ PZL
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
V
CC
V
CC
V
CC
V
CC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
/2
CC
/2
CC
/2
CC
/2
CC
2 × V
2 × V
2 × V
2 × V
50 pF
50 pF
50 pF
50 pF
500 Ω
500 Ω
500 Ω
500 Ω
0.3 V
0.3 V
0.3 V
0.3 V
CC
CC
CC
CC
V
V
V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
LOAD
V
+ V
∆
OL
OL
(see Note B)
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
− V
∆
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 5. Load Circuit and Voltage Waveforms
8
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PARAMETER MEASUREMENT INFORMATION (continued)
V
CC
SW
1
S
V
IL
2
V
IH
V
CC
S
A
V
IL
or V
IH
1
2
B1
B2
SW
V
O
R
L
50 Ω
GND
f
in
50 Ω
Figure 6. Frequency Response (Switch On)
S
TEST CONDITION
20log (V /V )
V
IL
V
V
10 O2
I
CC
20log (V /V )
V
IH
10 O1
I
CC
S
V
IL
or V
IH
V
B1
B1
f
in
V
B2
A
Analyzer
B2
GND
R
50 Ω
L
50 Ω
Figure 7. Crosstalk (Between Switches)
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PARAMETER MEASUREMENT INFORMATION (continued)
V
CC
SW
1
S
V
IL
2
V
IH
V
CC
S
A
V
IL
or V
IH
1
2
B1
B2
SW
Analyzer
R
L
50 Ω
GND
f
in
50 Ω
Figure 8. Feedthrough
V
CC
CC
V
S
1
2
B1
B2
R
GEN
Logic
Input
SW
V
GE
A
V
OUT
GND
R
L
C
L
R /C = 1 MΩ/100 pF
L
L
Logic
Input
OFF
ON
OFF
∆V
OUT
V
OUT
Q = (∆V )(C )
OUT L
Figure 9. Charge-Injection Test
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PARAMETER MEASUREMENT INFORMATION (continued)
V
CC
SW
1
S
V
IL
2
V
IH
V
CC
S
A
V
IL
or V
IH
1
2
B1
B2
10 µF
SW
R
V
O
C
L
L
10 kΩ
50 pF
GND
V /2
CC
f
in
600 Ω
V
CC
V
CC
V
CC
V
CC
= 1.65 V, V = 1.4 V
I
P-P
P-P
P-P
P-P
= 2.30 V, V = 2.0 V
I
= 3.00 V, V = 2.5 V
I
= 4.50 V, V = 4.0 V
I
Figure 10. Total Harmonic Distortion
V
CC
CC
V
S
B1
B2
V = V /2
I
CC
V
O
A
GND
V
S
R
L
C
L
R /C = 50 Ω/35 pF
L
L
V
O
0.9 y V
O
t
B-M
Figure 11. Break-Before-Make Internal Timing
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Jul-2009
PACKAGING INFORMATION
Orderable Device
1P1G3157QDBVRQ1
1P1G3157QDCKRQ1
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
6
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
DCK
6
3000 Green (RoHS &
no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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OTHER QUALIFIED VERSIONS OF SN74LVC1G3157-Q1 :
Catalog: SN74LVC1G3157
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
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