SN74LVC1G66DCKR [TI]
SINGLE BILATERAL ANALOG SWITCH; 单双边模拟开关
| 型号： | SN74LVC1G66DCKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SINGLE BILATERAL ANALOG SWITCH |
| 文件： | 总17页 (文件大小：386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢀꢊ ꢁꢈ ꢄ ꢋ ꢌꢊ ꢄꢍꢎ ꢋꢏꢍꢄ ꢍꢁꢍ ꢄꢐ ꢈ ꢀ ꢑꢊ ꢎꢆ ꢒ
SCES323H − JUNE 2001 − REVISED SEPTEMBER 2003
DBV OR DCK PACKAGE
(TOP VIEW)
D
Available in the Texas Instruments
NanoStar and NanoFree Packages
D
D
D
D
D
D
D
D
D
1.65-V to 5.5-V V
Operation
CC
1
2
3
5
4
A
B
GND
V
CC
Inputs Accept Voltages to 5.5 V
C
Max t of 0.8 ns at 3.3 V
pd
High On-Off Output Voltage Ratio
High Degree of Linearity
YEA, YEP, YZA, OR YZP PACKAGE
(BOTTOM VIEW)
High Speed, Typically 0.5 ns
(V
= 3 V, C = 50 pF)
CC
L
3 4
2
GND
B
C
V
Low On-State Resistance, Typically ≈5.5 Ω
(V = 4.5 V)
1 5
A
CC
CC
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This single analog switch is designed for 1.65-V to 5.5-V V
operation.
CC
The SN74LVC1G66 can handle both analog and digital signals. The device permits signals with amplitudes of
up to 5.5 V (peak) to be transmitted in either direction.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
‡
NanoStar − WCSP (DSBGA)
0.17-mm Small Bump − YEA
SN74LVC1G66YEAR
SN74LVC1G66YZAR
SN74LVC1G66YEPR
SN74LVC1G66YZPR
NanoFree − WCSP (DSBGA)
0.17-mm Small Bump − YZA (Pb-free)
−40°C to 85°C
Reel of 3000
_ _ _C6_
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
Reel of 3000
Reel of 250
Reel of 3000
SN74LVC1G66DBVR
SN74LVC1G66DBVT
SN74LVC1G66DCKR
SOT (SOT-23) − DBV
SOT (SC-70) − DCK
C66_
C6_
−40°C to 85°C
Reel of 250
SN74LVC1G66DCKT
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,
and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCES323H − JUNE 2001 − REVISED SEPTEMBER 2003
description/ordering information (continued)
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
FUNCTION TABLE
CONTROL
INPUT
(C)
SWITCH
L
OFF
ON
H
logic diagram (positive logic)
1
2
B
A
C
4
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
CC
Input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
I
Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
I/O
CC
Control input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
I
I/O port diode current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
IOK I/O
I/O CC
On-state switch current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
T
I/O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Package thermal impedance, θ (see Note 4): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
JA
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 132°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground, unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 5.5 V maximum.
4. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCES323H − JUNE 2001 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 5)
MIN
1.65
0
MAX
UNIT
V
V
V
Supply voltage
I/O port voltage
5.5
CC
V
CC
V
I/O
V
V
V
V
V
V
V
V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
V
× 0.65
CC
CC
CC
CC
CC
CC
CC
CC
CC
V
V
V
× 0.7
× 0.7
× 0.7
CC
CC
CC
V
High-level input voltage, control input
V
IH
= 4.5 V to 5.5 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
V
× 0.35
CC
V
V
V
× 0.3
× 0.3
× 0.3
5.5
20
CC
CC
CC
V
V
Low-level input voltage, control input
Control input voltage
V
V
IL
= 4.5 V to 5.5 V
0
I
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
20
∆t/∆v
Input transition rise/fall time
ns/V
10
= 4.5 V to 5.5 V
10
T
A
Operating free-air temperature
−40
85
°C
NOTE 5: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
30
UNIT
V
CC
I
S
I
S
I
S
I
S
I
S
I
S
I
S
I
S
= 4 mA
= 8 mA
= 24 mA
= 32 mA
= 4 mA
= 8 mA
= 24 mA
= 32 mA
1.65 V
2.3 V
3 V
12
9
V = V
or GND,
I
CC
IH
20
V
C
= V
r
On-state switch resistance
Ω
on
7.5
5.5
74.5
20
15
(see Figures 1 and 2)
4.5 V
1.65 V
2.3 V
3 V
10
100
30
V = V
to GND,
I
CC
IH
V
C
= V
r
I
Peak on resistance
Ω
on(p)
11.5
7.5
20
(see Figures 1 and 2)
4.5 V
15
V = V
CC
and V = GND or
O
1
I
V = GND and V = V
,
Off-state switch leakage current
5.5 V
µA
I
V
O
CC
S(off)
†
0.1
= V (see Figure 3)
C
IL
1
†
V = V
CC
or GND, V = V , V = Open
IH
I
C
O
I
I
I
On-state switch leakage current
Control input current
Supply current
5.5 V
5.5 V
5.5 V
µA
µA
µA
S(on)
(see Figure 4)
0.1
1
†
V
= V
or GND
I
C
CC
0.1
10
V
V
= V
= V
or GND
− 0.6 V
CC
C
CC
†
1
∆I
Supply current change
5.5 V
5 V
500
µA
pF
pF
pF
CC
C
CC
C
C
C
Control input capacitance
Switch input/output capacitance
Switch input/output capacitance
2
6
ic
5 V
io(off)
io(on)
5 V
13
†
T
A
= 25°C
3
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SCES323H − JUNE 2001 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 5)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
V
= 5 V
CC
0.15 V
CC
0.2 V
CC
0.3 V
CC
0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX
MIN MAX
MIN MAX
MIN
MAX
†
‡
t
t
t
A or B
B or A
A or B
A or B
2
12
10
1.2
6.5
6.9
0.8
5
0.6
4.2
5
ns
ns
ns
pd
en
C
C
2.5
2.2
1.9
1.4
1.8
2
1.5
1.4
§
6.5
dis
†
t
and t
PHL
are the same as t . The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and
pd
PLH
the specified load capacitance when driven by an ideal voltage source (zero output impedance).
‡
§
t
t
and t
and t
are the same as t
are the same as t
.
en
PZL
PLZ
PZH
PHZ
.
dis
analog switch characteristics, T = 25°C
A
FROM
TO
(OUTPUT)
PARAMETER
(INPUT)
TEST CONDITIONS
V
CC
TYP
UNIT
1.65 V
2.3 V
3 V
35
120
175
195
>300
>300
>300
>300
35
C
= 50 pF, R = 600 Ω,
L
L
f
in
= sine wave
(see Figure 6)
¶
4.5 V
1.65 V
2.3 V
3 V
Frequency response
(switch ON)
A or B
B or A
A or B
B or A
MHz
C
= 5 pF, R = 50 Ω,
L
L
f
in
= sine wave
(see Figure 6)
4.5 V
1.65 V
2.3 V
3 V
C
= 50 pF, R = 600 Ω,
50
L
L
Crosstalk
C
mV
f
in
= 1 MHz (square wave)
(control input to signal output)
70
(see Figure 7)
4.5 V
1.65 V
2.3 V
3 V
100
−58
−58
−58
−58
−42
−42
−42
−42
0.1
C
= 50 pF, R = 600 Ω,
= 1 MHz (sine wave)
L
L
f
in
(see Figure 8)
#
4.5 V
1.65 V
2.3 V
3 V
Feed-through attenuation
(switch OFF)
A or B
dB
C
= 5 pF, R = 50 Ω,
L
L
f
in
= 1 MHz (sine wave)
(see Figure 8)
4.5 V
1.65 V
2.3 V
3 V
C
= 50 pF, R = 10 kΩ,
L
L
0.025
0.015
0.01
f
in
= 1 kHz (sine wave)
(see Figure 9)
4.5 V
Sine-wave distortion
A or B
B or A
%
1.65 V
2.3 V
3 V
0.15
0.025
0.015
0.01
C
= 50 pF, R = 10 kΩ,
L
L
f
in
= 10 kHz (sine wave)
(see Figure 9)
4.5 V
¶
#
Adjust f voltage to obtain 0 dBm at output. Increase f frequency until dB meter reads −3 dB.
in
Adjust f voltage to obtain 0 dBm at input.
in
in
4
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SCES323H − JUNE 2001 − REVISED SEPTEMBER 2003
operating characteristics, T = 25°C
A
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
V
= 5 V
CC
TYP
CC
TYP
CC
TYP
CC
TYP
11
PARAMETER
TEST CONDITIONS
UNIT
C
Power dissipation capacitance f = 10 MHz
8
9
9
pF
pd
5
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SCES323H − JUNE 2001 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
V
CC
B or A
A or B
V = V
I CC
or GND
V
O
C
V
IH
V
C
(ON)
GND
I
S
VI * VO
ron
+
W
IS
V
V − V
I
O
Figure 1. On-State Resistance Test Circuit
100
V
CC
= 1.65 V
V
CC
= 2.3 V
V
CC
= 3.0 V
10
V
CC
= 4.5 V
1
0.0
0.5
1.0
1.5
2.0
2.5
− V
3.0
3.5
4.0
4.5
V
IN
Figure 2. Typical r as a Function of Input Voltage (V ) for V = 0 to V
CC
on
I
I
6
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SCES323H − JUNE 2001 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
CC
V
B or A
A or B
V
I
A
V
O
C
V
IL
V
C
(OFF)
GND
Condition 1: V = GND, V = V
CC
I
O
Condition 2: V = V , V = GND
I
CC
O
Figure 3. Off-State Switch Leakage-Current Test Circuit
V
CC
CC
V
B or A
A or B
A
V = V
I CC
or GND
V
O
V
O
= Open
C
V
IH
V
C
(ON)
GND
Figure 4. On-State Leakage-Current Test Circuit
7
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SCES323H − JUNE 2001 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
LOAD
Open
S1
R
L
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
PLH PHL
/t
C
L
t
V
R
PLZ PZL
LOAD
GND
L
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
C
R
L
V
LOAD
L
∆
V
I
t /t
r f
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
5 V 0.5 V
V
CC
V
CC
V
CC
V
CC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
CC
V
CC
V
CC
V
CC
/2
/2
/2
/2
2 × V
2 × V
2 × V
2 × V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
su
h
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
V
0 V
t
t
t
t
t
PHL
PZL
PLZ
+ V
PLH
PHL
Output
Waveform 1
V
/2
OH
LOAD
V
V
V
M
Output
M
V
V
M
S1 at V
(see Note B)
V
LOAD
OL
∆
V
OL
V
OL
t
PLH
t
t
PZH
PHZ
− V
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
V
M
OH
∆
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 5. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢉ
ꢀꢊ ꢁꢈ ꢄ ꢋ ꢌꢊ ꢄꢍꢎ ꢋꢏꢍꢄ ꢍꢁꢍ ꢄꢐ ꢈ ꢀ ꢑꢊ ꢎꢆ ꢒ
SCES323H − JUNE 2001 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
CC
V
0.1 µF
B or A
A or B
C
V
O
R
L
C
L
V
IH
50 Ω
f
V
C
in
(ON)
GND
V
CC
/2
R /C : 600 Ω/50 pF
L
L
R /C : 50 Ω/5 pF
L
L
Figure 6. Frequency Response (Switch ON)
V
CC
CC
V
R
in
600 Ω
B or A
A or B
C
V
CC
/2
V
O
R
600 Ω
C
L
L
50 pF
V
C
GND
V
CC
/2
50 Ω
Figure 7. Crosstalk (Control Input − Switch Output)
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉꢉ
ꢀ ꢊꢁ ꢈꢄ ꢋ ꢌ ꢊ ꢄ ꢍꢎ ꢋꢏ ꢍꢄ ꢍꢁ ꢍꢄ ꢐꢈ ꢀ ꢑꢊ ꢎ ꢆꢒ
SCES323H − JUNE 2001 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
CC
V
0.1 µF
50 Ω
B or A
A or B
C
V
O
C
R
R
L
L
L
V
IL
V
C
f
in
(OFF)
GND
V
CC
/2
V
CC
/2
R /C : 600 Ω/50 pF
L
L
R /C : 50 Ω/5 pF
L
L
Figure 8. Feed-Through (Switch OFF)
V
CC
CC
V
10 µF
10 µF
B or A
A or B
C
V
O
C
R
10 kΩ
L
L
V
IH
50 pF
600 Ω
V
C
f
in
(ON)
GND
V
CC
/2
V
CC
V
CC
V
CC
V
CC
= 1.65 V, V = 1.4 V
P-P
I
= 2.3 V, V = 2 V
I
P-P
= 3 V, V = 2.5 V
I
P-P
P-P
= 4.5 V, V = 4 V
I
Figure 9. Sine-Wave Distortion
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS025C – FEBRUARY 1997 – REVISED FEBRUARY 2002
DCK (R-PDSO-G5)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,10
0,65
5
4
0,13 NOM
1,40 2,40
1,10 1,80
1
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
0,10
1,10
0,80
0,10
0,00
4093553-2/D 01/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-203
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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