SN74LVC1GX04-EP [TI]
CRYSTAL OSCILLATOR DRIVER; 晶体振荡器驱动器
| 型号： | SN74LVC1GX04-EP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CRYSTAL OSCILLATOR DRIVER |
| 文件： | 总15页 (文件大小：442K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC1GX04-EP
CRYSTAL OSCILLATOR DRIVER
www.ti.com
SGDS029–SEPTEMBER 2007
1
FEATURES
2
•
Controlled Baseline
•
•
•
Low Power Consumption, 10 μA Max ICC
–
–
–
One Assembly
±24 mA Output Drive at 3.3 V
One Test Site
Ioff Supports Partial-Power-Down Mode
Operation
One Fabrication Site
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
•
Enhanced Diminishing Manufacturing Sources
(DMS) Support
ESD Protection Exceeds JESD 22
•
•
•
Enhanced Product-Change Notification
(1)
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
Qualification Pedigree
Available in Texas Instruments NanoStar™
and NanoFree™ Packages
1000-V Charged-Device Model (C101)
•
•
•
Supports 5-V VCC Operation
DRL PACKAGE
(TOP VIEW)
Inputs Accept Voltages to 5.5 V
One Unbuffered Inverter (SN74LVC1GU04) and
One Buffered Inverter (SN74LVC1G04)
Y
1
2
3
6
5
4
NC
GND
X1
VCC
X2
•
Suitable for Commonly Used Clock
Frequencies:
–
15 kHz, 3.58 MHz, 4.43 MHz, 13 MHz,
25 MHz, 26 MHz, 27 MHz, 28 MHz
See mechanical drawings for dimensions.
NC – No internal connection
•
Max tpd of 3.7 ns at 3.3 V
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
DESCRIPTION/ORDERING INFORMATION
The SN74LVC1GX04 is designed for 1.65-V to 5.5-V VCC operation. This device incorporates the
SN74LVC1GU04 (inverter with unbuffered output) and the SN74LVC1G04 (inverter) functions into a single
device. The LVC1GX04 is optimized for use in crystal oscillator applications.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING(3)
–55°C to 125°C SOT (SOT-553) – DRL
Reel of 4000 CLVC1GX04MDRLREP CDD
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DRL: The actual top-side marking has one additional character that designates the assembly/test site.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
SN74LVC1GX04-EP
CRYSTAL OSCILLATOR DRIVER
www.ti.com
SGDS029–SEPTEMBER 2007
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
X1 and X2 can be connected to a crystal or resonator in oscillator applications. The device provides an additional
buffered inverter (Y) for signal conditioning (see Figure 3). The additional buffered inverter improves the signal
quality of the crystal oscillator output by making it rail to rail.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff (Y output only). The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
OUTPUTS
X2
INPUT
X1
Y
H
L
H
L
L
H
LOGIC DIAGRAM (POSITIVE LOGIC)
6
4
Y
3
X1
X2
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
6.5
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to Y output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
6.5
V
VO
VO
IIK
6.5
V
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–50
–50
mA
mA
mA
mA
°C/W
°C
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
Package thermal impedance(4)
Storage temperature range
±50
±100
142
θJA
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SN74LVC1GX04-EP
CRYSTAL OSCILLATOR DRIVER
www.ti.com
SGDS029–SEPTEMBER 2007
Recommended Operating Conditions(1)
MIN
MAX UNIT
Operating
1.65
5.5
VCC
Supply voltage
Data retention only
Crystal oscillator use
VCC = 1.65 V to 5.5 V
VCC = 1.65 V to 5.5 V
1.5
2
V
VIH
VIL
VI
High-level input voltage
Low-level input voltage
Input voltage
0.75 × VCC
V
0.25 × VCC
V
V
0
0
0
5.5
VCC
5.5
–4
X2, Y
VO
Output voltage
V
Y output only, Power-down mode, VCC = 0 V
VCC = 1.65 V
VCC = 2.3 V
–8
IOH
High-level output current
–16
–24
–32
4
mA
VCC = 3 V
VCC = 4.5 V
VCC = 1.65 V
VCC = 2.3 V
8
IOL
Low-level output current
16
mA
VCC = 3 V
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ±0.5 V
20
Δt/Δv Input transition rise or fall rate
10
ns/V
10
TA
Operating free-air temperature
–55
125
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 2007, Texas Instruments Incorporated
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CRYSTAL OSCILLATOR DRIVER
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SGDS029–SEPTEMBER 2007
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 5.5 V
1.65 V
MIN TYP(1) MAX UNIT
IOH = –100 μA
IOH = –4 mA
VCC – 0.1
1.2
1.9
2.4
2.3
3.8
IOH = –8 mA
2.3 V
VOH
VI = 5.5 V or GND
V
V
IOH = –16 mA
IOH = –24 mA
IOH = –32 mA
IOL = 100 μA
IOL = 4 mA
3 V
4.5 V
1.65 V to 5.5 V
1.65 V
0.1
0.45
0.3
IOL = 8 mA
2.3 V
VOL
VI = 5.5 V or GND
IOL = 16 mA
0.4
3 V
IOL = 24 mA
0.63
0.70
±5
IOL = 32 mA
4.5 V
0 to 5.5 V
0
II
X1
VI = 5.5 V or GND
VI or VO = 5.5 V
VI = 5.5 V or GND,
VI = VCC or GND
μA
μA
μA
pF
Ioff
ICC
Ci
X1, Y
±10
10
IO = 0
1.65 V to 5.5 V
3.3 V
7
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2)
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX MIN MAX
X2
Y(1)
0.8
2
3.7
7.8
0.8
2
3.2
5
tpd
X1
ns
(1) X2 – no external load
Operating Characteristics
TA = 25°C
VCC = 3.3 V
TYP
VCC = 5 V
TYP
TEST
CONDITIONS
PARAMETER
UNIT
Cpd
Power dissipation capacitance
f = 10 MHz
24
35
pF
4
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SN74LVC1GX04-EP
CRYSTAL OSCILLATOR DRIVER
www.ti.com
SGDS029–SEPTEMBER 2007
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
PLH PHL
C
L
t
/t
V
LOAD
GND
R
L
PLZ PZL
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
V
V
3 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
/2
/2
2 × V
2 × V
6 V
2 × V
CC
15 pF
15 pF
15 pF
15 pF
1 MΩ
1 MΩ
1 MΩ
1 MΩ
0.15 V
0.15 V
0.3 V
CC
CC
CC
V
CC
CC
CC
1.5 V
/2
V
CC
V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
LOAD
V
+ V
∆
OL
OL
(see Note B)
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
- V
∆
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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CRYSTAL OSCILLATOR DRIVER
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SGDS029–SEPTEMBER 2007
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
PLH PHL
C
L
t
/t
V
LOAD
GND
R
L
PLZ PZL
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
V
V
3 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
/2
/2
2 × V
2 × V
6 V
2 × V
CC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
V
CC
CC
CC
1.5 V
/2
V
CC
V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
LOAD
V
+ V
∆
OL
OL
(see Note B)
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
- V
∆
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
6
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SN74LVC1GX04-EP
CRYSTAL OSCILLATOR DRIVER
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SGDS029–SEPTEMBER 2007
APPLICATION INFORMATION
Figure 3 shows a typical application of the SN74LVC1GX04 in a Pierce oscillator circuit. The buffered inverter
(SN74LVC1G04 portion) produces a rail-to-rail voltage waveform. The recommended load for the crystal shown
in this example is 16 pF. The value of the recommended load (CL) can be found in the crystal manufacturer's
data sheet.
Values of C1 and C2 are chosen so that
and C1 ≡ C2. Rs is the current-limiting resistor, and the
value depends on the maximum power dissipation of the crystal. Generally, the recommended value of Rs is
specified in the crystal manufacturer's data sheet and, usually, this value is approximately equal to the reactance
of C2 at resonance frequency, i.e.,
. RF is the feedback resistor that is used to bias the inverter in the
linear region of operation. Usually, the value is chosen to be within 1 MΩ to 10 MΩ.
SN74LVC1GU04
Portion
SN74LVC1G04
Portion
Y
X2
X1
C
LOAD
R
LOAD
R
F
2.2 MΩ
R
s
1 kΩ
C
L
16 pF
C
1
32 pF
C
2
32 pF
a) Logic Diagram View
Figure 3. Oscillator Circuit
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CRYSTAL OSCILLATOR DRIVER
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SGDS029–SEPTEMBER 2007
APPLICATION INFORMATION
6
Y
1
NC
C
LOAD
R
LOAD
2
5
GND
V
CC
X1
X2
3
4
R
F
2.2 MΩ
R
C
1 kΩ
s
C = 16 pF
L
C
1
32 pF
32 pF
2
b) Oscillator Circuit in DBV or DCK Pinout
Figure 3. Oscillator Circuit (continued)
Practical Design Tips
•
The open-loop gain of the unbuffered inverter decreases as power-supply voltage decreases. This decreases
the closed-loop gain of the oscillator circuit. The value of Rs can be decreased to increase the closed-loop
gain, while maintaining the power dissipation of the crystal within the maximum limit.
•
•
•
Rs and C2 form a low-pass filter and reduce spurious oscillations. Component values can be adjusted, based
on the desired cutoff frequency.
C2 can be increased over C1 to increase the phase shift and help in start-up of the oscillator. Increasing C2
may affect the duty cycle of the output voltage.
At high frequency, phase shift due to Rs becomes significant. In this case, Rs can be replaced by a capacitor
to reduce the phase shift.
8
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SN74LVC1GX04-EP
CRYSTAL OSCILLATOR DRIVER
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SGDS029–SEPTEMBER 2007
APPLICATION INFORMATION
Testing
After the selection of proper component values, the oscillator circuit should be tested using these components.
To ensure that the oscillator circuit performs within the recommended operating conditions, follow these steps:
1. Without a crystal, the oscillator circuit should not oscillate. To check this, the crystal can be replaced by its
equivalent parallel-resonant resistance.
2. When the power-supply voltage drops, the closed-loop gain of the oscillator circuit reduces. Ensure that the
circuit oscillates at the appropriate frequency at the lowest VCC and highest VCC
.
3. Ensure that the duty cycle, start-up time, and frequency drift over time is within the system requirements.
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
CLVC1GX04MDRLREP
V62/07632-01XE
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT
DRL
6
4000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOT
DRL
6
4000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1GX04-EP :
Catalog: SN74LVC1GX04
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Mar-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CLVC1GX04MDRLREP
SOT
DRL
6
4000
180.0
8.4
1.98
1.78
0.69
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Mar-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT DRL
SPQ
Length (mm) Width (mm) Height (mm)
202.0 201.0 28.0
CLVC1GX04MDRLREP
6
4000
Pack Materials-Page 2
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